CN111751183A - Sample table column and manufacturing method thereof - Google Patents
Sample table column and manufacturing method thereof Download PDFInfo
- Publication number
- CN111751183A CN111751183A CN202010630887.8A CN202010630887A CN111751183A CN 111751183 A CN111751183 A CN 111751183A CN 202010630887 A CN202010630887 A CN 202010630887A CN 111751183 A CN111751183 A CN 111751183A
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- plane
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- side walls
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
- G01N2001/2866—Grinding or homogeneising
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
- G01N2001/2873—Cutting or cleaving
Abstract
The embodiment of the application provides a sample table post and a manufacturing method thereof, the sample table post can be provided with a side plane, the top is provided with a fixed plane and a side wall, the side wall is positioned on other sides of the fixed plane except the side plane, the fixed plane is used for fixing a chip to be tested, when the chip to be tested is fixed on the fixed plane, the side wall can play a certain protection role on the chip to be tested, so that the chip to be tested is more reliably fixed, the processing and testing of the chip are facilitated, meanwhile, the position of the sample table post is easy to recognize due to the existence of the side wall, and the automatic fixing of the chip to be tested is facilitated.
Description
Technical Field
The present disclosure relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a sample pillar and a manufacturing method thereof.
Background
After the chip is prepared, an interface sample can be prepared to obtain the internal structure of the chip. Specifically, the side wall of the chip can be ground or cut to obtain a longitudinal section, and the longitudinal circuit structure in the chip can be embodied in the section, so that the chip can be detected.
At present, the chip can be stuck to the top end of the sample pillar, and then the side wall of the chip is ground or cut to obtain a section to be detected, so as to detect the section. However, the current pasting mode is not reliable enough, and the chip is easy to fall off, which is not beneficial to the processing and testing of the chip.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a sample stage and a method for manufacturing the same, which improve reliability of chip attachment by handling and testing chips.
In order to achieve the purpose, the technical scheme is as follows:
the present embodiments provide a sample stage column, the sample stage column having a side plane; the top of the sample table column is provided with a fixed plane and side walls, the side walls are located on the other sides of the fixed plane except the side plane, and the fixed plane is used for fixing a chip to be tested.
Optionally, the side walls are located on two opposite sides of the fixing plane, or two adjacent sides.
Optionally, when the side walls are located on two opposite sides of the fixing plane, the extending direction of the side walls is perpendicular to the side plane, and the surface of the side walls adjacent to the fixing plane is a plane.
Optionally, the side wall surrounds the fixing plane, an opening is formed in the plane where the side plane is located, and when the chip to be tested is fixed in the fixing plane, the side wall of one side of the chip to be tested is exposed through the opening.
Optionally, a groove is further formed in the region where the fixing plane is located.
The embodiment of the application also provides a manufacturing method of the sample pillar, which comprises the following steps:
providing a sample stage post; the sample stage post has a side plane;
etching the top of the sample stage column to form a fixed plane and a side wall on the top of the sample stage column; the side walls are located on the other sides of the fixing plane except the side plane, and the fixing plane is used for fixing a chip to be tested.
Optionally, the side walls are located on two opposite sides of the fixing plane, or two adjacent sides.
Optionally, when the side walls are located on two opposite sides of the fixing plane, the extending direction of the side walls is perpendicular to the side plane, and the surface of the side walls adjacent to the fixing plane is a plane.
Optionally, the side wall surrounds the fixing plane, an opening is formed in the plane where the side plane is located, and when the chip to be tested is fixed in the fixing plane, the side wall of one side of the chip to be tested is exposed through the opening.
Optionally, the method further includes:
and etching the fixed plane to form a groove.
Optionally, the top of the sample pillar is etched by using an ion etching process.
The embodiment of the application provides a sample table post and a manufacturing method thereof, the sample table post can be provided with a side plane, the top is provided with a fixed plane and a side wall, the side wall is positioned on other sides of the fixed plane except the side plane, the fixed plane is used for fixing a chip to be tested, namely, when the chip to be tested is fixed on the fixed plane, the side wall can play a certain protection role on the chip to be tested, therefore, the chip to be tested is more reliable in fixation, the processing and testing of the chip are facilitated, meanwhile, the position of the sample table post is easy to recognize due to the existence of the side wall, and therefore, the automatic fixation of the chip to be tested is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a sample pillar provided in an embodiment of the present application;
FIG. 2 is a schematic view of a primary sample stage in an embodiment of the present application;
FIG. 3 is a schematic view of another sample stage provided in an embodiment of the present application;
FIG. 4 is a schematic view of yet another sample stage provided by an embodiment of the present application;
FIG. 5 is a schematic view of yet another sample stage provided by an embodiment of the present application;
FIG. 6 is a schematic view of yet another sample stage provided by an embodiment of the present application;
fig. 7 is a schematic diagram of a method for manufacturing a sample pillar according to an embodiment of the present disclosure.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
At present, the chip can be adhered to the top end of the sample stand column, the sample stand column is usually etched to form a plane on the top end, the chip is adhered to the plane on the top end of the sample stand column, then the side wall of the chip can be ground or cut to obtain a section to be detected, and therefore the section can be detected. However, the chip is placed on the top of the sample stage by the adhering method, and the chip is likely to fall off due to the risk of being touched by mistake in the subsequent operation, which is not favorable for the test of the processing of the chip.
Based on the technical problem, the embodiment of the application provides a sample table post and a manufacturing method thereof, the sample table post can be provided with a side plane, the top of the sample table post is provided with a fixed plane and a side wall, the side wall is located on the other sides of the fixed plane except the side plane, and the fixed plane is used for fixing a chip to be tested, namely, when the chip to be tested is fixed on the fixed plane, the side wall can play a certain protection role on the chip to be tested, so that the chip to be tested is more reliably fixed, the processing and testing of the chip are facilitated, and meanwhile, the position of the sample table post is easy to identify due to the existence of the side wall, and the automatic fixing of the chip to be tested.
For better understanding of the technical solutions and effects of the present application, the following detailed description will be made of specific embodiments with reference to the accompanying drawings.
Referring to fig. 1, a schematic structural diagram of a sample column according to an embodiment of the present disclosure is shown, in which fig. 1(b) is a cross-sectional view of the sample column shown in fig. 1(a) along direction AA.
The sample pillars (finger)100 are raised structures on the plane, a plurality of sample pillars 100 in an array form can be formed on the plane, each sample pillar 100 can be fixed with a chip to be tested, and then a plurality of chips to be tested on the sample pillars can be processed at the same time and detected in the same batch, so that the chip detection efficiency is improved. The material of the sample stage column may be copper or other materials.
In the embodiment of the application, interface sample preparation can be performed after the chip preparation is completed, wherein the chip can be an area with an independent function in a wafer, and during the specific implementation, a wafer block (chunk) obtained by cutting the wafer can be used as a chip to be detected, and then the chip to be detected can be processed and detected.
The sample stage 100 may have a side plane 101 for processing a side surface of a chip to be tested fixed on the sample stage from the side plane, for example, grinding a side wall of the chip to be tested with sand paper, thereby obtaining a section to be tested of the chip to be tested, and detecting the section to be tested, thereby obtaining characteristics of a circuit structure inside the chip. The top of the sample stage 100 may have a fixing plane for fixing a chip to be tested, and specifically, the chip to be tested may be attached to the fixing plane, for example, a substrate of the chip to be tested may be attached toward the fixing plane.
As a possible implementation manner, a sample column 100 may be provided, which is shown in FIG. 2 and is a schematic view of an original sample column in the present embodiment, wherein FIG. 2(b) is a cross-sectional view of the sample column shown in FIG. 2(a) along the direction AA, and then the top of the sample column 100 is directly flattened to obtain a fixed plane 102, and FIG. 3 is a schematic view of another sample column provided in the present embodiment, wherein FIG. 3(b) is a cross-sectional view of the sample column shown in FIG. 3(a) along the direction AA. After the chip 200 to be tested is fixed on the fixing plane 102, refer to fig. 4, which is a schematic diagram of another sample pillar provided in the embodiment of the present application, where fig. 4(b) is a cross-sectional view of the sample pillar shown in fig. 4(a) along the direction AA, the chip 200 to be tested protrudes from the top end of the sample pillar 100, and there is a risk of being touched by mistake in the subsequent operation, and the chip 200 to be tested is easy to fall off, which is not favorable for testing the processing of the chip. In addition, after the top end of the sample pillar 100 is flattened, in the process of automatically adhering the sample by using the machine, the reliability of the adhered sample is easily affected by the limitation of the view field, for example, the chip 200 to be tested may not be accurately aligned with the top end of the sample pillar 100, so that the adhered chip 200 to be tested is also easily detached.
Therefore, in the embodiment of the present application, the sample stage 100 may include a top fixing plane 103 and side walls 104, the side walls are located on the other sides of the fixing plane 103 except the side plane 101, and the side walls 104 may be located on one side of the fixing plane 103, may also be located on two sides of the fixing plane 103, and may also be located on three sides of the fixing plane 103. The side wall 104 can be used as an alignment mark during sample adhering, so that the efficiency and the accuracy of automatic sample adhering are improved.
Specifically, when the side walls 104 are located at two sides of the fixed plane 103, the side walls 104 may be located at two adjacent sides of the fixed plane 103, and when the chip 200 to be tested is fixed on the fixed plane 103, the two adjacent side walls of the chip 200 to be tested may be adjacent to the side walls 104, and the side walls 104 protect the two adjacent side walls of the chip 200 to be tested, so that the possibility of false touch is reduced, and the reliability of fixing the chip 200 to be tested is improved; when the side walls 104 are located at two sides of the fixing plane 103, the side walls 104 may be located at two opposite sides of the fixing plane 103, as shown in fig. 1, and when the chip 200 to be tested is fixed on the fixing plane 103, as shown in fig. 5, a schematic diagram of another sample pillar provided in the embodiment of the present application is provided, where fig. 5(b) is a cross-sectional view of the sample pillar shown in fig. 5(a) along the direction AA, two opposite side walls of the chip 200 to be tested may be adjacent to the side walls 104, and the side walls 104 protect the two opposite side walls of the chip 200 to be tested, so as to improve the reliability of fixing the chip 200 to be tested.
During specific implementation, the chip 200 to be tested may be attached to the surface of the fixing plane 103, or may be attached to the sidewalls of the sidewalls and the surface of the fixing plane 103, the distance between the two sidewalls may be greater than the width of the chip 200 to be tested, or may be equal to the width of the chip 200 to be tested, and the sidewalls may be arranged in parallel or may not be arranged in parallel. For example, the upper distance between the side walls 104 may be greater than the lower distance, the chip 200 to be tested may be placed between the side walls 104 and simultaneously contact the two side walls 104, and the chip 200 to be tested and the fixing plane 103 may be fixed by pasting, so that the chip 200 to be tested may not contact the fixing plane 103, thereby avoiding the influence of the material of the fixing plane 103 on the chip 200 to be tested, for example, impurities generated in the processing process of the chip 200 to be tested are attached to the surface of the chip 200 to be tested.
Specifically, the side walls 104 may be located on three sides of the fixing plane 103, and then the side walls 104 may surround the fixing plane 103 and have an opening in the plane of the side plane 101 of the sample stage 100, as shown in fig. 6, which is a schematic view of another sample stage provided in this embodiment of the present application, where fig. 6(b) is a cross-sectional view of the sample stage shown in fig. 6(a) along the direction AA. Thus, when the chip 200 to be tested is fixed on the fixing plane 103, one side wall of the chip 200 to be tested, which faces the side plane 101, can be exposed through the opening, and the other side walls are adjacent to the side wall 104, and the side wall 104 protects three side walls of the chip 200 to be tested, so that the possibility of mistaken touch is reduced, and the fixing reliability of the chip 200 to be tested is improved.
In specific implementation, the chip 200 to be tested may be attached to the surface of the fixing plane 103, or may be attached to the sidewalls of the sidewalls and the surface of the fixing plane 103, a distance between two opposite sidewalls may be greater than a width of the chip 200 to be tested, or may be equal to a width of the chip 200 to be tested, and the sidewalls may be arranged in parallel or may not be arranged in parallel. For example, the upper distance between the two opposite side walls 104 may be greater than the lower distance, the chip 200 to be tested may be placed between the three side walls 104 and simultaneously contact the three side walls 104, and the chip 200 to be tested and the fixing plane 103 may be fixed by adhesion, so that the chip 200 to be tested and the fixing plane 103 may not contact each other, thereby avoiding the influence of the material of the fixing plane 103 on the chip 200 to be tested, for example, impurities generated in the process of processing the chip 200 to be tested may adhere to the surface of the chip 200 to be tested.
When the side walls 104 are located on two opposite sides of the fixing plane 103, the extending direction of the side walls 104 may be perpendicular to the side plane 101 of the sample stage 100, and the surfaces of the side walls 104 adjacent to the fixing plane 103 are planes, as shown in fig. 1, when the chip 200 to be tested is fixed on the fixing plane 103, the side walls 104 may be parallel to two sides of the chip 200 to be tested, and the side plane 101 of the sample stage 100 is parallel to the other two sides of the chip 200 to be tested, as shown in fig. 5, so as to facilitate the processing of the chip 200 to be tested.
In the embodiment of the present application, a groove may be formed in the region where the fixing plane 103 is located, so that when the chip 200 to be tested is fixed on the fixing plane 103, the chip 200 to be tested may cover over the groove, thereby reducing the influence of the material of the sample pillar 100 on the chip 200 to be tested when the chip 200 to be tested is processed, for example, the material covers the surface of the chip 200 to be tested, and influences the morphology of the chip 200 to be tested.
The embodiment of the application provides a sample platform column, sample platform column can have a side plane, the top has fixed plane and side wall, the side wall is located other sides of fixed plane except the side plane, the fixed plane is used for fixed chip that awaits measuring, that is to say, when fixed chip that awaits measuring on the fixed plane, the side wall can play certain guard action to the chip that awaits measuring, consequently, the fixed of chip that awaits measuring is more reliable, do benefit to the processing and the test to the chip, and simultaneously, the existence of side wall makes sample platform column position easy recognition, consequently, do benefit to the automation and await measuring fixed of chip.
Referring to fig. 7, a schematic diagram of a method for manufacturing a sample pillar according to an embodiment of the present disclosure is shown, where the method may include:
s101, providing a sample table column.
In this embodiment, the sample stage 100 may have a side plane 101, and is used to process the side surface of the chip to be tested fixed on the sample stage from the side plane, for example, the side wall of the chip to be tested is ground by sand paper, so as to obtain the cross section to be tested of the chip to be tested, and the cross section to be tested is detected, so as to obtain the characteristics of the circuit structure inside the chip.
And S102, etching the top of the sample stage column.
In the embodiment of the present application, the sample pillar 100 may be etched to form the fixed plane 103 and the sidewall 104 on the top of the sample pillar, and the etching manner may be an ion etching process. The side walls are located on the other sides of the fixing plane 103 except the side plane 101, and the side walls 104 may be located on one side of the fixing plane 103, on both sides of the fixing plane 103, or on three sides of the fixing plane 103. The side wall 104 can be used for alignment marking during sample adhering, and the efficiency and accuracy of automatic sample adhering are improved.
Specifically, when the side walls 104 are located at two sides of the fixed plane 103, the side walls 104 may be located at two adjacent sides of the fixed plane 103, and when the chip 200 to be tested is fixed on the fixed plane 103, the two adjacent side walls of the chip 200 to be tested may be adjacent to the side walls 104, and the side walls 104 protect the two adjacent side walls of the chip 200 to be tested, so that the possibility of false touch is reduced, and the reliability of fixing the chip 200 to be tested is improved; when the side walls 104 are located at two sides of the fixing plane 103, the side walls 104 may be located at two opposite sides of the fixing plane 103, as shown in fig. 1, and when the chip 200 to be tested is fixed on the fixing plane 103, as shown in fig. 5, two opposite side walls of the chip 200 to be tested may be adjacent to the side walls 104, and the side walls 104 form protection for the two opposite side walls of the chip 200 to be tested, so as to improve the reliability of fixing the chip 200 to be tested.
Specifically, the side walls 104 may be located on three sides of the fixed plane 103, and the side walls 104 may surround the fixed plane 103 and have an opening in the plane where the side plane 101 of the sample stage 100 is located, so that when the chip 200 to be tested is fixed on the fixed plane 103, one side wall of the chip 200 to be tested, which faces the side plane 101, may be exposed through the opening, and the remaining side walls are adjacent to the side walls 104, and the side walls 104 protect all three side walls of the chip 200 to be tested, thereby reducing the possibility of erroneous touch and improving the reliability of fixing the chip 200 to be tested.
When the side walls 104 are located on two opposite sides of the fixing plane 103, the extending direction of the side walls 104 may be perpendicular to the side plane 101 of the sample stage 100, and the surfaces of the side walls 104 adjacent to the fixing plane 103 are planes, as shown in fig. 1, when the chip 200 to be tested is fixed on the fixing plane 103, the side walls 104 may be parallel to two sides of the chip 200 to be tested, and the side plane 101 of the sample stage 100 is parallel to the other two sides of the chip 200 to be tested, as shown in fig. 5, so as to facilitate the processing of the chip 200 to be tested.
In the embodiment of the present application, a groove may be formed in the region where the fixing plane 103 is located, so that when the chip 200 to be tested is fixed on the fixing plane 103, the chip 200 to be tested may cover over the groove, thereby reducing the influence of the material of the sample pillar 100 on the chip 200 to be tested when the chip 200 to be tested is processed, for example, the material covers the surface of the chip 200 to be tested, and influences the morphology of the chip 200 to be tested.
The embodiments in this specification are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A sample stage column, wherein said sample stage column has a side plane; the top of the sample table column is provided with a fixed plane and side walls, the side walls are located on the other sides of the fixed plane except the side plane, and the fixed plane is used for fixing a chip to be tested.
2. The sample stage according to claim 1, wherein the side walls are located on opposite sides, or adjacent sides, of the fixing plane.
3. The sample stage according to claim 2, wherein when the side walls are located on opposite sides of the fixing plane, the extending direction of the side walls is perpendicular to the side plane, and the surface of the side walls adjacent to the fixing plane is a plane.
4. The sample stage according to claim 1, wherein the side wall surrounds the fixing plane and has an opening in a plane of the side plane, and when the chip to be tested is fixed in the fixing plane, the chip to be tested exposes one side wall through the opening.
5. The sample stage column according to any of claims 1 to 4, wherein a recess is further formed in the area of the fixing plane.
6. A method of manufacturing a sample stage, comprising:
providing a sample stage post; the sample stage post has a side plane;
etching the top of the sample stage column to form a fixed plane and a side wall on the top of the sample stage column; the side walls are located on the other sides of the fixing plane except the side plane, and the fixing plane is used for fixing a chip to be tested.
7. The method of claim 6, wherein the side walls are located on opposite sides, or adjacent sides, of the fixing plane.
8. The method of claim 7, wherein when the sidewalls are located on opposite sides of the fixing plane, the extending direction of the sidewalls is perpendicular to the side plane, and the surface of the sidewalls adjacent to the fixing plane is a plane.
9. The method according to any one of claims 6-8, further comprising:
and etching the fixed plane to form a groove.
10. The method of any one of claims 6-8, wherein the etching of the top of the sample stage is performed using an ion etching process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010630887.8A CN111751183A (en) | 2020-07-03 | 2020-07-03 | Sample table column and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010630887.8A CN111751183A (en) | 2020-07-03 | 2020-07-03 | Sample table column and manufacturing method thereof |
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| CN111751183A true CN111751183A (en) | 2020-10-09 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060054820A1 (en) * | 2004-09-10 | 2006-03-16 | Hang-Ja Kim | Method of forming TEM specimen and related protection layer |
| CN103344794A (en) * | 2013-06-24 | 2013-10-09 | 上海华力微电子有限公司 | Multifunctional semiconductor sample fixture |
| CN206892007U (en) * | 2017-05-11 | 2018-01-16 | 广东省肇庆市质量计量监督检测所 | A kind of scanning electron microscope electron back scattering diffraction test sample platform |
| CN209182269U (en) * | 2018-09-29 | 2019-07-30 | 胜科纳米（苏州）有限公司 | Multifunctional sample platform |
| CN210465317U (en) * | 2019-09-06 | 2020-05-05 | 马鞍山钢铁股份有限公司 | Sample seat suitable for EBSD test |
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2020
- 2020-07-03 CN CN202010630887.8A patent/CN111751183A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060054820A1 (en) * | 2004-09-10 | 2006-03-16 | Hang-Ja Kim | Method of forming TEM specimen and related protection layer |
| CN103344794A (en) * | 2013-06-24 | 2013-10-09 | 上海华力微电子有限公司 | Multifunctional semiconductor sample fixture |
| CN206892007U (en) * | 2017-05-11 | 2018-01-16 | 广东省肇庆市质量计量监督检测所 | A kind of scanning electron microscope electron back scattering diffraction test sample platform |
| CN209182269U (en) * | 2018-09-29 | 2019-07-30 | 胜科纳米（苏州）有限公司 | Multifunctional sample platform |
| CN210465317U (en) * | 2019-09-06 | 2020-05-05 | 马鞍山钢铁股份有限公司 | Sample seat suitable for EBSD test |
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Application publication date: 20201009 |