CN111739932A - 一种柔性器件及其制备方法 - Google Patents
一种柔性器件及其制备方法 Download PDFInfo
- Publication number
- CN111739932A CN111739932A CN202010579128.3A CN202010579128A CN111739932A CN 111739932 A CN111739932 A CN 111739932A CN 202010579128 A CN202010579128 A CN 202010579128A CN 111739932 A CN111739932 A CN 111739932A
- Authority
- CN
- China
- Prior art keywords
- flexible
- layer
- region
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 46
- 239000004065 semiconductor Substances 0.000 claims description 38
- 239000011241 protective layer Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 14
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 14
- 239000012790 adhesive layer Substances 0.000 claims description 12
- -1 Polydimethylsiloxane Polymers 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000002861 polymer material Substances 0.000 claims description 9
- 229920005570 flexible polymer Polymers 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 6
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- VVQNEPGJFQJSBK-UHFFFAOYSA-N Methyl methacrylate Chemical compound COC(=O)C(C)=C VVQNEPGJFQJSBK-UHFFFAOYSA-N 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 229920000767 polyaniline Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 229920001197 polyacetylene Polymers 0.000 claims description 2
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000007667 floating Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 6
- 238000005452 bending Methods 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229920001486 SU-8 photoresist Polymers 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
- H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明涉及一种柔性器件及其制备方法,包括电极区、粘合层、柔性基底、器件区、柔性导线,其中所述器件区上表面覆盖保护层。本发明实现了柔性器件的浮空,避免了衬底形变对器件的影响,提高器件的可靠性和稳定性,实现了更大的延展性和可弯曲性。
Description
技术领域
本发明属于柔性电子技术领域,特别涉及一种柔性器件及其制备方法。
背景技术
现代社会对电子产品的功能和用户体验提出了越来越高的需求,将电子器件实现柔性、可弯折、折叠、伸缩等功能,使得电子产品更智能化、便携化、轻量化、可穿戴等符合人体工程学设计已成为发展趋势。将电子器件柔性化可以颠覆性地改变传统信息器件的刚性物理形态,具有轻薄、便携、可植入、可穿戴等特点,可实现信息与人、物体还有环境高效共融。柔性电子技术在信息、能源、医疗、国防、航天等领域具有广泛应用前景,成为全球学术界和工业界的研究热点。
现有的柔性器件,通常将器件直接制备在柔性基板上,器件与柔性材料接触连接,或通过过渡层、粘连层等与柔性材料连接。在来回弯折、不断拉伸过程中,基底中的应力传递到器件中,器件内部、界面将引入缺陷、损伤等,严重影响器件的性能可靠性。
发明内容
本发明所要解决的技术问题是提供一种柔性器件及其制备方法,克服现有柔性器件在来回弯折、不断拉伸的过程中,严重影响器件的性能可靠性的缺陷,本发明中通过将器件功能区和柔性导线置于柔性基底上方完全浮空,避免与基底直接接触,降低了基底对器件区的应力作用,保证柔性器件具有优良的电化学性能。
本发明提供一种柔性器件,包括:电极区、粘合层、柔性基底、保护层、器件区、柔性导线,所述器件区、柔性导线均悬浮于柔性基底上方,柔性导线连接电极区和器件区的电极,电极区通过粘合层与柔性基底连接,其中所述器件区上表面覆盖保护层。
所述电极区为导电材料,包括不限于金属单质或者合金、导电聚合物或其他材料形成的复合材料。
所述器件区为无机半导体器件、有机半导体器件均适用。
所述粘合层将电极与柔性基底连接,为有机化合物材料。
进一步,所述粘合层包括但不限于光刻胶、甲基丙烯酸甲酯PMMA、聚二甲基硅氧烷PDMS中的一种或多种。
所述柔性基底为柔性玻璃材料、金属材料、聚合物材料,或另一种适当的柔性衬底材料,包括不限于聚二甲基硅氧烷(PDMS)、聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)等。
所述保护层为器件区提供缓冲、保护作用。
所述保护层为柔性聚合物材料;所述柔性导线为导电性的柔性聚合物材料。
所述保护层包括但不限于聚二甲基硅氧烷PDMS、聚酰亚胺PI、甲基丙烯酸甲酯PMMA、聚对苯二甲酸乙二醇酯PET中的一种或几种。
所述柔性导线包括但不限于导电胶、聚苯胺、聚苯胺其衍生物、聚乙炔中的一种或几种。
所述柔性导线为蛇形、Z形、螺旋形中的一种,优选蛇形形状。
本发明提供一种柔性器件的制备方法,包括:
(1)提供半导体基板,并在半导体基板的第二半导体层中形成器件区;其中所述半导体
基板包括第一半导体层、绝缘埋层、第二半导体层;
(2)在对应于形成柔性导线的位置形成刻蚀窗口,刻蚀第二半导体层,形成贯穿至所述绝缘埋层的凹槽,然后在凹槽中填充具有导电性的柔性聚合物材料,形成柔性导线;
(3)在对应于形成电极区的位置形成刻蚀窗口,刻蚀第二半导体层,形成贯穿至所述绝缘埋层的凹槽,然后在凹槽中填充导电材料,形成电极区,并且柔性导线连接电极区和
器件区的电极;
(4)在器件区上表面覆盖一层保护层;所述保护层可以提供应力缓冲,并在刻蚀过程中
起到保护作用;
(5)依次刻蚀去除器件区外的第二半导体层、绝缘埋层,将器件区、柔性导线、电极区从第一半导体层剥离后转移到柔性基底上,并将电极区通过粘合层与柔性基底连接,器件区和柔性导线均位于基底上方完全浮空。
所述步骤(4)中通过光刻形成刻蚀窗口,采用旋涂或沉积方法形成保护层,最后去除光刻胶。
本发明提供一种所述方法制备的柔性器件。
本发明提供一种所述柔性器件的应用。
有益效果
(1)本发明提供的浮空的柔性器件结构,相对现有技术的改进主要在于将整个器件区和互联导线完全悬空于柔性基底上方,避免了柔性基底在较大拉伸和弯曲过程中形变应力引起器件区电学性能退化,发生阈值电压漂移、跨导降低、关态泄漏电流升高、饱和电流减小等现象,最终不能正常工作。因此本发明能够提高器件性能的可靠性和稳定性。
(2)本发明如采用蛇形状的柔性导线,可以实现更大的延展性,结合浮空设计,进一步增强了导线的柔性特性,同时利用柔性导线将器件区的电极端引出,使得测量过程更加简易方便。
附图说明
图1为柔性器件结构的截面图;
图2为柔性器件结构的俯视图;
图3为本发明制备流程图;
其中附图中电极区1、粘合层2、柔性基底3、保护层4、器件区5、柔性导线6。
具体实施方式
下面结合具体实施例,进一步阐述本发明。应理解,这些实施例仅用于说明本发明而不用于限制本发明的范围。此外应理解,在阅读了本发明讲授的内容之后,本领域技术人员可以对本发明作各种改动或修改,这些等价形式同样落于本申请所附权利要求书所限定的范围。
实施例1
柔性器件如图1和2所示,包括:电极区1、粘合层2、柔性基底3、保护层4、器件区5、柔性导线6,所述器件区5、柔性导线6均悬浮于柔性基底3上方,柔性导线6连接电极区1和器件区5的电极,电极区1通过粘合层2与柔性基底3连接,其中所述器件区5上表面覆盖保护层4。
实施例2
(1)提供半导体基板,所述半导体基板包括第一半导体层、绝缘埋层、第二半导体层。本发明的半导体基板为SOI结构,其中第一半导体层为8英寸硅衬底,绝缘埋层为氧化硅,厚度20nm~2μm,第二半导体层为单晶硅,厚度为10nm~1μm。在所述第二半导体层中形成一种半导体器件为SOI MOS晶体管,包括在所述第二半导体层上方形成栅极,包括栅极氧化层和多晶硅层,在所述栅极两侧的第二半导体层中形成源极和漏极,所述源极、漏极对NMOS晶体管为N型掺杂,对PMOS晶体管为P型掺杂。对所述源漏极、栅极分别进行电性接出,在器件周围形成浅沟槽隔离区进行器件间电气隔离,最终在第二半导体层中形成器件区5。
(2)在对应于形成柔性导线的位置形成刻蚀窗口,刻蚀第二半导体层,形成贯穿至所述绝缘埋层的凹槽,在所述凹槽中填充具有导电性的柔性聚合物材料聚苯胺形成的柔性导线6,优选蛇形导线。
(3)在对应于形成电极区的位置形成刻蚀窗口,刻蚀第二半导体层,形成贯穿至所述绝缘埋层的凹槽,在所述凹槽中填充导电材料聚苯胺形成电极区1,柔性导线6连接电极区1和器件区5的电极。
(4)在器件5上表面覆盖一层聚二甲基硅氧烷PDMS形成保护层4。一般通过光刻形成刻蚀窗口,采用旋涂或沉积方法形成保护层,最后去除光刻胶。所述保护层可以提供应力缓冲,并在刻蚀过程中起到保护作用。
(5)依次刻蚀去除器件区外的第二半导体层、绝缘埋层,将器件区、柔性导线、电极区从第一半导体层剥离后转移到柔性基底3上,其中电极区1通过粘合层2与柔性基底3连接,器件区和柔性导线均位于基底上方完全浮空。可选的,所述粘合层为SU-8光刻胶,厚度为0.01~1000μm;所述柔性基底为聚二甲基硅氧烷PDMS,厚度为0.01~1000μm。
相比现有技术,本发明所实现的柔性器件在承受更大拉伸和弯曲条件下,依然能够保证器件正常工作,器件阈值电压、关态泄漏电流、饱和电流、跨导等不发生显著退化而引起器件失效,从而提高了器件的可靠性和稳定性。
Claims (10)
1.一种柔性器件,包括:电极区(1)、粘合层(2)、柔性基底(3)、保护层(4)、器件区(5)、柔性导线(6),其特征在于,所述器件区(5)、柔性导线(6)均悬浮于柔性基底(3)上方,柔性导线(6)连接电极区(1)和器件区(5)的电极,电极区(1)通过粘合层(2)与柔性基底(3)连接,其中所述器件区(5)上表面覆盖保护层(4)。
2.根据权利要求1所述器件,其特征在于,所述粘合层为光刻胶、甲基丙烯酸甲酯PMMA、聚二甲基硅氧烷PDMS中的一种或几种;柔性基底为柔性玻璃材料、金属材料、聚合物材料中的一种或几种。
3.根据权利要求1所述器件,其特征在于,所述保护层为柔性聚合物材料;所述柔性导线为导电性的柔性聚合物材料。
4.根据权利要求3所述器件,其特征在于,所述保护层为聚二甲基硅氧烷PDMS、聚酰亚胺PI、甲基丙烯酸甲酯PMMA、聚对苯二甲酸乙二醇酯PET中的一种或几种。
5.根据权利要求3所述器件,其特征在于,所述柔性导线为导电胶、聚苯胺、聚苯胺其衍生物、聚乙炔中的一种或几种。
6.根据权利要求1所述器件,其特征在于,所述柔性导线为蛇形、Z形、螺旋形中的一种。
7.一种柔性器件的制备方法,包括:
(1)提供半导体基板,并在半导体基板的第二半导体层中形成器件区;其中所述半导体基板包括第一半导体层、绝缘埋层、第二半导体层;
(2)在对应于形成柔性导线的位置形成刻蚀窗口,刻蚀第二半导体层,形成贯穿至所述绝缘埋层的凹槽,然后在凹槽中填充具有导电性的柔性聚合物材料,形成柔性导线;
(3)在对应于形成电极区的位置形成刻蚀窗口,刻蚀第二半导体层,形成贯穿至所述绝缘埋层的凹槽,然后在凹槽中填充导电材料,形成电极区,并且柔性导线连接电极区和器件区的电极;
(4)在器件区上表面覆盖一层保护层;
(5)依次刻蚀去除器件区外的第二半导体层、绝缘埋层,将器件区、柔性导线、电极区从第一半导体层剥离后转移到柔性基底上,并将电极区通过粘合层与柔性基底连接,器件区和柔性导线均位于基底上方完全浮空。
8.根据权利要求7所述制备方法,其特征在于,所述步骤(4)中通过光刻形成刻蚀窗口,采用旋涂或沉积方法形成保护层,最后去除光刻胶。
9.一种权利要求7所述方法制备的柔性器件。
10.一种权利要求1所述柔性器件的应用。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010579128.3A CN111739932A (zh) | 2020-06-23 | 2020-06-23 | 一种柔性器件及其制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010579128.3A CN111739932A (zh) | 2020-06-23 | 2020-06-23 | 一种柔性器件及其制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111739932A true CN111739932A (zh) | 2020-10-02 |
Family
ID=72650586
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010579128.3A Pending CN111739932A (zh) | 2020-06-23 | 2020-06-23 | 一种柔性器件及其制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111739932A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113697759A (zh) * | 2021-07-09 | 2021-11-26 | 中国电子科技集团公司第十三研究所 | 基于柔性衬底的mems惯性传感器及制备方法 |
CN114041799A (zh) * | 2021-10-29 | 2022-02-15 | 南京大学 | 用于柔性传感器中电气互联的可拉伸图案化金属导线及加工工艺 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009074891A (ja) * | 2007-09-20 | 2009-04-09 | Citizen Holdings Co Ltd | 物理量センサとその製造方法 |
US20100255622A1 (en) * | 2009-04-06 | 2010-10-07 | Honeywell International, Inc. | Systems and methods for affixing a silicon device to a support structure |
JP2018022812A (ja) * | 2016-08-05 | 2018-02-08 | 国立研究開発法人産業技術総合研究所 | 電子デバイス及びその製造方法 |
-
2020
- 2020-06-23 CN CN202010579128.3A patent/CN111739932A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009074891A (ja) * | 2007-09-20 | 2009-04-09 | Citizen Holdings Co Ltd | 物理量センサとその製造方法 |
US20100255622A1 (en) * | 2009-04-06 | 2010-10-07 | Honeywell International, Inc. | Systems and methods for affixing a silicon device to a support structure |
JP2018022812A (ja) * | 2016-08-05 | 2018-02-08 | 国立研究開発法人産業技術総合研究所 | 電子デバイス及びその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113697759A (zh) * | 2021-07-09 | 2021-11-26 | 中国电子科技集团公司第十三研究所 | 基于柔性衬底的mems惯性传感器及制备方法 |
CN114041799A (zh) * | 2021-10-29 | 2022-02-15 | 南京大学 | 用于柔性传感器中电气互联的可拉伸图案化金属导线及加工工艺 |
CN114041799B (zh) * | 2021-10-29 | 2023-07-25 | 南京大学 | 用于柔性传感器中电气互联的可拉伸图案化金属导线及加工工艺 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102347368B (zh) | 晶体管、制造晶体管的方法及包括晶体管的平板显示器 | |
KR101262319B1 (ko) | 그래핀 전극을 포함하는 플렉시블/스트레처블 반도체 소자, 반도체층과 그래핀 전극 사이의 접촉저항 감소 방법, 및 그래핀 인터커넥터 | |
CN100431169C (zh) | 场效应晶体管及使用该晶体管的显示器件 | |
CN104040693B (zh) | 一种金属氧化物tft器件及制造方法 | |
CN102254938B (zh) | 薄膜晶体管、具有此薄膜晶体管的像素结构及电路结构 | |
CN106206710A (zh) | 一种二维材料异质结场效应晶体管、其制备方法和晶体管阵列器件 | |
CN111739932A (zh) | 一种柔性器件及其制备方法 | |
CN104656332B (zh) | 阵列基板及其制备方法和显示装置 | |
EP2284891A3 (en) | Semiconductor device and manufacturing method thereof | |
CN104752420A (zh) | 显示设备的抗静电装置及其制造方法 | |
US20120097955A1 (en) | Thin film transistor and pixel structure having the thin film transistor | |
CN107611173A (zh) | 氧化铝/二氧化硅双层栅极柔性薄膜晶体管及制备方法 | |
CN110148561A (zh) | Si基AlGaN/GaN 高电子迁移率晶体管转移至柔性衬底的方法 | |
Khan et al. | Flexible FETs using ultrathin Si microwires embedded in solution processed dielectric and metal layers | |
CN105932032A (zh) | 一种阵列基板及其制备方法 | |
CN106356306A (zh) | 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管 | |
CN109585367A (zh) | 显示装置、显示面板、阵列基板及其制造方法 | |
CN104022124B (zh) | 一种柔性显示基板及其制备方法、柔性显示装置 | |
CN107146773B (zh) | Tft基板的制作方法 | |
US9236492B2 (en) | Active device | |
CN105047677A (zh) | 显示基板及其制作方法和显示装置 | |
Lee et al. | Stretchable Si logic devices with graphene interconnects | |
CN111739933A (zh) | 一种浮空的柔性器件及其制备方法 | |
CN105845825A (zh) | 一种有机摩擦场效应晶体管、晶体管阵列及其制备方法 | |
CN102437194A (zh) | 金属氧化物薄膜晶体管及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201002 |
|
RJ01 | Rejection of invention patent application after publication |