CN111739813A - 芯片封装方法与芯片封装结构 - Google Patents

芯片封装方法与芯片封装结构 Download PDF

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CN111739813A
CN111739813A CN202010641529.7A CN202010641529A CN111739813A CN 111739813 A CN111739813 A CN 111739813A CN 202010641529 A CN202010641529 A CN 202010641529A CN 111739813 A CN111739813 A CN 111739813A
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chip packaging
insulating layer
metal
packaging method
repairing
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梅嬿
陈浩
许冠猛
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Hefei Qizhong Sealing Technology Co ltd
Chipmore Technology Corp Ltd
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Hefei Yisiwei Sealing And Testing Technology Co ltd
Beijing Eswin Technology Co Ltd
Chipmore Technology Corp Ltd
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Abstract

本发明提供了一种芯片封装方法与芯片封装结构，所述芯片封装方法包括先在半导体基片表面制备绝缘层，所述半导体基片表面具有金属焊盘，所述绝缘层设有与所述金属焊盘位置相对应的开口；再依次制备金属种子层与金属凸块，并刻蚀去除相邻所述金属凸块之间的金属种子层，使得相应区域的绝缘层向外暴露；然后，采用既定的激发源与工艺气体对相邻所述金属凸块之间的所述绝缘层进行等离子体修复。采用上述芯片封装方法得到的芯片封装结构能够有效改善绝缘层的电阻性能，减小、克服绝缘层漏电，有效提高产品良率与质量。

Description

芯片封装方法与芯片封装结构
技术领域
本发明涉及一种半导体生产技术领域，尤其涉及一种芯片封装方法与芯片封装结构。
背景技术
随着电子产业的发展与市场需求的提高，芯片封装结构的小型化是半导体技术发展的必然趋势。就倒装芯片而言，其通常采用金属凸块(pillar)及设置在凸块顶部的焊料连接至相应的基板，相邻凸块之间具有绝缘层。实际生产过程中，上述芯片完成金属种子层刻蚀并进行电性测试时，其绝缘层表面经常也会出现微小的电流，体现为电阻值偏低，造成产品失效。
鉴于此，有必要提供一种新的芯片封装方法与芯片封装结构。
发明内容
本发明的目的在于提供一种芯片封装方法与芯片封装结构，能够改善绝缘层的电阻性能，提高产品良率与质量。
为实现上述目的，本发明提供了一种芯片封装方法，主要包括：
在半导体基片表面制备绝缘层，所述半导体基片表面具有金属焊盘，所述绝缘层设有与所述金属焊盘位置相对应的开口；
制备金属种子层；
在所述金属种子层的既定区域制备金属凸块；
刻蚀，使得相邻所述金属凸块之间的绝缘层向外暴露；
等离子体修复，采用既定的激发源与工艺气体对相邻所述金属凸块之间的所述绝缘层进行修复。
作为本发明的进一步改进，所述制备金属种子层步骤包括先对所述绝缘层进行电感耦合等离子体刻蚀，再通过磁控溅射工艺沉积形成所述金属种子层。
作为本发明的进一步改进，所述制备金属凸块步骤包括：
涂布光刻胶；
曝光、显影使得所述既定区域的金属种子层向外暴露；
在所述既定区域的金属种子层上制得所述金属凸块。
作为本发明的进一步改进，所述金属凸块采用电镀工艺制得。
作为本发明的进一步改进，所述绝缘层的厚度设置为3～20μm。
作为本发明的进一步改进，所述芯片封装方法还包括：
选取若干样品；
采用所述激发源与工艺气体对所述样品进行修复，至少部分所述样品进行修复处理的时间不同；
对比修复处理后的样品性能，确定修复时间。
作为本发明的进一步改进，检测所述绝缘层在所述等离子体修复过程中的减薄量，并控制所述减薄量不小于0.1μm。
本发明还提供一种芯片封装结构，采用如前所述的芯片封装方法制得。
作为本发明的进一步改进，所述绝缘层设置为聚酰亚胺薄膜。
作为本发明的进一步改进，所述金属凸块包括沿垂直于所述半导体基片的方向延伸设置第一导电部分、设置在所述第一导电部分背离所述半导体基片一端的第二导电部分。
本发明的有益效果是：采用本发明芯片封装方法与芯片封装结构，刻蚀去除相邻所述金属凸块之间的金属种子层之后，采用既定的激发源与工艺气体对相应区域的所述绝缘层进行等离子体修复，恢复提高相邻所述金属凸块之间的绝缘层的电阻性能，减小、克服绝缘层可能出现的漏电，提高产品良率与质量。
附图说明
图1是本发明芯片封装方法的主要流程示意图；
图2是本发明芯片封装结构的结构示意图。
具体实施方式
以下将结合附图所示的实施方式对本发明进行详细描述。但该实施方式并不限制本发明，本领域的普通技术人员根据该实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
结合图1与图2所示，本发明提供一种芯片封装方法及采用该芯片封装方法制得的芯片封装结构100。
所述芯片封装方法主要包括：
提供半导体基片10，该半导体基片10表面具有金属焊盘11及钝化层12，所述钝化层12形成有使得所述金属焊盘11向外暴露的开口；
在所述半导体基片10表面制备绝缘层20，所述绝缘层20同样设有与所述金属焊盘位置相对应的开口，以使得所述金属焊盘11向外暴露；
制备金属种子层30；
在所述金属种子层30的既定区域制备金属凸块40；
刻蚀，使得相邻所述金属凸块40之间的绝缘层20向外暴露；
等离子体修复，采用既定的激发源与工艺气体对相邻所述金属凸块40之间的所述绝缘层20进行修复，得到相应的芯片封装结构100。
所述钝化层12设置为氮化硅、氧化硅等膜层，其用以保护所述金属焊盘11并实现电学隔离；所述绝缘层20设置由聚合物构成，本实施例中，所述绝缘层20设置为聚酰亚胺(Polyimide)薄膜且其厚度优选设置为3～20μm。所述绝缘层20能够有效阻滞电子迁移，减小相邻所述金属凸块40之间的漏电流，也防止水汽等对所述半导体基片10的腐蚀。通常地，所述绝缘层20的开口通常设置小于所述钝化层12的开口，即使得所述绝缘层20完全覆盖所述钝化层12。
所述制备金属种子层30步骤包括先对所述绝缘层20进行电感耦合等离子体刻蚀(ICP Etch)，再通过磁控溅射工艺沉积形成所述金属种子层30。其中，所述金属种子层30一般会覆盖整个绝缘层20以及所述绝缘层20的开口区域。
所述制备金属凸块40步骤具体包括：
涂布光刻胶；
曝光、显影使得所述既定区域的金属种子层30向外暴露；
在所述既定区域的金属种子层30上制得所述金属凸块40，所述金属凸块40通常可采用电镀工艺制得。
所述金属凸块40包括沿垂直于所述半导体基片10的方向延伸设置第一导电部分41、设置在所述第一导电部分41背离所述半导体基片10一端的第二导电部分42，所述第二导电部分42优选不超出所述第一导电部分41的范围。作为示例地，所述第一导电部分41可采用铜或铜合金制得；所述第二导电部分42可设置由锡或锡合金制得。需要说明的是，所述金属种子层30、导电凸块40的成型方式并不限于上述工艺与步骤；所述金属凸块40所采用的材料及具体结构可视不同的产品类型与需求而定。
在此，我们也对所述绝缘层20电阻下降机理进行了相关的分析与测试，参下表所示，A：对绝缘层20进行电感耦合等离子体刻蚀，再于所述绝缘层20表面先后完成制备、刻蚀去除金属种子层30；B：直接在绝缘层20表面制备金属种子层30，并刻蚀去除上述金属种子层30；C：仅对绝缘层20进行电感耦合等离子体刻蚀。
Figure BDA0002571327570000041
其中，A组测试结果有力说明本申请芯片封装结构100通过等离子体修复过程能够有效恢复绝缘层20的电阻性能；另两组测试结果则说明所述绝缘层20的电阻性能下降主要缘于电感耦合等离子体刻蚀制程。
实际应用中，可采用微波等离子体激发源和/或射频等离子体激发源将工艺气体激发生成相应的等离子体，以对所述绝缘层20进行修复；所述工艺气体可采用O2、N2、CF4或上述不同气体的组合。此处，为减小所述等离子体修复过程对所述金属凸块40的影响，优选采用射频等离子体激发源配合N2对所述绝缘层20进行修复。
所述芯片封装方法还包括：
选取若干样品，所述样品具有初始结构与电阻性能一致的绝缘层20，且所述绝缘层20均进行同样的电感耦合等离子体刻蚀过程；
采用所述激发源与工艺气体对所述样品的绝缘层20进行修复，至少部分所述样品进行修复处理的时间不同；
对比修复处理后的样品性能，确定修复时间，所述修复时间是指所述绝缘层20能够实现较理想的性能回复所需的时间，也可理解为实际生产中所述等离子体修复步骤所需的最小工艺时长。
上述等离子体修复过程也会对所述绝缘层20产生一定程度的蚀刻，换言之，所述绝缘层20经所述等离子体修复后其厚度通常有所减小。为更好地实现产品检测与评估，所述芯片封装方法还包括检测所述绝缘层20在所述等离子体修复过程中的减薄量，并控制所述减薄量不小于0.1μm。
综上所述，本发明芯片封装方法通过刻蚀去除相邻所述金属凸块40之间的金属种子层30之后，采用既定的激发源与工艺气体对相应区域的所述绝缘层20进行等离子体修复，恢复提高相邻所述金属凸块40之间的绝缘层20的电阻性能，减小、克服绝缘层20可能出现的漏电，提高产品良率与质量。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (10)

1.一种芯片封装方法，其特征在于：
在半导体基片表面制备绝缘层，所述半导体基片表面具有金属焊盘，所述绝缘层设有与所述金属焊盘位置相对应的开口；
制备金属种子层；
在所述金属种子层的既定区域制备金属凸块；
刻蚀，使得相邻所述金属凸块之间的绝缘层向外暴露；
等离子体修复，采用既定的激发源与工艺气体对相邻所述金属凸块之间的所述绝缘层进行修复。
2.根据权利要求1所述的芯片封装方法，其特征在于：所述制备金属种子层步骤包括先对所述绝缘层进行电感耦合等离子体刻蚀，再通过磁控溅射工艺沉积形成所述金属种子层。
3.根据权利要求1所述的芯片封装方法，其特征在于：所述制备金属凸块步骤包括涂布光刻胶；
曝光、显影使得所述既定区域的金属种子层向外暴露；
在所述既定区域的金属种子层上制得所述金属凸块。
4.根据权利要求1或3所述的芯片封装方法，其特征在于：所述金属凸块采用电镀工艺制得。
5.根据权利要求1所述的芯片封装方法，其特征在于：所述绝缘层的厚度设置为3～20μm。
6.根据权利要求1所述的芯片封装方法，其特征在于：所述芯片封装方法还包括选取若干样品；
采用所述激发源与工艺气体对所述样品进行修复，至少部分所述样品进行修复处理的时间不同；
对比修复处理后的样品性能，确定修复时间。
7.根据权利要求1所述的芯片封装方法，其特征在于：检测所述绝缘层在所述等离子体修复过程中的减薄量，并控制所述减薄量不小于0.1μm。
8.一种芯片封装结构，其特征在于：所述芯片封装结构采用如权利要求1-7任一项所述的芯片封装方法制得。
9.根据权利要求8所述的芯片封装结构，其特征在于：所述绝缘层设置为聚酰亚胺薄膜。
10.根据权利要求8所述的芯片封装结构，其特征在于：所述金属凸块包括沿垂直于所述半导体基片的方向延伸设置第一导电部分、设置在所述第一导电部分背离所述半导体基片一端的第二导电部分。
CN202010641529.7A 2020-07-06 2020-07-06 芯片封装方法与芯片封装结构 Pending CN111739813A (zh)

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CN112802813A (zh) * 2020-12-22 2021-05-14 颀中科技（苏州）有限公司 芯片封装结构、芯片封装结构的制备方法和显示屏

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CN101207046A (zh) * 2006-12-18 2008-06-25 中芯国际集成电路制造(上海)有限公司 凸点的形成方法
CN101924083A (zh) * 2009-06-09 2010-12-22 日月光半导体制造股份有限公司 半导体封装件及其制造方法

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CN101207046A (zh) * 2006-12-18 2008-06-25 中芯国际集成电路制造(上海)有限公司 凸点的形成方法
CN101924083A (zh) * 2009-06-09 2010-12-22 日月光半导体制造股份有限公司 半导体封装件及其制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112802813A (zh) * 2020-12-22 2021-05-14 颀中科技（苏州）有限公司 芯片封装结构、芯片封装结构的制备方法和显示屏

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