CN111726120B - RLHDB3 coding method, device, equipment and storage medium of DSP - Google Patents

RLHDB3 coding method, device, equipment and storage medium of DSP Download PDF

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CN111726120B
CN111726120B CN202010661474.6A CN202010661474A CN111726120B CN 111726120 B CN111726120 B CN 111726120B CN 202010661474 A CN202010661474 A CN 202010661474A CN 111726120 B CN111726120 B CN 111726120B
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rlhdb3
output
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processing
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CN111726120A (en
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刘剑丽
陈金鹰
曹俊兴
蔡方凯
赵耀
吴睿
李晓钰
倪磊
丁姝郁
黄山
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Chengdu Technological University CDTU
Chengdu Univeristy of Technology
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Chengdu Univeristy of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a RLHDB3 coding method, a device, equipment and a storage medium based on a DSP, firstly, initializing an RLHDB3 coding program of a DSP chip; inputting data to be encoded to a new address from an input port PA1 of the DSP chip by using an instruction PORTR, and loading the data to be encoded to an accumulator A; judging whether the data to be coded is a0 value, if so, processing the input 0 value, otherwise, processing the input 1 value; and performing sliding processing, outputting RLHDB3 codes, and finishing the RLHDB3 codes based on the DSP. The invention solves the problems of lack of flexibility of change, high cost, resource logic occupation and low working rate in the existing coding mode through the design, and simultaneously solves the problem of high-speed data transmission while lighting by using the LED, in particular the problem that the illumination intensity is influenced by long-time LED turn-off caused by continuous 0 code transmission.

Description

RLHDB3 coding method, device, equipment and storage medium of DSP
Technical Field
The invention belongs to the technical field of RLHDB3 coding, and particularly relates to a RLHDB3 coding method, device, equipment and storage medium based on a DSP.
Background
The Rise Level High Density Bipolar code of Order 3code (RLHDB 3) is a coding mode for improving a reference Level on the basis of coding HDB3 of a digital interface with the speed of 2MHz, 8MHz and 32MHz specified in the G.703 recommendation by ITU-T, and realizes that no negative Level exists in a transmission code so that an LED illuminating lamp can be lightened when encountering the transmission continuous 0 code. The HDB3 encoding of the original data can be realized by adopting a special AMI/HDB3 encoder/decoder chip such as CD 22103; the method can also be realized by using a complex programmable logic device CPLD or a field programmable logic device FPGA to carry out logic design; in some applications with low requirements on the coding rate, the LHDB3 encoder/decoder can be designed by utilizing the single chip microcomputer. In the three coding modes, the special chip is relatively convenient to use, but the flexibility of change is lacked; the CPLD/FPGA occupies logic resources, and the cost is higher; the singlechip is low in price but low in working speed. More importantly, the LED lamp can not be lightened when transmitting the-1 code, and the lighting effect is influenced. For this purpose, the present application proposes to use the DSP chip STM320C54x of the company TI for coding, which combines the advantages mentioned above.
Disclosure of Invention
Aiming at the defects in the prior art, the RLHDB3 coding method, the RLHDB3 coding device, the RLHDB3 coding equipment and the RLHDB3 coding storage medium solve the problems that the existing coding mode lacks flexibility of change, is high in cost, occupies resource logic and is low in working rate, an LED lamp cannot be lighted when continuous 0 codes are transmitted, and the LED lamp cannot be lighted when-1 codes in HDB3 codes are transmitted, so that the lighting effect is influenced.
In order to achieve the above purpose, the invention adopts the technical scheme that:
the scheme provides a RLHDB3 coding method of a DSP, which comprises the following steps:
s1, initializing RLHDB3 coding program of the DSP chip;
s2, inputting the data to be coded to a new address new _ data from the input port PA1 of the DSP chip by using an instruction PORTR, and loading the data to be coded to an accumulator A;
s3, judging whether the data to be coded is 0 value, if yes, processing the input 0 value and entering the step S4, otherwise, processing the input 1 value and entering the step S4;
and S4, performing sliding processing on the 0 value or the 1 value processed in the step S3, outputting RLHDB3 codes, and finishing the RLHDB3 codes based on the DSP.
Further, the step S1 is specifically: the setting pointer DP is 0, the initial value of the flag signal foe is 0, and the initial value of the flag signal fpn is 1, and 0, +1, and-1 values output from RLHDB3 are stored in tpvl0 units, tpvl1 units, and tpvl1n units, respectively.
Still further, the processing the input 0 value in step S3 includes the following steps:
a1, performing minus 1 counting processing on the auxiliary register AR2, and judging whether the data input in the auxiliary register AR2 is a0 value, if so, processing input continuous 4 0 values, and entering step A2, otherwise, outputting the 0 value in the tpvl0 unit to the tmp unit, completing the processing of the input 0 value, and entering step S4;
a2, resetting the initial value of the count of the auxiliary register AR2 to 4, and judging whether the value of the flag signal foe is 1, if yes, indicating that the number of 1 is odd between two destruction pulses V, inserting 000V group codes, and entering step A3, otherwise, indicating that the number of 1 is even between two destruction pulses V, inserting B00V group codes, and entering step A6;
a3, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of positive and negative 1 are output, and entering step A4, otherwise, indicating that even number of positive and negative 1 are output, and entering step A5;
a4, outputting +1 in the tpvl1 unit to the tmp unit, resetting foe the flag initial value foe-0, completing the processing of inputting 0 value, and proceeding to step S4;
a5, outputting-1 in the tpvl1n unit to the tmp unit, resetting foe the flag initial value foe to 0, completing the processing of inputting 0 value, and proceeding to step S4;
a6, where the initial value of the reset flag signal foe is foe ═ 0, and the flag signal fpn is xored with the value 1, the expression of the xor operation of the flag signal fpn with the value 1 is:
fpn←fpn⊕1；
a7, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of 1 are output, and entering step A8, otherwise, indicating that even number of 1 are output, and entering step A9;
a8, performing output assignment of tmp ═ tpvl1 and tmp +3 ═ tpvl1 respectively, completing the processing of the input 0 value, and proceeding to step S4;
a9, performing output assignment of tmp ═ tpvl1n ═ -1 and tmp +3 ═ tpvl1n ═ -1, respectively, completing the processing of the input 0 value, and proceeds to step S4.
Still further, the processing the input 1 value in step S3 includes the following steps:
b1, storing the count initial value 4 of the continuous 4 input detection values 0 in the auxiliary register AR2, and clearing the past count of the 0 value;
b2, performing xor operation of flag signal foe and value 1 and xor operation of flag signal fpn and value 1, respectively, updating the parity number flag signal of input 1 value and outputting the positive/negative code parity number flag signal;
the expression of the exclusive or operation of the flag signal foe with the value 1 is:
foe←foe⊕1；
the expression of the exclusive or operation of the flag signal fpn with the value 1 is:
fpn←fpn⊕1；
b3, judging whether the output data is a positive code according to the new output positive and negative code parity number flag signal fpn, if so, entering the step B4, otherwise, if so, outputting the data is a negative code, and entering the step B5;
b4, outputting +1 of tpvl1 unit to tmp unit, completing the processing of input 1 value, and proceeding to step S4;
b5, output-1 in tpvl1n unit to tmp unit, complete the processing of input 1 value, and proceed to step S4.
Still further, the step S4 includes the steps of:
c1, establishing a linear sliding window taking the tmp unit as a starting address;
c2, copying tmp +3 to tmp +4, tmp +2 to tmp +3, tmp +1 to tmp +2 and tmp to tmp +1 respectively by using a delay instruction, moving the data in the linear sliding window by one unit to the high address direction, and adjusting the RLHDB3 encoding rate by adding a no-operation instruction;
c3, outputting tmp +4 to RLHDB3 output units, wherein if the value in the RLHDB3 output unit is +1, the value output to the output port PA0 of the DSP chip is +2 reference levels, if the value in the RLHDB3 output unit is 0, the value output to the output port PA0 of the DSP chip is +1 reference levels, and if the value in the RLHDB3 output unit is-1, the value output to the output port PA0 of the DSP chip is 0 reference levels, and then the value is output to the output port PA0 of the DSP chip;
c4, judging whether there is new input data, if yes, returning to step S1, otherwise, finishing RLHDB3 coding based on DSP.
The invention also provides a RLHDB3 encoding device of the DSP, which comprises: the LED lamp comprises a DSP chip module for executing an encoding function, an RAM data memory for storing temporary data, a ROM program memory for storing an execution program, an output driving circuit for increasing the load capacity of the LED lamp and the LED lamp which is connected with the output driving circuit and completes the functions of illumination and data transmission, wherein the DSP chip module is a C54xDSP chip module.
Further, the DSP chip module and the RAM data memory include:
the initialization unit is used for initializing the RLHDB3 coding program of the DSP chip;
the acquiring unit is used for inputting data to be encoded to a new address new _ data from an input port PA1 of the DSP chip by using an instruction PORTR, and loading the data to be encoded to an accumulator A;
the device comprises a detection unit, a processing unit and a processing unit, wherein the detection unit is used for processing data to be encoded, and the processing of the data to be encoded comprises the processing of an input 0 value or the processing of an input 1 value;
a sliding processing unit for moving the 0 value or the 1 value processed by the detection unit to the high address direction and adjusting the RLHDB3 encoding rate by adding a no-operation instruction;
and the output unit is used for outputting the RLHDB3 coding result based on the DSP chip.
The invention also provides RLHDB3 encoding equipment of the DSP, which comprises a processor, a data temporary storage RAM memory and a ROM program memory for storing and executing programs; stored in the ROM program memory is at least one instruction, at least one program, or a set of instructions that is loaded and executed by the at least one processor to perform the operations performed in the RLHDB3 encoding method of any one of claims 1-5.
The present invention also provides a computer-readable storage medium having stored therein at least one instruction, at least one program, or a set of instructions for loading by at least one processor and executing data temporarily encoded in RAM memory to carry out operations performed in the RLHDB3 encoding method of any one of claims 1 to 5.
The invention has the beneficial effects that:
(1) the invention analyzes the RLHDB3 coding rule, and provides a design method for realizing RLHDB3 coding by using STM320C54x series DSP chips through software programming, the coding characteristic of the invention is that the insertion of B00V codes is controlled by using a parity number mark which sets the mark number of 1 code between two V in an output data stream, positive and negative codes are controlled and output by setting the number of the parity numbers of the positive and negative codes with the mark number of 1 and B00V code group in the output data stream, and the coding rate is adjusted by adding a null operation instruction. Through CCS development environment simulation test, the preset RLHDB3 coding output is achieved, and the problems that the current coding mode lacks flexibility of change, is high in cost, occupies resource logic and is low in working rate, an LED lamp cannot be lightened when continuous 0 codes are transmitted, and the LED lamp cannot be lightened when-1 codes in HDB3 codes are transmitted, so that the lighting effect is influenced are solved;
(2) the program initialization mainly completes the setting of a pointer DP (0), the assignment of an initial value foe (0) and an initial value fpn (1), and stores three possible values of 0, +1 and-1 in the output of RLHDB3 by three units of 64 (named tpvl0), 65 (named tpvl1) and 66 (named tpvl1n) respectively for calling in the output process, thereby providing convenience for operation.
Drawings
FIG. 1 is a block diagram of the RLHDB3 encoding circuit provided by the present invention.
FIG. 2 is a flow chart of the method of the present invention.
FIG. 3 is a diagram illustrating memory space allocation according to the present embodiment.
FIG. 4 is a schematic diagram of an RLHDB3 encoding device in the present invention.
FIG. 5 is a schematic diagram of the simulated output waveforms of RLHDB3 in this embodiment,
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
The RLHDB3 coding has the characteristics that the direct current component in the signal transmission code is zero, the low-frequency component is less, the number of zero is not more than 3, and the clock signal is conveniently extracted from the code pattern, and the difficulty and the key of the coding are how to replace 4 continuous 0 codes into 000V or B00V code groups. According to the specified RLHDB3 encoding rule, in order to adapt to the program code of the DSP chip, the RLHDB 3code encoding rule is carefully analyzed, and the assignment of B and V is related to not only the inclusion of odd or even number of 1 between two V, but also the output of odd or even number of +1 code or-1 code, so that the assignment of B and V can be controlled by designing a flag signal. Based on the above analysis, the present invention provides a RLHDB3 encoding method based on DSP, as shown in fig. 1-2, which is implemented as follows:
s1, initializing RLHDB3 coding program of the DSP chip;
in this embodiment, as shown in fig. 3, memory space in the DSP chip is allocated, where (a) is pre-allocation to the memory, and (b) is an occupation situation of the memory after the program is run. The program initialization is mainly completed by setting the pointer DP equal to 0, assigning foe equal to 0, and assigning fpn equal to 1. In addition, three possible values of 0, +1 and-1 in the output of RLHDB3 are stored in three units of 64 (named tpvl0), 65 (named tpvl1) and 66 (named tpvl1n) respectively for calling in the output process.
In this embodiment, the foe flag is used to identify the number of parity codes with index 1 between two V's in the data stream. When foe is equal to 0, it indicates that there are an even number of (0, 2, 4, … …)1 codes between two destruction pulses V. When foe is equal to 1, it indicates that there are an odd number of (1, 3, 7, … …)1 codes between two V. When 1 code appears in the input data stream, the exclusive or operation of the foe flag and the value 1 is performed once, foe ═ foe ^ 1, and the value foe is changed between 0 and 1 alternately. At initial setup foe is 0, the destruction pulse V is +1, assuming an even number of codes 1, and the previous insertion V is-1. If the mark number in the input data stream is 1 code, foe changes the value of 0 and 1 once, and the positive and negative polarities of 1 code are alternated. When 4 consecutive 0 s appear, the insertion code group is 000V when foe is equal to 1, B is equal to 0, and the positive and negative polarities of V are the same as the polarities of 1 in the previous original codes. When foe is equal to 0, the insertion code group is B00V, and the positive and negative polarities of B, V codes are different from the polarities of 1 code in the former V code and original code. After each insertion of one code group 000V, B00V, foe is reset to 0.
In this embodiment, the fpn flag is used to identify the odd or even number of positive or negative codes with mark number 1, B00V code group in the output data stream. When fpn is equal to 0, it indicates that 1 code and B00V code block in the output code of RLHDB3 are an even number of (0, 2, 4, … …) negative pulses, wherein the in-phase pulse B, V in the B00V code block is counted as one pulse. When fpn is equal to 1, it indicates that 1 code and B00V code block in the output code of RLHDB3 are odd number of (1, 3, 5, … …) positive pulses, wherein the in-phase pulse B, V in the B00V code block is regarded as one pulse count. When 1 code and B00V code block appear in the data stream, the XOR operation of fpn flag and value 1 is performed once, fpn ═ fpn ^ 1. At initial setting fpn is 0. If the mark number in the data stream is 1 code or the insertion code group B00V, an exclusive-or operation fpn is performed to change the value from fpn to 1, and the value changes from 0 to 1, which means that the polarity of RLHDB3 changes once, and the dc component in the data stream is eliminated. When the 1 code or the insertion code group B00V appears, the polarity of B, V code in the 1 code or B00V is negative when the operation result fpn ═ fpn ≦ 1 ≦ 0. When the operation result fpn is fpn ≦ 1, the polarity of B, V code in code 1 or insertion code group B00V becomes positive. When the code group 000V is inserted, no operation of fpn ^ 1 is performed for fpn, and the polarity of the V code in 000V is negative when fpn is 0 and positive when fpn is 1.
S2, inputting data to be coded to a new address new _ data from the input port PA1 of the DSP chip by using an instruction PORTR, and loading the data to be coded to an accumulator A;
in this embodiment, the new data is input by inputting the data to be encoded from the input port PA1 to new _ data through the instruction PORTR, and then the input data is loaded to the accumulator a. Then, it is determined whether the input data is 0 or 1, and if 0 is input, the process for 0 is performed, and if 1 is input, the process for 1 is performed.
S3, judging whether the data to be coded is 0 value, if yes, processing the input 0 value and entering the step S4, otherwise, processing the input 1 value and entering the step S4;
the processing of the input 0 value in step S3 includes the steps of:
a1, performing minus 1 counting processing on the auxiliary register AR2, and judging whether the data input in the auxiliary register AR2 is a0 value, if so, processing input continuous 4 0 values, and entering step A2, otherwise, outputting the 0 value in the tpvl0 unit to the tmp unit, completing the processing of the input 0 value, and entering step S4;
a2, resetting the initial value of the count of the auxiliary register AR2 to 4, and judging whether the value of the flag signal foe is 1, if yes, indicating that the number of 1 is odd between two destruction pulses V, inserting 000V group codes, and entering step A3, otherwise, indicating that the number of 1 is even between two destruction pulses V, inserting B00V group codes, and entering step A6;
a3, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of positive and negative 1 are output, and entering step A4, otherwise, indicating that even number of positive and negative 1 are output, and entering step A5;
a4, outputting +1 in the tpvl1 unit to the tmp unit, resetting foe flag initial value foe-0, completing the processing of inputting 0 value, and proceeding to step S4;
a5, outputting-1 in the tpvl1n unit to the tmp unit, resetting foe the flag initial value foe to 0, completing the processing of inputting 0 value, and proceeding to step S4;
a6, where the initial value of the reset flag signal foe is foe ═ 0, and the flag signal fpn is xored with the value 1, the expression of the xor operation of the flag signal fpn with the value 1 is:
fpn←fpn⊕1；
a7, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of 1 are output, and entering step A8, otherwise, indicating that even number of 1 are output, and entering step A9;
a8, performing output assignment of tmp ═ tpvl1 and tmp +3 ═ tpvl1 respectively, completing the processing of the input 0 value, and proceeding to step S4;
a9, performing output assignment of tmp ═ tpvl1n ═ -1 and tmp +3 ═ tpvl1n ═ -1, respectively, completing processing of an input 0 value, and proceeding to step S4;
the processing of the input 1 value in step S3 includes the steps of:
b1, storing the count initial value 4 of the continuous 4 input detection values 0 in the auxiliary register AR2, and clearing the past count of the 0 value;
b2, performing xor operation of flag signal foe and value 1 and xor operation of flag signal fpn and value 1, respectively, updating the parity number flag signal of input 1 value and outputting the positive/negative code parity number flag signal;
the expression of the exclusive or operation of the flag signal foe with the value 1 is:
foe←foe⊕1；
the expression of the exclusive or operation of the flag signal fpn with the value 1 is:
fpn←fpn⊕1；
b3, judging whether the output data is a positive code according to the new output positive and negative code parity number flag signal fpn, if so, entering the step B4, otherwise, if so, outputting the data is a negative code, and entering the step B5;
b4, outputting +1 of tpvl1 unit to tmp unit, completing the processing of input 1 value, and proceeding to step S4;
b5, outputting-1 in tpvl1n unit to tmp unit, completing the processing of input 1 value, and proceeding to step S4;
s4, performing sliding processing on the 0 value and the 1 value processed in the step S3, outputting RLHDB3 codes, and finishing the RLHDB3 codes based on the DSP, wherein the realization method comprises the following steps:
c1, establishing a linear sliding window with a tmp unit as a starting address;
c2, copying tmp +3 to tmp +4, tmp +2 to tmp +3, tmp +1 to tmp +2 and tmp to tmp +1 respectively by using delay instructions, moving the data in the linear sliding window by one unit to the high address direction, and adjusting the RLHDB3 encoding rate by adding no-operation instructions;
c3, outputting tmp +4 to RLHDB3 output units, wherein if the value in the RLHDB3 output unit is +1, the value output to the output port PA0 of the DSP chip is +2 reference levels, if the value in the RLHDB3 output unit is 0, the value output to the output port PA0 of the DSP chip is +1 reference levels, and if the value in the RLHDB3 output unit is-1, the value output to the output port PA0 of the DSP chip is 0 reference levels;
c4, judging whether there is new input data, if yes, returning to step S1, otherwise, finishing RLHDB3 coding based on DSP.
In this embodiment, a linear sliding window with a tmp unit as a start address is established, and tmp +3 to tmp +4, tmp +2 to tmp +3, tmp +1 to tmp +2, and tmp to tmp +1 are copied by using a delay instruction, so that data in the linear sliding window moves by one unit in the high address direction. The objective is to determine the B value by depositing the first 3 rd cell tmp +4 of the tmp +1 cell of V in the B00V process. And finally, outputting tmp +4 to an output unit RLHDB3 unit, outputting to a port PA0, and then performing the next round of processing of new input data.
Example 2
As shown in fig. 4, the present invention further provides a RLHDB3 encoding device based on DSP, which includes a DSP chip module for executing encoding function, a RAM data storage for storing temporary data, a ROM program storage for storing execution program, an output driving circuit for increasing LED lamp load capacity, and an LED lamp connected to the output driving circuit for completing lighting and data transmission functions, wherein the DSP chip module is a C54xDSP chip module, and the DSP chip module and the RAM data storage include: the initialization unit is used for initializing the RLHDB3 coding program of the DSP chip; the acquiring unit is used for inputting data to be encoded to a new address new _ data from an input port PA1 of the DSP chip by using an instruction PORTR, and loading the data to be encoded to an accumulator A; the device comprises a detection unit, a processing unit and a processing unit, wherein the detection unit is used for processing data to be encoded, and the processing of the data to be encoded comprises the processing of an input 0 value or the processing of an input 1 value; a sliding processing unit for moving the 0 value or the 1 value processed by the detection unit to the high address direction and adjusting the RLHDB3 encoding rate by adding a no-operation instruction; and the output unit is used for outputting the RLHDB3 coding result based on the DSP chip.
In this embodiment, the initialization program specifically includes: the initial values of the pointer DP ═ 0, the assigned flag signal foe ═ 0, and the assigned flag signal fpn ═ 1 are set, and the 0, +1, and-1 values output from RLHDB3 are stored in tpvl0 unit, tpvl1 unit, and tpvl1n unit, respectively.
Example 3
The invention also provides RLHDB3 encoding equipment based on the DSP, which comprises a processor, a data temporary storage RAM memory and a ROM program memory for storing and executing programs; the ROM program memory has stored therein at least one instruction, at least one program, or a set of instructions that is loaded and executed by the at least one processor to perform the operations performed in the RLHDB3 encoding method of embodiment 1.
Example 4
The present invention also provides a computer readable storage medium having stored therein at least one instruction, at least one program, or a set of instructions that is loaded by at least one processor and executed in RAM memory to temporarily store encoded data to implement the operations performed in the RLHDB3 encoding method of embodiment 1.
In this embodiment, as shown in FIG. 5, when the above program is run in the CCS development environment, the output-B00-V + B00+ V00-1 +1-1+1 simulation waveforms when input 00000000001111 are shown in FIG. 5. In the RLHDB3 encoding process, the program paths for outputting +1, -1, and 0 codes are different, and the number of instructions executed is different, so the output code duration is different, which may cause the position of the output code to be jittered, and may cause the recognition error of the receiving end. The solution is as follows: the maximum number of clock cycles occupied by V of the output B00V is taken as the standard, the number of used cycles is taken as M, and the time occupied by the output symbol is adjusted by adding NOP null operation to other paths with less execution instruction number, so that the output durations of the 3 types of symbols are the same.
Further analysis shows that if N additional NOP instructions are added to each output branch to adjust the duration of each output code, different RLHDB 3code rates can be obtained, thereby being capable of adapting to the coding requirements of different transmission rates. Let the rate of RLHDB 3code be B, CLKOUT be the working clock of DSP, M be the number of cycles occupied by the longest branch in the coded output, and N be the number of additionally added cycles to control the transmission rate, so that the purpose of B adjustment can be achieved by adjusting N.
The invention provides a design scheme for realizing RLHDB3 coding by software programming by utilizing STM320C54x series DSP chips. The encoding method is characterized in that the insertion of B00V codes is controlled by using a parity number mark with the mark number of 1 code between two V in an output data stream, positive and negative codes are controlled and output by setting the number of the parity numbers of the positive and negative codes with the mark numbers of 1 and B00V code groups in the output data stream, the encoding rate is adjusted by adding a null operation instruction, and the preset RLHDB3 encoding output is achieved through CCS development environment simulation test. The RLHDB 3code is a common transmission code pattern in digital baseband transmission, and no scheme for realizing the coding of RLHDB3 by adopting a DSP chip is available at present, and the method for realizing the coding of RLHDB3 by utilizing the DSP chip has the advantages of high coding speed, adaptability to coding requirements of different transmission rates, relatively low cost and flexible application, and has better application value.
The invention solves the problems of lack of flexibility of change, high cost, resource logic occupation and low working rate in the existing coding mode through the design, and simultaneously solves the problem of high-speed data transmission while lighting by using the LED, in particular the problem that the illumination intensity is influenced by long-time LED turn-off caused by continuous 0 code transmission. The invention realizes RLHDB3 coding by using the DSP chip, has the advantages of fast coding, adaptability to coding requirements of different transmission rates, relatively low cost and flexible application, realizes that the LED lamp transmits data while lighting, reduces the influence of continuous transmission of 0 code on lighting to the minimum, and has better application value.

Claims (7)

  1. A RLHDB3 encoding method for a DSP, comprising the steps of:
    s1, initializing RLHDB3 coding program of the DSP chip;
    s2, inputting data to be coded to a new address new _ data from the input port PA1 of the DSP chip by using an instruction PORTR, and loading the data to be coded to an accumulator A;
    s3, judging whether the data to be coded is 0 value, if yes, processing the input 0 value and entering the step S4, otherwise, processing the input 1 value and entering the step S4;
    the processing of the input 0 value in step S3 includes the following steps:
    a1, performing minus 1 counting processing on the auxiliary register AR2, and judging whether the data input in the auxiliary register AR2 is a0 value, if so, processing input continuous 4 0 values, and entering step A2, otherwise, outputting the 0 value in the tpvl0 unit to the tmp unit, completing the processing of the input 0 value, and entering step S4;
    a2, resetting the initial value of the count of the auxiliary register AR2 to 4, and judging whether the value of the flag signal foe is 1, if yes, indicating that the number of 1 is odd between two destruction pulses V, inserting 000V group codes, and entering step A3, otherwise, indicating that the number of 1 is even between two destruction pulses V, inserting B00V group codes, and entering step A6;
    a3, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of positive and negative 1 are output, and entering step A4, otherwise, indicating that even number of positive and negative 1 are output, and entering step A5;
    a4, outputting +1 in the tpvl1 unit to the tmp unit, resetting foe flag initial value foe-0, completing the processing of inputting 0 value, and proceeding to step S4;
    a5, outputting-1 in the tpvl1n unit to the tmp unit, resetting foe the flag initial value foe to 0, completing the processing of inputting 0 value, and proceeding to step S4;
    a6, where the initial value of the reset flag signal foe is foe ═ 0, and the flag signal fpn is xored with the value 1, the expression of the xor operation of the flag signal fpn with the value 1 is:
    fpn←fpn⊕1；
    a7, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of 1 are output, and entering step A8, otherwise, indicating that even number of 1 are output, and entering step A9;
    a8, performing output assignment of tmp ═ tpvl1 and tmp +3 ═ tpvl1 respectively, completing the processing of the input 0 value, and proceeding to step S4;
    a9, performing output assignment of tmp ═ tpvl1n ═ -1 and tmp +3 ═ tpvl1n ═ -1, respectively, completing processing of an input 0 value, and proceeding to step S4;
    and S4, performing sliding processing on the 0 value or the 1 value processed in the step S3, outputting RLHDB3 codes, and finishing the RLHDB3 codes based on the DSP.
  2. 2. The RLHDB3 encoding method of the DSP of claim 1, wherein the step S1 specifically comprises: the pointer DP is set to 0, the initial value of the flag-given signal foe is 0, and the initial value of the flag-given signal fpn is 1, and 0, +1, and-1 values to be output by the RLHDB3 are stored in the tpvl0 unit, the tpvl1 unit, and the tpvl1n unit, respectively.
  3. 3. The RLHDB3 encoding method for DSP of claim 1, wherein the step S3 of processing the input 1 value includes the steps of:
    b1, storing the count initial value 4 of the continuous 4 input detection values 0 in the auxiliary register AR2, and clearing the past count of the 0 value;
    b2, performing xor operation of flag signal foe and value 1 and xor operation of flag signal fpn and value 1, respectively, updating the parity number flag signal of input 1 value and outputting the positive/negative code parity number flag signal;
    the expression of the exclusive or operation of the flag signal foe with the value 1 is:
    foe←foe⊕1；
    the expression of the exclusive or operation of the flag signal fpn with the value 1 is:
    fpn←fpn⊕1；
    b3, determining whether the output data is a positive code according to the new output positive and negative code parity number flag signal fpn, if so, entering step B4, otherwise, if the output data is a negative code, entering step B5;
    b4, outputting +1 of tpvl1 unit to tmp unit, completing the processing of input 1 value, and proceeding to step S4;
    b5, output-1 in tpvl1n unit to tmp unit, complete the processing of input 1 value, and proceed to step S4.
  4. 4. The RLHDB3 encoding method for DSP of claim 1, wherein the step S4 includes the steps of:
    c1, establishing a linear sliding window with a tmp unit as a starting address;
    c2, copying tmp +3 to tmp +4, tmp +2 to tmp +3, tmp +1 to tmp +2 and tmp to tmp +1 respectively by using a delay instruction, moving the data in the linear sliding window by one unit to the high address direction, and adjusting the RLHDB3 encoding rate by adding a no-operation instruction;
    c3, outputting tmp +4 to RLHDB3 output units, wherein if the value in the RLHDB3 output unit is +1, the value output to the output port PA0 of the DSP chip is +2 reference levels, if the value in the RLHDB3 output unit is 0, the value output to the output port PA0 of the DSP chip is +1 reference levels, and if the value in the RLHDB3 output unit is-1, the value output to the output port PA0 of the DSP chip is 0 reference levels;
    c4, judging whether there is new input data, if yes, returning to step S1, otherwise, finishing RLHDB3 coding based on DSP.
  5. 5. An RLHDB3 encoding apparatus for a DSP, comprising: a DSP chip module for executing coding function, a RAM data memory for storing temporary data respectively connected with the DSP chip module, a ROM program memory for storing execution program, an output drive circuit for increasing LED lamp load capacity, and an LED lamp connected with the output drive circuit for completing lighting and data transmission functions,
    the DSP chip module is a C54xDSP chip module;
    the DSP chip module and the RAM data memory comprise:
    the initialization unit is used for initializing the RLHDB3 coding program of the DSP chip;
    the acquiring unit is used for inputting data to be encoded to a new address new _ data from an input port PA1 of the DSP chip by using an instruction PORTR, and loading the data to be encoded to an accumulator A;
    the device comprises a detection unit, a processing unit and a processing unit, wherein the detection unit is used for processing data to be encoded, and the processing of the data to be encoded comprises the processing of an input 0 value or the processing of an input 1 value;
    the processing of the input 0 value comprises the following steps:
    a1, performing minus 1 counting processing on the auxiliary register AR2, and judging whether the data input in the auxiliary register AR2 is a0 value, if so, processing input continuous 4 0 values, and entering the step A2, otherwise, outputting the 0 value in the tpvl0 unit to the tmp unit, and finishing the processing of the input 0 value;
    a2, resetting the initial value of the count of the auxiliary register AR2 to 4, and judging whether the value of the flag signal foe is 1, if yes, indicating that the number of 1 is odd between two destruction pulses V, inserting 000V group codes, and entering step A3, otherwise, indicating that the number of 1 is even between two destruction pulses V, inserting B00V group codes, and entering step A6;
    a3, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of positive and negative 1 are output, and entering step A4, otherwise, indicating that even number of positive and negative 1 are output, and entering step A5;
    a4, outputting +1 in a tpvl1 unit to a tmp unit, resetting foe the initial value of the flag to foe-0, and completing the processing of inputting a0 value;
    a5, outputting-1 in a tpvl1n unit to a tmp unit, resetting foe the initial value of the flag to foe-0, and finishing the processing of inputting 0 value;
    a6, where the initial value of the reset flag signal foe is foe ═ 0, and the flag signal fpn is xored with the value 1, the expression of the xor operation of the flag signal fpn with the value 1 is:
    fpn←fpn⊕1；
    a7, judging whether the value of the flag signal fpn is equal to 1, if so, indicating that odd number of 1 are output, and entering step A8, otherwise, indicating that even number of 1 are output, and entering step A9;
    a8, respectively carrying out output assignment of tmp-tpvl 1 and tmp + 3-tpvl 1, and finishing the processing of an input 0 value;
    a9, respectively carrying out output assignment of tmp ═ tpvl1n ═ -1 and tmp +3 ═ tpvl1n ═ -1, and finishing the processing of an input 0 value;
    a sliding processing unit for moving the 0 value or the 1 value processed by the detection unit to the high address direction and adjusting the RLHDB3 encoding rate by adding a no-operation instruction;
    and the output unit is used for outputting the RLHDB3 coding result based on the DSP chip.
  6. 6. The RLHDB3 coding device of the DSP is characterized by comprising a processor, a data temporary storage RAM memory and a ROM program memory for storing an executive program; the ROM program memory has stored therein at least one instruction, at least one program, or a set of instructions that is loaded and executed by the at least one processor to perform the operations performed in the RLHDB3 encoding method of any one of claims 1-4.
  7. 7. A computer-readable storage medium having stored therein at least one instruction, at least one program, or a set of instructions for a ROM program memory, which is loaded by at least one processor and executed in RAM memory to temporarily store encoded data for performing the operations as claimed in any one of claims 1 to 4 in the RLHDB3 encoding method.
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