CN1571413A - A method and coder for baseband channel NRZ code stream to unipolar code stream conversion - Google Patents
A method and coder for baseband channel NRZ code stream to unipolar code stream conversion Download PDFInfo
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Abstract
The invention discloses a method which is used to transform the base band channel diszeroization binary system NRZ code flow to unipolarity and encoder. The HDB3 pre-coding circuit and CMI code circuit are formed to encoder to transform data current code pattern. The HDB3 pre-coding circuit utilizes the input clock signal to transform the NRZ code flow to HDB3 code flow, and correspondingly outputs V code indication information, B code indication information, B code polar indication information, and start code circuit indication information to CMI code circuit. The CMI code circuit reverses CMI code rule according to the coding identification to transform the indication information to code flow with composition CMI format to output. The method and encoder can realize the transformation function of the CMI coding with HDB3 pre-coding; moreover, the hardwired connection is simple and reliable, the transformed code flow is without spike.
Description
Technical Field
The invention relates to a baseband data signal processing technology in a communication system, in particular to a method and an encoder for converting a baseband channel non-return-to-zero binary NRZ code stream into a unipolar code stream.
Background
In the technical field of baseband data signal processing, the code identification inversion CMI code pattern with three-order high-density bipolar HDB3 precoding is generally simplified into an HDB3+ CMI code pattern. The CMI encoder with the HDB3 precoding is mainly applied to communication baseband encoding and is used for converting a unipolar non-return-to-zero NRZ code type data signal into a data stream in an HDB3+ CMI code type format. The HDB3+ CMI coding mode has the advantages of both HDB3 code pattern and CMI code pattern.
The code identification reversal CMI code is a quartic group interface code type which is recommended to be specified by CCITT, and the third-order high-density bipolar HDB3 code is a main transmission code type of the pulse code modulation PCM system. The technical documents and patent introduction about CMI coding and HDB3 coding are mainly related to the introduction of the implementation method of a single CMI coder or HDB3 coder. For example, U.S. Pat. No. 4, 5,510,786, "CMI ENCODERCIRCUIT" and U.S. Pat. No. 6,492,919, "Circuit System able for coding NRZ type binding signatures into CMI type binding signatures". Both patents disclose only hardware implementations of CMI encoders. While U.S. Pat. No. 4, 5,633,892 discloses a "Hybrid line coding method and apparatus using 4B/3T encoding for payload bits and 1B/1T encoding for decoding information" and U.S. Pat. No. 5,194,761 "wave mapping subsystem using converter and delay" nes ", both of which also disclose a hardware implementation method of the HDB3 encoder. None of the above related patents disclose a hardware implementation of a CMI encoder with HDB3 precoding. Because the HDB3 coding methods proposed by the HDB3 coding-related patents all convert NRZ code streams into bipolar code streams, and the CMI coding methods proposed by the CMI coding-related patents all convert NRZ code streams into unipolar code streams, the combination of the HDB3 coder and the CMI coder proposed by the above patents cannot realize the CMI coding conversion function with HDB3 precoding. Therefore, the method cited in the above patent can not directly realize that the NRZ code stream is pre-coded by the HDB3 and then the CMI transcoding function is performed.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method and a coder for converting a baseband channel NRZ code stream into a unipolar code stream, which can realize a function of converting a pre-coded CMI code with HDB 3.
In order to achieve the above object, the present invention provides a method for converting a baseband channel NRZ code stream into a unipolar code stream, which is characterized by comprising the following steps:
and 3, receiving the V code indication signal, the B code indication signal, the corresponding B code polarity indication signal and the corresponding start coding circuit indication signal, and converting the V code indication signal, the B code polarity indication signal and the start coding circuit indication signal into a code stream in a CMI format for output according to a coding identification reversal CMI coding rule.
The method is characterized in that in step 2, when the number of the continuous 0 codes in the NRZ code stream is not more than 3, the 0 code in the binary sequence is still encoded as the 0 code; the 1 codes in the binary sequence are alternately coded into +1 codes and-1 codes and respectively marked as B + and B-; and when 4 continuous 0 codes appear in the NRZ code stream, replacing the 4 continuous 0 codes by a replacing node BOOV or 000V, wherein B represents a mark meeting the polarity alternation rule, and V represents a mark destroying the polarity alternation rule.
The method described above, wherein in step 3, the B-code or the V-code is replaced with 00 codes; replacing the B + code or the V + code with the 11 code; the code 0 is replaced by a code 01.
In order to better achieve the above object, the present invention further provides an encoder for converting a baseband channel non-return-to-zero binary code stream into a unipolar code stream, which is characterized in that: comprises a three-order high-density bipolar HDB3 precoding circuit and a coded identifier inversion CMI coding circuit, wherein,
the HDB3 pre-coding circuit is used for performing three-order high-density bipolar HDB3 code stream conversion processing on a unipolar non-return-to-zero NRZ code stream by using the input clock signal and correspondingly outputting a V code indication signal, a B code polarity indication signal and a start coding circuit indication signal;
the CMI coding circuit is provided with a V code indicating signal input interface, a B code polarity indicating signal input interface, a starting coding circuit indicating signal input interface and a CMI format code stream output interface, and is used for receiving a V code indicating signal, a B code polarity indicating signal and a starting coding circuit indicating signal output by the three-order high-density bipolar HDB3 precoding circuit and converting the indicating signals into a CMI format code stream according to a coding identifier reversal CMI coding rule to output.
The encoder is characterized in that: the three-order high-density bipolar HDB3 precoding circuit comprises a shift register, a D trigger, a B code number recording register, a B code polarity recording register, an HDB3 encoding starting counter and a plurality of combinational logic devices; the shift register is used for receiving an NRZ code stream and a clock signal, and outputting a V code indicating signal and a B code indicating signal after being connected with the combinational logic device, the D trigger and the B code number recording register; the HDB3 coding start counter is configured to receive the clock signal, and on one hand, connect the B-code polarity recording register to output a B-code indication signal and a corresponding B-code polarity indication signal, and on the other hand, output a start coding circuit indication signal.
The encoder is characterized in that: the shift register is a 4-bit shift register and is used for detecting 4 continuous 0 codes in the input NRZ code stream.
The encoder is characterized in that the combinational logic device is any one of an and gate, an or gate and a not gate, or any combination thereof.
The encoder is characterized in that the HDB3 encodes a start counter of 3bit for starting counting from reset, stops counting when the count value reaches 4, and outputs a start encoding circuit indication signal.
The encoder as described above, wherein said coded flag reversal CMI encoding circuit comprises a clock positive edge triggered register XDP _ P, a clock negative edge triggered register XDN _ N, a clock negative edge triggered register XDP _ N, and a plurality of selectors and a plurality of combinational logic devices; wherein,
the register XDP _ P is used for negating and registering an XDP _ P value stored in the previous beat when a clock positive edge samples that an HDB3 precoding output indicating signal is 0 code; when the clock positive edge samples that the data after the HDB3 is pre-coded is B code or V code, the register XDP _ P is kept unchanged;
the register XDN _ N is used for keeping the register XDN _ N unchanged when the clock negative edge samples that the HDB3 precoding output indication signal is V code, and the register value of each other clock negative edge sampling time is automatically inverted and registered;
the register XDP _ N is used for negating and registering the value of the XDP _ P if the polarity indication is "-" when the clock negative edge samples that the HDB3 precoding output indication signal is V code; if the polarity indication at this time is "+", the register XDP _ N registers the value of XDP _ P; when the negative edge of the clock samples the HDB3 precoding output signal as B code, the register XDP _ N registers the XDN _ N output value, and when the negative edge of the clock samples the HDB3 precoding output indication signal as 0 code, the register XDP _ N registers the XDP _ P value.
And the output signal of the register XDP _ N is XOR-ed with the output signal of the register XDP _ P so as to output the CMI format code stream.
The encoder is characterized in that the combinational logic device is any one of a nor gate, an exclusive or gate, an exclusive nor gate and a nor gate, or any combination thereof.
The HDB3+ CMI encoder hardware circuit provided by the patent can simply and effectively realize that NRZ code stream is pre-coded through HDB3, then CMI format conversion function is carried out, and the NRZ code stream can be directly realized by the hardware circuit. The hardware circuit only needs a clock with the same rate as the NRZ code type data flow, does not need a clock with the frequency multiplication of the NRZ code type data flow rate 2, and directly converts the NRZ code flow into a CMI code flow pre-coded by HDB 3.
The HDB3+ CMI coding hardware circuit has the characteristics of simplicity, reliability, no burr of converted code stream and the like.
Embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Drawings
FIG. 1 is a data flow composition for converting NRZ patterns to HDB3+ CMI patterns according to the present invention.
FIG. 2 is an overall block diagram of an implementation of the HDB3+ CMI encoding circuit of the present invention.
Fig. 3 is a hardware circuit of the HDB3 precoding section of the present invention.
FIG. 4 is a hardware circuit of the CMI encoding portion of the present invention.
Fig. 5a and 5b disclose the "01" waveform construction process.
FIG. 6 discloses the construction process in which "00" and "11" appear alternately.
FIG. 7 discloses the complete construction of HDB3+ CMI encoding.
Detailed Description
In the communication baseband data signal coding, the HDB3+ CMI code pattern is a binary line code pattern, which not only has the advantage of biphase code, but also can avoid long-link '0' in transmission and can provide certain error detection capability. In an embodiment of the invention, FIG. 1 illustrates the conversion of NRZ pattern data streams to HDB3+ CMI patterns.
The HDB3+ CMI encoding method is briefly described below: data of NRZ patterns are pre-coded into HDB3 format and then converted into CMI patterns according to CMI coding rules.
First step HDB3 precoding:
when the number of the continuous '0' codes in the code stream is not more than 3, the '0' in the binary sequence is still coded into '0'; while "1" in the binary sequence is alternately coded as "+ 1" and "-1" and respectively labeled as "B +" and "B-".
When 4 consecutive "0" s occur in the stream, the 4 consecutive "0" s are replaced with a specific code group, which is called a replacement section ("B00V" or "000V"). Wherein B represents the mark conforming to the polarity alternation rule, and V represents the mark destroying the polarity alternation rule. The two substitution nodes are selected according to the following principle: the number of B pulses between any two adjacent V pulses is made to be an odd number. And the principle of polarity alternation and inversion of the V code and the principle of polarity alternation and inversion of the B code are satisfied.
And a second step of CMI coding:
and replacing the 'B-' or 'V-' obtained by the precoding conversion of the previous step by '00'.
And replacing the B + or V + obtained by the precoding conversion of the previous step by 11.
And replacing the 0 obtained by the precoding conversion of the previous step by 01.
In fig. 2, 3 and 4, an embodiment of the present invention is an encoder 10 for baseband channel data stream pattern conversion, comprising a three-stage high density bipolar HDB3 precoding circuit 1 and a code label inversion CMI coding circuit 2.
Fig. 2 shows an overall block diagram for implementing the HDB3+ CMI encoding circuit, in which the HDB3 precoding circuit 1 is mainly used to complete the functions of converting an input NRZ code pattern into a V code and a B code, outputting a corresponding B code polarity indication, starting an encoding circuit indication, and the like. The HDB3 precoding circuit 1 has a data input interface 11(DataIn), a clock signal input interface 12(XCLK), and a reset signal interface 13(reset), and generates a V code indication signal 14(HDB3_ V), a B code indication signal 15(HDB3_ B), a B code polarity indication signal 17(Insert _ B), and a Start code indication signal 16(HDB3_ Start), which are input to the CMI coding section. The CMI encoding circuit 2 has a code stream 25(code _ out) output for mainly realizing conversion of the V code indication signal 14(HDB3_ V), the B code indication signal 14(HDB3_ B), and the B code polarity indication signal 17(Insert _ B) into a CMI format.
Fig. 3 shows an HDB3 precoding circuit, which includes a 4-bit shift register 111, a B-code number recording register 181, a B-code polarity recording register 182, an HDB3 code enable counter 121, 1D flip-flop 18, and some combinational logic devices U1, U3, U4, U5, U6, U7, and U8.
The 4-bit shift register 111 is not a strict shift register, and is used to detect 4 consecutive "0" s in the input NRZ code stream. If 4 consecutive '0's appear in the NRZ code stream, the output of U1 is '1', the input D terminal of D flip-flop 18 is '1', and the input terminal of the 2 nd bit register in the 4-bit shift register 111 is '1', so the last '0' in the 4 consecutive '0's appearing in the NRZ code stream is changed to '1' in the shift register.
The D flip-flop 18 is configured to indicate that 4 consecutive "0" s occur in the NRZ code stream, and when 4 consecutive "0" s occur in the 4-bit shift register 111, the output of the D flip-flop 18 with the input D terminal being U1 and the output of U7 are obtained by combining U8 or a gate, so that the input D terminal of the D flip-flop 18 is "1" at this time. When the second and third "0" of 4 consecutive "0" in the NRZ code stream are shifted into the 0 th shift register, the output of U7 is the output Q value of D flip-flop 18, and the output of U1 is "0", so the input D of D flip-flop 18 is its own Q output value at this time, that is, D flip-flop 18 keeps "1" at this time. When the last "0" of 4 consecutive "0" in the NRZ code stream, that is, the code stream modified to "1" is shifted into the 0 th shift register, the output of U7 is "0", the output of U1 is also "0", and therefore the input D terminal of D flip-flop U2 is "0" at this time. When no 4 consecutive "0" s appear in the NRZ code stream, the output of U1 is "0", and the output of U7 is also "0", so that the D flip-flop 18 remains "0" at this time.
The V code indicating signal 14(HDB3_ V) is the output of the U3 and gate, and when the last "0" of the 4 consecutive "0" in the NRZ code stream, i.e., the code stream modified to "1", is shifted into the 0 th shift register, the output of the 0 th shift register is "1", and the output of the D flip-flop 18 is also "1", so the output of U3 is "1", which indicates the presence of a V code in the NRZ code stream.
The B code indication signal 15(HDB3_ B) is the output of the U6 or gate, when no 4 consecutive "0" s appear in the NRZ code stream, the output Q terminal of the D flip-flop 18 is "0", and at this time, if the output of the 0 th shift register is "1", the output of U4 is "1" to indicate that the B code appears in the NRZ code stream. If 4 consecutive '0's appear in the NRZ code stream, the output of U1 is '1', and if the output of B code number recording register 181 is '0' (indicating that the number of B codes appearing before is an even number), the output of U5 is '1', the output of U6 is also '1', indicating that 4 consecutive '0's appear in the NRZ code stream, and the node needs to be replaced by 'BOOV'.
The B-code number register 181 records only the parity number of "1" appearing in the 0 th bit shift register when the D flip-flop output is "0".
The B-code polarity recording register 182 records only the number of parities for which the output of the U6 or gate is "1" when the Start encode circuit instruction signal 16(HDB3_ Start) is "1", that is, the number of parities for which the B-code instruction signal 15(HDB3_ B) appears, and outputs a B-code polarity instruction signal 17(Insert _ B).
The HDB3 encodes the Start counter 121 to be a 3-bit counter, starts counting from reset, stops counting when the count value reaches 4, and outputs the encoded Start indication signal 16(HDB3_ Start) to be "1".
In fig. 4, the present invention provides a CMI coding circuit 2, which includes 3D flip-flops, 2 selectors, 5 nor gates, 2 exclusive-or gates, 1 exclusive-nor gate, and 3 not gates. The encoding start indication signal 16(HDB3 start) indicates that HDB3 precoding has started for starting the CMI encoding circuit 2.
The value of the D input terminal of the D flip-flop 28(XDP _ P) is obtained by combining the values of the encoded Start indication signal 16(HDB3_ Start), the V code indication signal 14(HDB3_ V), and the B code indication signal 15(HDB3_ B) input through the U27 (nor gate), U28 (exclusive nor gate), U29 (nor gate) and the Q output terminal of the D flip-flop 28(XDP _ P). The logic expression of the Verilog language of the D-side input D-side of the D flip-flop 28(XDP _ P) is:
DXDP_P＝(～(HDB3_B|HDB3_V))^Q。
if the values of the V code indication signal 14(HDB3_ V) and the B code indication signal 15(HDB3_ B) are both "0", the D flip-flop 28(XDP _ P) inverts the value of the output Q terminal and inputs the inverted value to the input D terminal of the D flip-flop 28(XDP _ P), so that the output Q terminal of the D flip-flop 28(XDP _ P) generates transitions of "0- > 1" or "1- > 0"; if the values of the V code indication signal 14(HDB3_ V) and the B code indication signal 15(HDB3_ B) are "1", the D flip-flop 28(XDP _ P) will remain unchanged.
The value of the input D terminal of the D flip-flop 27(XDP _ N) is obtained by combining the values of the encoded start signal 16(HDB3_ start), the B polarity record signal 17(Insert _ B), the V code indication signal 14(HDB3_ V) and the B code indication signal 15(HDB3_ B) through U22 (nor gate), U24 (exclusive or gate), U33 (selector), U26 (nor gate) with the Q output terminal of the D flip-flop 26(XDN _ N) and the Q output terminal of the D flip-flop 28(XDP _ P). The logic expression of Verilog language at the input D-side of the D flip-flop 27(XDP _ N) is:
DXDP_N＝((~HDB3_B)&(((～HDB3_V)| Insert_B)^QXDP_P))|(HDB3_B
&QXDN N)。
if the values of the B code indicating signal 15(HDB3_ B) and the V code indicating signal 14(HDB3_ V) are both "0", the D flip-flop 27(XDP _ N) inputs the value of the output Q terminal of the D flip-flop 28(XDP _ P) to the input D terminal of the D flip-flop 27(XDP _ N).
If the value of the B-code indicating signal 15(HDB3_ B) is "1", the D flip-flop 27(XDP _ N) inputs the value of the output Q terminal of the D flip-flop 26(XDN _ N) to the input D terminal of the D flip-flop 27(XDP _ N).
If the value of V code indicating signal 14(HDB3_ V) is "1" and Insert B is "0", D flip-flop 27(XDP _ N) inverts the value of the output Q of D flip-flop 28(XDP _ P) and inputs the inverted value to the input D of D flip-flop 27(XDP _ N).
If the value of the V code indicating signal 14(HDB3_ V) is "1" and the value of the B code indicating signal 15(HDB3_ B) is "1", the D flip-flop 27(XDP _ N) inputs the value of the output Q terminal of the D flip-flop 28(XDP _ P) to the input D terminal of the D flip-flop 27(XDP _ N).
The value of the input D terminal of the D flip-flop 27(XDN _ N) is obtained by combining the values of the input signals HDB3_ start, HDB3_ V through U22 (selector) and U30 (nor gate) with the value of the output Q terminal of the D flip-flop 26(XDN _ N). The logic expression of the Verilog language of the D-side input D-side of the D flip-flop 26(XDN _ N) is:
DXDN_N＝(~QXDN_N) & (~HDB3_V)|(QXDN_N & HDB3_V)
if the value of the V code indication signal 14(HDB3_ V) is "1", the D flip-flop 26(XDN _ N) will remain unchanged, and conversely, the D flip-flop 27(XDN _ N) inputs the value of the output Q terminal of the D flip-flop 27(XDN _ N) to the input D terminal of the D flip-flop 27(XDN _ N).
The output CMI code stream 25(code _ out) of the CMI encoding circuit 2 is obtained by the difference or difference of the Q-terminal values output by the D flip-flop 27(XDP _ N) and the D flip-flop 28(XDP _ P) through U31 (exclusive or gate).
The method and process of converting the V-code indication signal 14(HDB3_ V), the B-code indication signal 15(HDB3_ B), and the polarity indication signal 17(Insert _ B) into CMI format code streams according to the present invention are further described in detail below with reference to fig. 5a, 5B, 6, and 7.
In the embodiment of the invention, the CMI coding circuit respectively adopts an XDP _ P register triggered by a clock positive edge, an XDN _ N register triggered by a clock negative edge and an XDP _ N register triggered by a clock negative edge.
If the HDB3_ V or HDB3_ B signal inputted to the CMI encoding circuit 2 is "0", the XDP _ P register inverts the XDP _ P value stored in the previous beat and registers the inverted XDP _ P value, so that the output Q of the XDP _ P register generates a transition of "0- > 1" or "1- > 0". The XDP _ N register registers the output of the XDP _ P register so that the output of the XDP _ P register is XOR-ed with the output of the XDP _ N register to create a "01" waveform. Fig. 5a and 5b show the "01" waveform construction process.
If the input HDB3_ V or HDB3_ B signal to the CMI encoding circuit 2 is "1", the XDP _ P register remains unchanged, which ensures that when HDB3 is precoded as a B code or a V code, the XDP _ P and XDP _ N are different or only "11" or "00" waveforms can be obtained, and no "01" waveform is formed.
From the XDP _ P register characteristics described above, the following rules can be derived:
when the two B/V codes or the 0 code between the two B/V codes are odd numbers, the XDP _ P register values obtained at the two sampling moments are mutually reversed.
And when the two B/V codes or the 0 code between the two B/V codes is an even number, the XDP _ P register values obtained at the two sampling moments are the same.
When the B/V codes appear continuously, the XDP _ P register values obtained at the sampling moments are the same.
The XDN _ N register automatically reverses the register value every time the negative edge of the clock is sampled, and the following rule can be obtained;
and when the two B/V codes or the 0 code between the two B/V codes are odd numbers, the XDN _ N register values obtained at the two sampling moments are the same.
When the two B/V codes or the 0 code between the two B/V codes are even numbers, the XDN _ N register values obtained at the two sampling moments are mutually reversed.
When the B/V codes continuously appear, the XDN _ N register values obtained at the sampling moments are reciprocal.
It follows that, without considering the V code, the XDN _ N signal is xored with the XDP _ P signal to obtain "00" and "11" which always alternate. FIG. 6 shows the construction process in which "00" and "11" appear alternately.
Since the occurrence of the V code destroys the rule that "00" and "11" appear alternately, the function of the XDN _ N register needs to be slightly modified, and the characteristic that the polarity destruction waveform also appears in the output CMI + HDB3 transcoding when the V code occurs is obtained.
The modified XDN _ N register characteristics are as follows: if the HDB3_ V signal input to the CMI encoding circuit is "1", the XDN _ N register remains unchanged, otherwise, the XDN _ N register inverts the output value of the XDN _ N of the previous beat and registers the inverted output value. This ensures that the HDB3 precoded B-code can be distinguished from XDP-P by XDN _ N or that "00" and "11" always alternate. However, for V-codes, the "00" or "11" substitution cannot be correctly achieved by merely xoring XDN with XDP _ P, so register XDP _ N assistance is also needed to achieve the correct conversion of V-codes.
When the HDB3_ V signal input to the CMI encoding circuit is "1", the input of the register XDP _ N is determined by the polarity indication obtained by the HDB3 precoding and the value of the XDP _ P register. If the polarity is indicated as "-", the XDP _ N register inverts the output value of the XDP _ P register and registers the inverted output value, so that the output of the XDP _ N register is different from the output of the XDP _ P register or "00" is obtained; if the polarity is indicated as "+", the XDP _ N register registers the output value of the XDP _ P register so that the XDP _ N register output is different from the XDP _ P register output or is available as "11". When the HDB3_ B is "1", the XDP _ N register registers an output value of the XDN _ N register, and when both the HDB3_ V and HDB3_ B are "0", the XDP _ N register registers an output value of the XDP _ P register.
And finally, carrying out XOR on the output value of the XDP _ N register and the output value of the XDP _ P register to obtain the code stream in the CMI format. Fig. 7 shows the HDB3+ CMI transcoding process in the presence of a V code.
Claims (10)
1. A method for converting a baseband channel non-return-to-zero binary code stream into a unipolar code stream is characterized by comprising the following steps:
step 1, receiving a unipolar non-return-to-zero NRZ code stream of a baseband channel, and simultaneously inputting a clock signal;
step 2, performing three-order high-density bipolar HDB3 code stream conversion processing on the unipolar non-return-to-zero NRZ code stream by using the clock signal, thereby respectively outputting a V code indication signal, a B code indication signal, a corresponding B code polarity indication signal and a start coding circuit indication signal;
and 3, receiving the V code indication signal, the B code indication signal, the corresponding B code polarity indication signal and the indication signal for starting the coding circuit, and converting the V code indication signal, the B code indication signal, the corresponding B code polarity indication signal and the indication signal for starting the coding circuit into a code stream in a CMI format for output according to a coding identification reversal CMI coding rule.
2. The method of claim 1, wherein in step 2, when the number of consecutive 0 codes in the NRZ code stream is not more than 3, the 0 code in the binary sequence is still encoded as the 0 code; the 1 codes in the binary sequence are alternately coded into +1 codes and-1 codes and respectively marked as B + and B-; and when 4 continuous 0 codes appear in the NRZ code stream, replacing the 4 continuous 0 codes by a replacing node BOOV or 000V, wherein B represents a mark meeting the polarity alternation rule, and V represents a mark destroying the polarity alternation rule.
3. The method of claim 2, wherein in step 3, the B-code or the V-code is replaced with 00 codes; replacing the B + code or the V + code with the 11 code; the code 0 is replaced by a code 01.
4. An encoder for converting a baseband channel non-return-to-zero binary code stream into a unipolar code stream, comprising: comprises a three-order high-density bipolar HDB3 precoding circuit and a coded identifier inversion CMI coding circuit, wherein,
the HDB3 pre-coding circuit is used for performing three-order high-density bipolar HDB3 code stream conversion processing on a unipolar non-return-to-zero NRZ code stream by using the input clock signal and correspondingly outputting a V code indication signal, a B code polarity indication signal and a start coding circuit indication signal;
the CMI coding circuit is provided with a V code indicating signal input interface, a B code polarity indicating signal input interface, a starting coding circuit indicating signal input interface and a CMI format code stream output interface, and is used for receiving a V code indicating signal, a B code polarity indicating signal and a starting coding circuit indicating signal output by the three-order high-density bipolar HDB3 precoding circuit and converting the indicating signals into a CMI format code stream according to a coding identifier reversal CMI coding rule to output.
5. The encoder of claim 4, wherein: the three-order high-density bipolar HDB3 precoding circuit comprises a shift register, a D trigger, a B code number recording register, a B code polarity recording register, an HDB3 encoding starting counter and a plurality of combinational logic devices; the shift register is used for receiving an NRZ code stream and a clock signal, and outputting a V code indicating signal and a B code indicating signal after being connected with the combinational logic device, the D trigger and the B code number recording register; the HDB3 coding start counter is configured to receive the clock signal, and on one hand, connect the B-code polarity recording register to output a B-code indication signal and a corresponding B-code polarity indication signal, and on the other hand, output a start coding circuit indication signal.
6. The encoder of claim 4, wherein: the shift register is a 4-bit shift register and is used for detecting 4 continuous 0 codes in the input NRZ code stream.
7. The encoder of claim 5, wherein the combinational logic device is any one of an AND gate, an OR gate, a NOT gate, or any combination thereof.
8. The encoder as claimed in claim 4, 5,6 or 7, wherein the HDB3 encodes the start counter as a 3-bit counter for counting from reset, stopping counting when the count value reaches 4, and outputting a start encoding circuit indication signal.
9. The encoder of claim 4 wherein the encoding identification reversal CMI encoding circuit comprises a clock positive edge triggered register XDP _ P, a clock negative edge triggered register XDN _ N, a clock negative edge triggered register XDP _ N, and a plurality of selectors and a plurality of combinational logic devices; wherein,
the register XDP _ P is used for negating and registering an XDP _ P value stored in the previous beat when a clock positive edge samples that an HDB3 precoding output indicating signal is 0 code; when the clock positive edge samples that the data after the HDB3 is pre-coded is B code or V code, the register XDP _ P is kept unchanged;
the register XDN _ N is used for keeping the register XDN _ N unchanged when the clock negative edge samples that the HDB3 precoding output indication signal is V code, and the register value of each other clock negative edge sampling time is automatically inverted and registered;
the register XDP _ N is used for negating and registering the value of the XDP _ P if the polarity indication is "-" when the clock negative edge samples that the HDB3 precoding output indication signal is V code; if the polarity indication at this time is "+", the register XDP _ N registers the value of XDP _ P; when the negative edge of the clock samples the HDB3 precoding output signal as B code, the register XDP _ N registers the XDN _ N output value, and when the negative edge of the clock samples the HDB3 precoding output indication signal as 0 code, the register XDP _ N registers the XDP _ P value.
And the output signal of the register XDP _ N is XOR-ed with the output signal of the register XDP _ P so as to output the CMI format code stream.
10. The encoder of claim 9, wherein the combinational logic device is any one of a nor gate, an xor nor gate, a nor gate, or any combination thereof.
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