TWI271958B - Transmitting apparatus of serial transmission - Google Patents
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- TWI271958B TWI271958B TW94126378A TW94126378A TWI271958B TW I271958 B TWI271958 B TW I271958B TW 94126378 A TW94126378 A TW 94126378A TW 94126378 A TW94126378 A TW 94126378A TW I271958 B TWI271958 B TW I271958B
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1271958 九、發明說明: 【發明所屬之技術領域】 本發明係一用於串列傳輸之傳輸裝置,尤指 該傳輸碼用於差動4-脈衝振幅調變信號之串列 傳輸系統,達到有效降低時脈回復時所產生的資 料轉換邊界抖動之特性。 ^ I 【先前技術】 在串列的連接資料通信過程中,資料的時脈 並沒有與資料一同傳送。在接收端產生的本地時 脈,造成的相位干擾,或是在時脈取樣時所存在 的相位排列問題,在接收高速資料時也同時存在 =貝料轉換邊界抖動之問題,上述之問題都會影響 > 整體系統之性能。因此在接收端時脈產生和時序 回復對於一個高速傳輸信號系統是非常重要與 關鍵的功能。 利用8B/10B編碼之資料傳輸機制,已成為 今曰南速串列傳輸的標準。它是實際硬體層的一 4刀’並且可能是被用於任何十億位元乙太網路 (Gigabit Ethernet)、百億位元乙太網路〇〇 Gigabit 5 12719581271958 IX. Description of the invention: [Technical field of the invention] The present invention relates to a transmission device for serial transmission, in particular to a serial transmission system for a differential 4-pulse amplitude modulation signal, which is effective Reduces the characteristics of the data transition boundary jitter produced by the clock recovery. ^ I [Prior Art] In the serial connection data communication process, the data clock is not transmitted with the data. The local clock generated at the receiving end, the phase interference caused, or the phase alignment problem existing in the clock sampling, when there is high-speed data, there is also the problem of the bump transition boundary jitter, and the above problems will affect > Performance of the overall system. Therefore, clock generation and timing recovery at the receiving end are very important and critical functions for a high speed transmission signal system. The data transmission mechanism using 8B/10B encoding has become the standard for the transmission of serial transmissions in the south. It is a 4 knives of the actual hardware layer and may be used for any Gigabit Ethernet, Gigabit Ethernet, Gigabit 5 1271958
Ethernet)’自動櫃員機(ATM),無線或者光纖的 傳輸鏈路等。它包含連續的編碼與解碼規則,與 資料連接層溝通之特別的指令和錯誤偵察的能 力。根據其編碼機制能夠產生直流平衡之位元串 歹J貝料’主要疋因為此位元串列資料保含相等的 正和負脈衝數量❶而直流平衡的目的,主要是為 了避免因交流柄合造成信號的失真。並提供 的時序資訊,每傳輸5位元資料至少為有二資料 轉換給接收端做時序回復,並且增加檢測在資料 的輸送期間所產生之單一或多錯誤的可能性。 雖然上述之習知技術,可達到高速串列傳 輸,但是無法降低時脈回復時所產生的資料轉換 邊界抖動,及傳送每10位元,會有一固定的資 料轉換提供接收端快速作時序同步。故,一妒習 用者係無法符合使用者於實際使用時之所需^ 【發明内容】 因此,本發明主要目的係在於,利用—傳輸 碼甩於一差冑4_脈衝振幅調變信號之串列傳輸 系統,達财效降低時脈回復時所產生的資料轉 I271958 換邊界抖動之特性。 為達上述之目的,本發明係一用於串列傳輸 之傳輸裝置,其傳輸碼係為—心脈衝振幅調變對 稱式傳輸碼,制於該差動4_脈衝振幅調變信號 之串列傳輸系統,其包含至少一以上之4_脈衝: U調變對稱式編碼裝置、一傳送裝置、一傳送介Ethernet) 'Automatic Teller Machine (ATM), wireless or fiber optic transmission link. It contains continuous encoding and decoding rules, special instructions and error reconnaissance capabilities to communicate with the data connection layer. According to its coding mechanism, it can generate the DC balance of the bit string 歹J shell material 'mainly because this bit string data contains the same number of positive and negative pulses, and the purpose of DC balance, mainly to avoid the AC handle The distortion of the signal. The timing information is provided, and at least two data transmissions are converted to the receiving end for timing recovery, and the possibility of detecting single or multiple errors generated during the data transmission period is increased. Although the above-mentioned conventional techniques can achieve high-speed serial transmission, the data switching boundary jitter generated when the clock is recovered cannot be reduced, and every 10 bits transmitted, there is a fixed data conversion to provide the receiver with fast timing synchronization. Therefore, the user can not meet the needs of the user in actual use. [Inventive content] Therefore, the main object of the present invention is to use a transmission code 甩 to a string of 4 脉冲 pulse amplitude modulation signals. The column transmission system, which reduces the characteristics of the data generated by the clock recovery when the clock is restored to I271958. For the purpose of the above, the present invention is a transmission device for serial transmission, wherein the transmission code is a heart pulse amplitude modulation symmetric transmission code, and is formed in the series of the differential 4_pulse amplitude modulation signal. a transmission system comprising at least one or more 4_pulses: a U-modulation symmetric coding device, a transmission device, and a transmission medium
面、一接收裝置、一時序回復裝置及至少一以上 之4-脈衝振幅調變對稱式解碼裝置。 【實施方式】a receiving device, a timing recovery device and at least one 4-pulse amplitude modulation symmetric decoding device. [Embodiment]
喷參閱『第1圖』所示,係為本發明差動4· 脈衝振幅調變信號之串列傳輸系統架構示意 圖。如圖所不:該差動4-脈衝振幅調變信號之串 列傳輸系統架構係包含至少一以上之4_脈衝振 幅調變對稱式編碼裝置la、lb、一傳送裝置2、 一傳輸介面3、一接送裝置4、一時序回復裝置5 及至夕 以上4 _脈衝振幅調變對稱式解碼裝置 6a、6b。其傳輸方法係為輸入一 16位元平行資 料,該16位元平行資料分為一最高有效位元資 料及一最低有效位元資料。其中,該最高有效位 7 1271958The spray is shown in Fig. 1 and is a schematic diagram of the serial transmission system architecture of the differential 4·pulse amplitude modulation signal of the present invention. As shown in the figure, the serial transmission system architecture of the differential 4-pulse amplitude modulation signal includes at least one of 4_pulse amplitude modulation symmetric coding devices la, lb, a transmission device 2, and a transmission interface 3. A pick-up device 4, a time-series recovery device 5, and 4 _ pulse amplitude modulation symmetric decoding devices 6a, 6b. The transmission method is to input a 16-bit parallel data, and the 16-bit parallel data is divided into a most significant bit data and a least significant bit data. Where the most significant bit 7 1271958
兀資料及該最低有效位元係為8位元,分別輪入 至該4-脈-衝振幅調變對稱式編碼裝置以,、 行編碼並得到一 10位元資料,且輸入至該傳2 裝置2。該傳送裝置2係包含一心脈衝振幅調= 之調變裝置,調變為多組差動4_脈衝振幅調變信 號。該差動4-脈衝振幅調變信號係具有1〇組, 藉由該傳輸介面3傳送至該接收装置4。該接收 裝置4係包含一 4-脈衝振幅調變解調變裝置,解 調變該差動4-脈衝振幅調變信號為一 2〇位元資 料並輸入至該時序回復裝置5,該2〇位元資料經 資料轉換後,該20位元資料分為各1〇位元資 料及10位元資料輸入至該4-脈衝振幅調變對 稱式解碼裝置6a、6b進行解碼,得到各8位元 負料’合併為16位元資料輸出。 睛參閱『第2圖』所示,係為本發明編碼方 法流程圖。如圖所示:輸入一 8位元資料進行編 碼’該編碼方法係包含下列步驟·· 步驟(a) 11·輸入一 8位元資料,並配合rst、 int一rd—val[l:〇]、int—rd—η 及 K 字元信號(k—char signal)等信號; 8 1271958 碼或 …元信號值為信號進行判斷’ ·、、,則該8位元資料為特殊控 制碼’該K字元信號值為〇,則該8位元 資料碼; 寸馬The data and the least significant bit are octets, respectively, which are wheeled into the 4-pulse-amplitude amplitude modulation symmetric coding device, and coded and obtained a 10-bit data, and input to the transmission 2 Device 2. The transmitting device 2 includes a modulation device with a heart pulse amplitude modulation = modulated into a plurality of sets of differential 4_pulse amplitude modulation signals. The differential 4-pulse amplitude modulation signal has a 1 〇 group and is transmitted to the receiving device 4 via the transmission interface 3. The receiving device 4 includes a 4-pulse amplitude modulation demodulation device, and the differential 4-pulse amplitude modulation signal is demodulated into a 2-bit data and input to the timing recovery device 5, After the bit data is converted by the data, the 20-bit data is divided into 1 bit data and 10-bit data is input to the 4-pulse amplitude modulation symmetric decoding device 6a, 6b for decoding, and each 8-bit element is obtained. Negative material 'combined into 16-bit data output. The eye is shown in the "Fig. 2", which is a flow chart of the coding method of the present invention. As shown in the figure: input an 8-bit data for encoding 'This encoding method includes the following steps · Step (a) 11 · Enter an 8-bit data, and cooperate with rst, int-rd-val[l:〇] , int-rd-η and K-char signal (k-char signal) and other signals; 8 1271958 code or ... meta-signal value for signal judgment ' ·,,, then the 8-bit data is a special control code 'K The character signal value is 〇, then the 8-bit data code;
編碼所產生之差值量; ㈣⑷13:若騎特殊控制碼,該8位元資 料進行編碼「該8位元資料及一初始差值量經由 一 K字元查表規則^signal)進行 編碼,其輸出為-1G位元資料及—8位元資料The amount of difference generated by the encoding; (4) (4) 13: If a special control code is used, the 8-bit data is encoded, "the 8-bit data and an initial difference amount are encoded via a K-character lookup rule ^signal", Output is -1G bit data and -8 bit data
步驟⑷14a :若為該資料碼,該8位元資料 分成- 5位元資料及一 3位元資料,分別進行編 碼’·該5位元資料及一初始差值量經由一 abcdei—l00k_up查表規則進行編碼,其輸出為一 6位元資料及一 5位元資料編碼所產生之差值 S,其中,該5位元資料編碼所產生之差值量係 作為該3位元資料編碼之差值量之參考; 步驟(e) 14b :該3位元資料及上述該5位元 資料編碼所產生之差值量,經由一 fghj_1〇〇k_up 9 1271958 查表規則進行編碼,其輸出為—4位元資料及一 3位元資料編碼所產生之差值量。該3位元資料 編碼所產生之差值里係為該8位元資料編碼所產 生之差值量; 步驟(f)15:編碼後經最後整合單元輸出該ι〇 位元資料及該8位元資料編碼所產生之差值量。 其中該8位元資料編碼所產生之差值量係可回授 給下組資料編碼之差值量之參考。(如第2圖所 示,該差值量係由連接符號16連接,該連接符 號16係代表該輸出之差值量可回授至下一組解 碼差值量) 該最後整合單元之資料輸出係由K字元信 號來判斷。若該K字元信號值為丨,則該輸出係 為步驟(c)13之輸出;若該K字元信號值為〇,該 輸出係為步驟(d)14a及步驟(e)i4b之輸出。該差 值量輸出’其初始差值量預設為〇〇(_〗),若該 int—rd—n信號值為〇,則輸入int—rcj—vai信號值終 改内部之差值量,反之則輸出步驟(c)13或步驟 (d)14a、步驟(e)i4b編碼所產生之差值量。 1271958 上述步驟(b)12’該4_脈衝振幅調變的信號串 列傳輸系統係具有256組編碼與該資料蹲定義相 對應、12組編碼與該特殊控制碼定義相對應,該 編碼係為實體層與資料連接層的溝通信號。Step (4) 14a: If the data code is the data code, the 8-bit data is divided into -5 bit data and a 3-bit data, respectively, and the code is respectively encoded. 'The 5-bit data and an initial difference amount are checked by an abcdei-l00k_up table. The rule is encoded, and the output is a difference S generated by a 6-bit data and a 5-bit data encoding, wherein the difference generated by the 5-bit data encoding is used as the difference between the 3-bit data encoding Reference to the value; Step (e) 14b: The difference between the 3-bit data and the 5-bit data encoding is encoded by a fghj_1〇〇k_up 9 1271958 table lookup rule, and the output is -4 The amount of difference between the bit data and a 3-bit data encoding. The difference generated by the 3-bit data encoding is the difference amount generated by the 8-bit data encoding; Step (f) 15: After encoding, the ι-bit data and the 8-bit are output by the final integration unit. The amount of difference produced by the metadata encoding. The difference amount generated by the 8-bit data encoding is a reference to the difference amount of the data encoding of the next group. (As shown in Fig. 2, the difference is connected by a connection symbol 16 which represents that the difference amount of the output can be fed back to the next set of decoding difference amounts) The data output of the last integrated unit It is judged by the K character signal. If the K-character signal value is 丨, the output is the output of step (c) 13; if the K-character signal value is 〇, the output is the output of step (d) 14a and step (e) i4b . The difference quantity output 'the initial difference quantity is preset to 〇〇(_〗), and if the int_rd_n signal value is 〇, the input int_rcj_vai signal value is changed internally to the difference amount, Otherwise, the difference amount generated by the encoding of the step (c) 13 or the step (d) 14a and the step (e) i4b is output. 1271958 The above step (b) 12' The 4_pulse amplitude modulation signal serial transmission system has 256 groups of codes corresponding to the data 蹲 definition, and 12 groups of codes corresponding to the special control code definition, the coding system is The communication signal between the physical layer and the data connection layer.
工砥y ^(〇U14a與步驟(e)14b,输入該8伯 π資料編碼成10位元資料,輸出之10位元資料 係為步驟⑷14a輸出之6位元資料與步驟⑷i4t 輸出之4位元資料所組合而成。將6位元資料與 該4位疋貝料係為二組輸出單元,而該每組輸出 單元内所含的位元!與位元〇之數目差可為〇、±2 和⑷如+2係表示在該輸出單元組中,該位元】 比該位元0的數目多2。該輸出單位中位元i與 位元0之數目[係可定義差值量。該輸出單元 内所含的位元1與位元0之數目差係'可為〇、±2 該輸出單元係會補償之前所傳輸之位元所 來位& 1與位元G之個數差或維持原本的 值。該輸出單元補償前面傳輸的位元!與位元 〇之數目差’該差值量係會落在±1和±3,作為 :出單元組與另-輸出單元組的位元1和位元; 平衡之指標。 兀〇 1271958 、〇月參閱『第3圖』所示,係為本發明解石馬方 法机程圖。如圖所示:輸人-資料進行解媽,該 解碼方法係包含下列步驟: 步驟(A)61 :輸入一 1〇位元資料,並配合Work 砥 y ^ (〇 U14a and step (e) 14b, input the 8 π π data into 10-bit data, the output octet data is the 6-bit data output in step (4) 14a and the 4-bit output in step (4) i4t The metadata is combined. The 6-bit data and the 4-bit mussels are two sets of output units, and the difference between the number of bits! and the number of bits contained in each set of output units can be ±2 and (4) as +2 means that in the output unit group, the bit is more than the number of the bit 0. The number of bits i and the number of bits 0 in the output unit [Definable difference amount The difference between the number of bit 1 and bit 0 contained in the output unit is '〇, ±2. The output unit compensates for the bit & 1 and bit G of the previously transmitted bit. The difference or the original value is maintained. The output unit compensates for the difference between the previously transmitted bit! and the number of bits ' 'The difference will fall between ±1 and ±3 as: out unit and other-output unit The bit 1 and the bit of the group; the index of balance. 兀〇1271958, 〇月, see "Fig. 3", which is the machine diagram of the method of solving the stone horse in the present invention. Shows: input - Profile de mother, based decoding method comprising the following steps: Step (A) 61: inputting a 1〇 bit data, and with
⑻lnt~rd-Val[1 :〇]及int-r<Ln等信號,且同時 進行一資料解碼路徑及一錯誤摘測與特殊控制 碼辨別路徑; 芡驟(B)62a:進行該資料解碼路徑時,該夏 位元資料分為- 6位元資料及- 4位元資料,、 行解碼,$ 6位元資料經由一 EDCBA—^ 查表規則進行解碼,其輸出為—5位元資料及_ 6位元資料解碼所產生之差值量,該6位元資半(8) lnt~rd-Val[1:〇] and int-r<Ln and other signals, and simultaneously perform a data decoding path and a fault extraction and special control code discrimination path; Step (B) 62a: Perform the data decoding path At the time, the summer bit data is divided into - 6 bit data and - 4 bit data, and the line decoding, the $6 bit data is decoded by an EDCBA-^ table lookup rule, and the output is -5 bit data and _ 6-bit data decoding to produce the difference, the 6-bit half
解碼所產生之差值量係為下一組解碼之差值邊 之參考。 步驟(C)62b :言亥4位元資料及上述該解碼所 產生之差值量經一 HGFj〇〇k—up查表規則進行 解碼’其輸出為-3位元資料及—4位元資料解 碼所產生之差值量。該4位元資料解碼所產生之 差值量係為10位元資料解碼所產生之差值量。 12 1271958 ^ joj 是否有錯誤;係經由—any一⑽rJ〇〇kup杳表規 則比對該資料及該差值量,是否合乎該傳輸碼之 原則。當發現錯誤發生時,係發出一錯誤信號 該錯誤信號值係為1;當無錯物發 生,該錯誤信號係為〇。 ^驟阳631) ·進行特殊控制碼辨別路徑時, 判斷該資料是否為該特殊控制喝;係經由一 k~charJ〇gic查表規則判斷是否為該特殊控制 碼,當該資料為特輸控制碼時,係發出一 K字元 信號,則該K字元作號枯炎,. β ,值為1 ,备該資料為資料 碼,則該Κ字元信號值為〇 步驟(聯上述步驟完成後經最後整合單元 仔到一 8位元資料、一 1〇位元資料解碼所產生 之差值量、-錯誤信號及一"元信號。該1〇 位元資料解碼所產生 解碼差值量之參考(如第之=回授給下組資料 、查姑〜 %如第3圖所示’該差值量接由 連接付唬65連接,該遠接 之該連接付號65係代表該輸出 … 授至下一組解媽差值量)。該Γ0位 Μ料解碼所產生之差值量輸出,其初始差值量 1271958 預"又為〇〇(ββ1),若該int—rd—n信號值為〇,則輸 入int 一 rd-val信號值修改内部之差值量,反ι則 輸出步驟(B)62a與步驟(C)62b編碼所產生之差 值量。 5月參閱『第4圖』所示,係為本發明一單位 差值量·及位元間隔之關係曲線圖。如圖所示··該 差值量為平衡資料傳輸之位元1與位元〇之指 杯’並可定義出一單位差值量及位元間隔之關係 曲線。當所傳送之位元為位元1時,關係曲線則 上升45度,並與起始點相差一數位總合變化量, 所累積的差值量為起始點的差值量加一。當傳送 之位元為位元〇時,關係曲線則下降45度,並 與起始點相差一數位總合變化量,所累積的差值 量為起始點的差值量減一。該單元垂直數位總和 變化量7最大範圍為2。 w參閱『第5圖』所示,係為本發明整體差 值量與位元傳送之關係曲線圖。如圖所示:該一 單位差值量及位元間隔之關係曲線係可發展為 整體差值量與位元傳送之關係曲線,分別由6位 几輸出單元與4位元輸出單元之差值量及位元間 14 1271958 隔之關係曲線所組成。在6位元輸出單元與4位 元輪出單元之邊界上,其垂直之數位總合變化量 之取大範圍為6,該差值量為±1及土3。該每一位 一係八有固定編碼及位元順序81。每一 1 〇位 元輸出資料中,係於位元3與位元2之間固定會 有一組對稱式資料轉換邊界83。在位元傳輸上每 傳輸8個位元,至少會傳送—組位元1與位元〇The amount of difference produced by the decoding is a reference to the difference side of the next set of decodings. Step (C) 62b: The 4-bit data of Yanhai and the difference amount generated by the decoding are decoded by a HGFj〇〇k-up table check rule, and the output is -3 bit data and -4 bit data. Decode the amount of difference produced. The difference generated by the decoding of the 4-bit data is the difference generated by the decoding of the 10-bit data. 12 1271958 ^ joj Whether there is an error; whether it is in accordance with the principle of the transmission code by the -any one (10) rJ〇〇kup table rule. When an error is found, an error signal is issued. The error signal value is 1; when no error occurs, the error signal is 〇. ^Jiyang 631) ·When the special control code is used to identify the path, it is judged whether the data is the special control drink; whether it is the special control code through a k~charJ〇gic table check rule, when the data is special control When the code is issued, a K-character signal is sent, then the K-character is numbered, and β is a value of 1. If the data is a data code, the value of the Κ character signal is 〇 step (completed in the above steps) After the final integration unit, the difference amount generated by the decoding of an 8-bit data and a 1-bit data, an error signal, and a "meta signal. The decoding difference generated by the decoding of the 1-bit data The reference (such as the first = feedback to the next group of data, check the abundance ~ % as shown in Figure 3) the difference is connected by the connection 唬 65, the connection of the connection of the number 65 represents the output ... grants the next set of difference values for the mother.) The output of the difference between the 0 bits of the data is decoded. The initial difference is 1271958. The pre-quot; is 〇〇(ββ1), if the int_rd— If the value of the n signal is 〇, input the int- rd-val signal value to modify the internal difference, and then output the step (B) 62a and Step (C) 62b encodes the difference amount generated by the code. See the "Fig. 4" in May, which is a graph of the relationship between the unit difference amount and the bit interval of the present invention. The difference is the relationship between the bit 1 of the balanced data transmission and the finger cup of the bit ' and can define a unit difference and the bit interval. When the transmitted bit is bit 1, the relationship curve Then it rises by 45 degrees and differs from the starting point by a total number of changes, and the accumulated difference is the difference of the starting point plus one. When the transmitted bit is the bit 〇, the relationship curve decreases. 45 degrees, and a difference of the total number of changes from the starting point, the accumulated difference is the difference of the starting point minus one. The maximum number of vertical digits of the unit is 7 and the maximum range is 2. Figure 5 shows the relationship between the overall difference and the bit transfer of the present invention. As shown in the figure, the relationship between the unit difference and the bit interval can be developed as the overall difference and The relationship curve of bit transfer is the difference and bit of 6-bit output unit and 4-bit output unit respectively 14 1271958 is composed of a relationship curve. At the boundary between the 6-bit output unit and the 4-bit round-out unit, the vertical digital sum total variation is a large range of 6, and the difference is ±1 and soil. 3. Each bit has a fixed code and bit order 81. In each of the 1 bit output data, a set of symmetric data conversion boundaries 83 is fixed between bit 3 and bit 2. For every 8 bits transmitted on a bit transfer, at least the transfer of the bit 1 and the bit 〇
之轉換邊界,其連串長度(_ length) 82係為8。 該對稱式資料轉換邊界83可以提供接收裝置作 時序回復之時序資訊,係提供足夠的時序資訊, 每傳輸8位70資料至少為有-資料轉換給接收端 、夺序、回復。其中,該垂直數位總和變化量範圍 : 並表示整體位元傳輸係是收斂於固定範圍 ^垂直數位總和變化量,所㈣傳輸碼係可藉由 平衡位it傳輸之位元i與位元Q之數目,達到直 流平衡傳輸碼之特性。 μ參閱『第6圖』所示,係為本發明差動4_ 脈衝振幅調變信號傳輸之三種資料轉換邊界型 態圖。如圖所示··係包含型態- 93、型態二94 及H 一 95二種資料轉換邊界型態。一曲線係 15 1271958 為一差動4-脈衝振幅調變信號傳輸曲線91,另一 線係為一相對應之差動4 _脈衝振幅調變信號 傳輸曲、線92。請參閱『第7圖』所示,係為:: 明考慮型態一資料與型態二資料轉換之比較 圖,如圖所示:係包含型態一 93及型態二%之 資料轉換邊界100型態,其中包含一差動4_脈衝 鲁 振幅調變信號傳輸曲線91及一相對應之差動4_ 脈衝振幅調變信號傳輸曲線92 ^該型態一 93係 具有一對稱式資料轉換邊界1〇〇,該對稱式資料 轉換邊界100係由該差動4-脈衝振幅調變信號傳 輸曲線91與資料轉換邊界1〇〇交集於資料轉換 時間101之中點所形成,並根據該資料轉換邊界 100以提供正確的時序回復之參考資訊。該差動 # 扣脈衝振幅調變的信號串列傳輸系統係利用4_脈 衝振幅調變對稱式傳輸碼之編碼規則,係每傳輸 10個信號保證至少存在一組對稱式資料轉換邊 界1 〇〇。若在接收端做時序回復時,係考慮該對 稱式資料轉換邊界100所提供之時序資訊,並於 時序回復時能夠有效的改善參考之時序資訊轉 換邊界抖動達±25%資料轉換碑間1〇2,亦可改盖 1271958 所回復之時脈轉換邊界抖動。 。月參閱『第8及第9圖』所示,係為本發明 傳輸馬所k供之對稱式轉換邊界圖及本發明傳 輸碼所提供之時序同步資訊圖。如圖所示:係包 含一組最高有效位元lu及一組最低有效位元 1 (如第8圖所示)。係一 8位元資料編碼成一 位元121資料,每10位元121資料中,位元 3與位70 2係具有固定編碼,該固定編碼係為(1,〇) 或(〇,1)。經過調變成差動4_脈衝振幅調變信號 後,在傳送的10個符號中可得符號3與符號2 之對稱式資料轉換型態,保證每傳送10個符號 至少存在一對稱式資料轉換邊界。固定每傳送 位元121會存在一組(丨,0)或(〇,1)的資料轉換,且 固定發生於每10位元121係為一個週期(如第9 圖所示)。§亥固定編碼位元位置係有一固定的編 碼規則,並表示其存在一固定的同步時序資訊提 供接收端快速達到同步。請參閱『第1〇及第u 圖』所示,係為本發明差動4_脈衝振幅調變作號 隨機資料轉換邊界圖及本發明差_ 4_脈衝振= 調變信號只考慮對稱式資料轉換邊界 耶圖所 17 1271958 示··係利用-4 _脈衝振幅調㈣統電路模擬該差 動4-脈衝振幅調變信號隨機資料轉換邊界及該 4-脈衝振幅調變信號只考慮對稱式資料轉換邊界 圖。 綜上所述,本發明用於串列傳輸之傳輸裝置 可有效改善習用之種種缺點,可使用於該差動心 # 脈衝振幅調變的信號串列傳輸系統,達到有效降 低時脈回復時所產生的資料轉換邊界抖動,並提 供接收端快速作時序同步,且保持傳統The transition boundary has a series length (_length) 82 of 8. The symmetric data conversion boundary 83 can provide timing information of the receiving device for timing recovery, and provides sufficient timing information, and each transmission of 8 bits of 70 data is at least - data conversion to the receiving end, reordering, and replying. Wherein, the vertical digit sum variation range: and indicates that the overall bit transmission system converges to a fixed range ^ vertical digit sum variation, and (4) the transmission code can be transmitted by the balance bit it, the bit i and the bit Q The number reaches the characteristics of the DC balanced transmission code. μ See “Figure 6” for the three data conversion boundary diagrams of the differential 4_pulse amplitude modulation signal transmission of the present invention. As shown in the figure, the system contains type-93, type II 94 and H-95 data conversion boundary types. A curve system 15 1271958 is a differential 4-pulse amplitude modulation signal transmission curve 91, and the other line is a corresponding differential 4 _ pulse amplitude modulation signal transmission curve, line 92. Please refer to Figure 7 for the following: The comparison chart of the type 1 data and the type 2 data conversion is as shown in the figure: the data conversion boundary containing the pattern type 93 and the type 2% The 100 type state includes a differential 4_pulse Lu amplitude modulation signal transmission curve 91 and a corresponding differential 4_pulse amplitude modulation signal transmission curve 92. The type 93 has a symmetric data conversion boundary. 1〇〇, the symmetric data conversion boundary 100 is formed by the differential 4-pulse amplitude modulation signal transmission curve 91 and the data conversion boundary 1〇〇 intersecting at a point in the data conversion time 101, and converted according to the data. Boundary 100 provides reference information for correct timing recovery. The signal serial transmission system of the differential pulse modulation is a coding rule using a 4_pulse amplitude modulation symmetric transmission code, and at least 10 sets of symmetric data conversion boundaries are guaranteed for each transmission of 10 signals. . If timing feedback is performed at the receiving end, the timing information provided by the symmetric data conversion boundary 100 is considered, and the timing information of the reference can be effectively improved when the timing is restored. The boundary jitter is ±25%. 2, can also change the clock transition boundary jitter returned by 1271958. . See the "8th and 9th drawings" for the month, which is the timing conversion information map provided by the transmission horse of the present invention and the timing synchronization information provided by the transmission code of the present invention. As shown in the figure: the system contains a set of most significant bits lu and a set of least significant bits 1 (as shown in Figure 8). One 8-bit data is encoded into one-bit 121 data. For each 10-bit 121 data, bit 3 and bit 70 2 have a fixed code, and the fixed code is (1, 〇) or (〇, 1). After being modulated into a differential 4_pulse amplitude modulation signal, a symmetric data conversion pattern of symbol 3 and symbol 2 can be obtained among the transmitted 10 symbols, ensuring that at least one symmetric data conversion boundary exists for every 10 symbols transmitted. . There is a set of (丨, 0) or (〇, 1) data conversions for each transfer bit 121 fixed, and the fixed occurrence occurs every 10 bits of 121 for one cycle (as shown in Fig. 9). § Hai fixed coded bit position has a fixed coding rule, and indicates that there is a fixed synchronization timing information to provide fast synchronization of the receiving end. Please refer to the "1st and uth diagrams" for the differential 4_pulse amplitude modulation of the present invention. The boundary map of the random data conversion and the difference of the present invention _ 4_pulse vibration = modulation signal only consider the symmetry Data conversion boundary Yates 17 17271958 shows the use of -4 _ pulse amplitude modulation (four) system simulation of the differential 4-pulse amplitude modulation signal random data conversion boundary and the 4-pulse amplitude modulation signal only consider symmetry Data conversion boundary map. In summary, the transmission device for serial transmission of the present invention can effectively improve various disadvantages of the conventional use, and can be used for the signal serial transmission system for the differential amplitude modulation of the differential heart to achieve effective reduction of clock recovery. The resulting data is converted to boundary jitter and provides fast timing synchronization at the receiving end, while maintaining the tradition
8B/10B 傳輸碼之傳輸優點,進而使本創作之產生能更進 步、更實用、更符合使用者之所須,確已符合創 作專利申請之要件,爰依法提出專利申請。 _ 淮以上所述者’僅為本創作之較隹實施例而 已田不能以此限定本創作實施之範圍,·故,凡 依本創作申請專利範圍及創作說明書内容所作 之簡單的等效變化與修飾,皆應仍屬本創作專利 涵蓋之範圍内。 1271958 【圖式簡單說明】 第1圖,係本發明4-脈衝振幅調變傳輸系統架構 示意圖。 第2圖,係本發明編碼方法流程圖。 第3圖’係本發明解碼方法流程圖。 第4圖,係本發明一單位差值量及位元間隔之關 係曲線圖。 第5圖,係為本發明整體差值量與位元傳送之關 係曲線圖。 第6圖,係本發明差動4_脈衝振幅調變信號傳輸 之二種資料轉換邊界型態示意圖。 第7圖,係本發明考慮型態一資料與型態二資料 轉換之比較圖。 第8圖,係本發明傳輸碼所提供之對稱式轉換邊 界圖。 第9圖,係本發明傳輸碼提供之時序同步資訊圖。 第10圖,係本發明差動4_脈衝振幅調變信號隨機 資料轉換邊界圖。 第11圖,係本發明差動4-脈衝振幅調變信號只考 慮對稱式資料轉換邊界圓。 1271958 【主要元件符號說明】 4-脈衝振幅調變對稱式編碼裝置la、lb 步驟(a) 11 步驟(b)12 步驟(c)13 步驟(d)14a 步驟(e)14b Φ 步驟(f)15 連接符號16 傳送裝置2 傳輸介面3 、 接收裝置4 時序回復裝置5 φ 4-脈衝振幅調變對稱式解碼裝置6a、6b 步驟(A)61 步驟(B)62a 步驟(C)62b 步驟(D)63a 步驟(E)63b 步驟(F)64 20 1271958 連接符號65 單元垂直數位總和變化量7 … 位元順序81 連串長度82 對稱式資料轉換邊界83 差動4-脈衝振幅調變信號傳輸曲線91 相對應之差動4_脈衝振幅調變信號傳輸曲線92 型態一 93 型態二94 型態三95 資料轉換邊界1〇〇 資料轉換時間101 25%資料轉換時間102 • 最高有效位元111 最低有效位元112 10位元121 21The transmission advantages of the 8B/10B transmission code, in turn, make the creation of this creation more progressive, more practical, and more in line with the needs of the user. It has indeed met the requirements for the creation of a patent application, and has filed a patent application according to law. _ Huai above is only a comparative example of this creation, and Tian Tian cannot limit the scope of this creation. Therefore, the simple equivalent changes made by the scope of the patent application and the content of the creation manual are Modifications shall remain within the scope of this Creative Patent. 1271958 [Simplified description of the drawings] Fig. 1 is a schematic diagram showing the architecture of a 4-pulse amplitude modulation transmission system of the present invention. Figure 2 is a flow chart of the encoding method of the present invention. Figure 3 is a flow chart of the decoding method of the present invention. Fig. 4 is a graph showing the relationship between a unit difference amount and a bit interval of the present invention. Fig. 5 is a graph showing the relationship between the overall difference amount and the bit transfer of the present invention. Fig. 6 is a schematic diagram showing two types of data conversion boundary states of differential 4_pulse amplitude modulation signal transmission of the present invention. Fig. 7 is a comparison diagram of the data of the type 1 and the type 2 data of the present invention. Figure 8 is a symmetrical conversion boundary diagram provided by the transmission code of the present invention. Figure 9 is a timing synchronization information diagram provided by the transmission code of the present invention. Figure 10 is a diagram showing the random data conversion boundary of the differential 4_pulse amplitude modulation signal of the present invention. In Fig. 11, the differential 4-pulse amplitude modulation signal of the present invention only considers the symmetric data conversion boundary circle. 1271958 [Description of main component symbols] 4-pulse amplitude modulation symmetrical coding device la, lb Step (a) 11 Step (b) 12 Step (c) 13 Step (d) 14a Step (e) 14b Φ Step (f) 15 Connection symbol 16 Transmission device 2 Transmission interface 3, receiving device 4 Timing recovery device 5 φ 4-pulse amplitude modulation symmetric decoding device 6a, 6b Step (A) 61 Step (B) 62a Step (C) 62b Step (D ) 63a Step (E) 63b Step (F) 64 20 1271958 Connection symbol 65 Unit vertical digit sum change amount 7 ... Bit order 81 Serial length 82 Symmetric data conversion boundary 83 Differential 4-pulse amplitude modulation signal transmission curve 91 corresponding differential 4_ pulse amplitude modulation signal transmission curve 92 type one 93 type two 94 type three 95 data conversion boundary 1 data conversion time 101 25% data conversion time 102 • most significant bit 111 Least significant bit 112 10 bits 121 21
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