CN111756382B

CN111756382B - C54 x-based RLHDB3 decoding method, device and storage medium

Info

Publication number: CN111756382B
Application number: CN202010661060.3A
Authority: CN
Inventors: 刘剑丽; 陈金鹰; 蔡方凯; 曹俊兴; 张勇; 张敏; 赵耀; 吴睿; 汪杰
Original assignee: Chengdu Technological University CDTU; Chengdu Univeristy of Technology
Current assignee: Chengdu Technological University CDTU; Chengdu Univeristy of Technology
Priority date: 2020-07-10
Filing date: 2020-07-10
Publication date: 2021-10-08
Anticipated expiration: 2040-07-10
Also published as: CN111756382A

Abstract

The invention discloses a decoding method, a device and a storage medium of RLHBD3 based on C54x, which are characterized in that an input and level conversion module is firstly utilized to convert an input RLHDB 3code into an HDB 3code, then a design scheme of HDB3 decoding is realized by utilizing a C54x series DSP chip through software programming, and the number of received continuous 0 is judged by setting two received continuous 0 and three received continuous 0 marks, so that the output processing of 0 and +/-1 in 000V +/-and B +/-00V +/-and +/-1 codes is determined. The method has the advantages of fast decoding, adaptability to decoding requirements of different transmission rates, relatively low cost and flexible application, when the technical requirements or indexes are required to be adjusted, a hardware circuit is not required to be modified, only a new program is required to be downloaded to a memory, the requirements of data transmission and illumination can be met even when 0 code is continuously transmitted, and the method has good application value.

Description

C54 x-based RLHDB3 decoding method, device and storage medium

Technical Field

The invention belongs to the technical field of RLHDB3 coding and decoding, and particularly relates to a C54 x-based RLHDB3 decoding method, a device and a storage medium.

Background

RLHDB3 code: rise Level High sensitivity Bipolar of Order 3code, rising Level three-Order High Density Bipolar code. The RLHDB 3code is an improved level-rising unipolar non-return-to-zero code on the basis of an AIM (alternating Mark Inversion, Alternative Mark Inversion code), overcomes the problem that timing extraction is difficult due to excessive AMI codes and excessive 0, and overcomes the problem that an LED lamp cannot be lighted for illumination due to the negative level of the HDB 3code, so that the LED lamp always has forward current to pass through, and the requirements of data transmission and illumination can be met.

The ITU-T puts out HDB 3code as a coding mode of a digital interface in G.703 suggestion, and in order to realize the decoding of HDB 3code, a special AMI/HDB3 coder chip such as CD22103 can be adopted for design; the design of an HDB3 coder/decoder can also be carried out by utilizing a CPLD/FPGA; and the single chip microcomputer can be used for designing the HDB3 coder/decoder. The three decoding modes have respective advantages and disadvantages, the invention provides a design scheme for decoding by adopting a DSP chip STM320C54x of TI company, and corresponding decoding can be carried out according to different transmission code speeds only by downloading decoding software in the chip.

Disclosure of Invention

Aiming at the defects in the prior art, the RLHDB3 decoding method, the RLHDB3 decoding device and the storage medium based on the C54x solve the problems that the existing decoding method needs to depend on a hardware circuit and is difficult to adapt to different transmission code rates, and solve the problem that the data can be transmitted and the illumination needs to be solved even when 0 code is continuously transmitted.

In order to achieve the purpose of the invention, the technical scheme adopted by the invention is an RLHDB3 decoding method based on C54x, which comprises the following steps:

s1, receiving the RLHDB3 coded signal sent by the LED through the signal receiving module, and inputting the signal to the level conversion module;

s2, removing the direct current signal in the RLHDB3 coded signal through a level conversion module, and outputting the obtained HDB 3code to a DSP chip of a C54x series;

s3, decoding the HDB 3code through the DSP chip of the C54x series, and further realizing the decoding of the RLHDB3 code.

Further, in step S1, the signal receiving module includes a photo-receiving tube and a ground resistor connected to a negative electrode of the photo-receiving tube, and the negative electrode of the photo-receiving tube is connected to the level conversion module as an output end of the signal receiving module;

the step S1 specifically includes:

the photoelectric receiving tube receives the RLHDB3 coded signal sent by the LED, the photoelectric receiving tube D is conducted along with the change of the RLHDB3 coded signal, a level signal of the RLHDB3 coded signal change process is obtained through the grounding resistor R, and the level signal is input to the level conversion module.

Further, the step S3 is specifically:

in a DSP chip of a C54x series, the number of continuous 0 codes in the HDB 3code is determined by setting continuous 0 identifiers, and the HDB3 is decoded by determining the decoding output of 000V +/-code group, B +/-00V +/-code group, +/-1 code and 0 and +/-1 in the 0 code in the HDB 3code according to the number of the continuous 0 codes, thereby realizing the decoding of RLHDB3 code.

Further, the set consecutive 0 identifiers include f20 and f 30;

when f20 is 1, the currently received HDB 3code is a B ± 00V ± code group;

when f30 is 1, it indicates that the received HDB 3code is 000V ± code group.

Further, the method for determining the decoding output of 0 and ± 1 in 000V ± code groups, B ± 00V ± code groups, ± 1 code and 0 code in HDB 3code according to the number of consecutive 0 is specifically as follows:

a1, sequentially detecting each code value of HDB3 codes;

a2, when the number of continuous 0 codes appearing in the current HDB 3code does not exceed 3, decoding each corresponding 0 code and outputting the decoded 0 code;

a3, when the code of +/-1 appears in the current HBD 3code, decoding each code of +/-1 to output as + 1;

a4, when +/-1 code appears in the current HDB 3code and f20 is equal to 1, representing that the current received code is +/-1 code of V +/-in a B +/-00V +/-code group, storing the B +/-00V +/-code group by setting a linear sliding window of 4 units, decoding the received +/-1 code to 0 code, and correspondingly decoding B +/-0, 0 and 0 stored in the first three units in the linear sliding window to 0, 0 and 0;

a5, when ± 1 code appears in the current HDB 3code and f30 is 1, indicating that ± 1 code of V ± in 000V ± code groups is currently received, storing the 000V ± code groups by setting a linear sliding window of 4 units, decoding the received ± 1 code as 0 code, and correspondingly decoding 0, 0 and 0 stored in the first three units in the linear sliding window as 0, 0 and 0;

a6, repeating the steps A2-A5, decoding and outputting each code bit value of the HDB 3code to be decoded, and realizing the decoding of the HDB 3.

A C54 x-based RLHDB3 decoding device, the device comprising:

the signal receiving module is used for receiving the RLHDB3 coded signal sent by the LED and inputting the RLHDB3 coded signal to the level conversion module;

the level conversion module is used for converting the RLHDB3 coded signal received by the signal receiving module into an HDB 3code and inputting the HDB 3code into the signal processing module for decoding the HDB3 code;

and the signal processing module is used for decoding the HDB 3code so as to realize RLHDB3 decoding.

Further, the signal processing module includes:

an input detection unit for detecting that the currently input HDB 3code is 0 or +/-1;

the identification determining unit is used for identifying the HDB 3code when the current input is +/-1 and determining that the HDB 3code is B +/-00V +/-code or 000V +/-code;

the code bit sliding unit is used for performing code bit moving operation when the input detection module detects 0 or +/-1 of the HDB3 code;

the data temporary storage unit is used for temporarily storing the B +/-00V +/-code group or the 000V +/-code group in the currently input HDB3 codes;

and the decoding output unit is used for performing corresponding decoding output according to the data stored in the data temporary storage module and the data input by the input detection module, so as to realize the decoding of the RLHDB 3.

Further, the decoding output unit comprises a 0-code decoding output mechanism and a +/-1-code decoding output mechanism;

the 0 code decoding output mechanism is used for decoding and outputting the 0 codes detected in the input detection unit when the number of the continuous 0 codes does not exceed 3 into the corresponding 0 codes;

the +/-1 code decoding and outputting mechanism is used for decoding and outputting +/-1 codes detected in the input detection unit to be +1, decoding and outputting the B +/-codes and the 0 codes in the B +/-00V +/-code group or the 000V +/-code group of the data temporary storage module unit to be 0, and decoding and outputting the V +/-codes detected as +/-1 in the B +/-00V +/-code group or the 000V +/-codes to be 0.

Further, the signal processing module is a DSP chip of C54x series.

A C54x readable storage medium, the C54x readable storage medium storing a C54x program, wherein the steps of the C54x based RLHDB3 decoding method as claimed in any one of claims 1 to 5 are implemented when the computing program is executed.

The invention has the beneficial effects that:

(1) the invention analyzes the RLHDB3 coding rule, proposes a design scheme that firstly, the input RLHDB 3code is converted into HDB 3code by a circuit conversion circuit, then the HDB3 decoding is realized by software programming by C54x series DSP chips, and the number of the received continuous 0 is judged by setting the received two continuous 0 and three continuous 0 marks, thereby determining the output processing of 0 and +/-1 in 000V +/-B +/-00V +/-and +/-1 codes;

(2) different input codes occupy different decoding instruction periods by adding no-operation instructions, namely problems of jitter, delay and rate of transmission code rate caused by the idle operation instructions;

(3) the design method for realizing RLHDB3 decoding by utilizing DSP chip software programming has the advantages of high decoding speed, adaptability to decoding requirements of different transmission rates, relatively low cost and flexible application, when the technical requirements or indexes need to be adjusted, a hardware circuit does not need to be modified, and only a new program needs to be downloaded into a memory, so that the defects that an LED in the prior art cannot pass through a "-1" code in an HDB 3code, a 2FSK code has a half period to enable an LED lamp to lose an illumination function, and a system loses a synchronous clock to extract signals and the LED lamp loses the illumination function when a baseband code continuously transmits 0 codes are overcome, the illumination function is realized while data is transmitted, and the design method has good application value.

Drawings

Fig. 1 is a flowchart of the RLHDB3 decoding method provided by the present invention.

Fig. 2 is a structural diagram of the RLHDB3 decoding device provided by the invention.

FIG. 3 is a flow chart of the HDB3 decoding method of C54x according to the present invention.

FIG. 4 is a schematic diagram of the DSP chip memory space allocation provided by the present invention.

FIG. 5 is a flow chart of the HDB3 decoding process provided by the present invention.

FIG. 6 is a schematic diagram of an HDB3 decoding simulation output waveform provided by the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.

According to the HDB3 encoding rule determined in the digital communication principle, in order to adapt to the program encoding of the DSP chip, the encoding rule can be described as follows:

(1) when the number of input continuous 0 is not more than 3, 0 in the input code is not processed, the value is directly output while being unchanged, and 1 in the input code is alternately output as-1 and + 1;

(2) if the number of consecutive 0's exceeds 3, every 4 0's are considered as a bar and defined as B00V, B, V may be 0, -1 and + 1;

wherein, the specific conditions of which values of B and V should be satisfied are as follows: v has the same polarity as the adjacent non-0 code; when the V is not seen, the polarity of the 1 code is alternated; v and V alternate in polarity; generally, the first B is taken as 0, and the first non-0 code is taken as-1; since V destroys the polarity alternation rule, B has 3 changes to satisfy the rule, so B is called destruction pulse, B is called regulation pulse, and B00V is called replacement section and destruction section. For example: unipolar return-to-zero code sequence:

1 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1

encoded HDB 3code sequence:

-1 0 0 0 V- +1 0 -1 B+ 0 0 V 0 -1 +1 -1 0 0 0 V- B+ 0 0 V+ 0 -1

in the HDB 3code stream, each code bit may be one of three forms of 0 code and +/-1 code according to the coding rule, the number of the continuous 0 code is at most 3, the continuous 0 code needs to be identified during decoding, and whether 000V +/-code groups and B +/-00V +/-code groups are inserted is judged.

Example 1:

the embodiment of the invention provides a C54 x-based RLHDB3 decoding method which is realized by utilizing a C54x series DSP chip through software programming and corresponds to the coding method, and as shown in FIG. 1, the specific method comprises the following steps:

As shown in fig. 2, the signal receiving module in embodiment 1 includes a photo-receiving tube and a ground resistor connected to a negative electrode of the photo-receiving tube, and the negative electrode of the photo-receiving tube is connected to the level conversion module as an output end of the signal receiving module;

step S1 of this embodiment specifically includes:

the photoelectric receiving tube receives RLHDB3 coded signals sent by the LED, the photoelectric receiving tube D is conducted along with the change of the RLHDB3 coded signals, level signals of the RLHDB3 coded signal change process are obtained through the grounding resistor R and input to the level conversion module

The RLHDB3 coded signal is a level-up HDB 3code, a transmission 2 unit level indicates a transmission '1' symbol, a transmission 1 unit level indicates a transmission '0' symbol, a transmission 0 unit level indicates a transmission '-1' symbol, a level conversion module removes a direct current signal in the received RLHDB3 coded signal, amplifies, shapes and converts the direct current signal into a level, and outputs an HDB 3code, wherein the HDB 3code transmits a1 unit level indicating a transmission '1' symbol, a transmission 0 unit indicating a transmission '0' symbol, and a transmission-1 unit indicating a transmission '-1' symbol; then, the HDB 3code is decoded by a DSP chip of the C54x series, specifically, the step S3 in this embodiment specifically includes:

in a DSP chip of a C54x series, the number of continuous 0 codes in the HDB3 codes is determined by setting continuous 0 identifiers, and the decoding output of 0 and +/-1 in 000V +/-code groups, B +/-00V +/-code groups, +/-1 codes and 0 codes in the HDB3 codes is determined according to the number of the continuous 0 codes, so that the HDB3 decoding is realized;

as shown in fig. 3, the method for determining the decoding output of 0 and ± 1 in 000V ± code groups, B ± 00V ± code groups, ± 1 code and 0 code in HDB 3code according to the number of consecutive 0 is specifically:

a1, acquiring HDB3 codes to be decoded, and sequentially detecting each code value of the HDB3 codes;

decoding 0 codes of the currently received HDB3 codes into:

specifically, only one 0 code in the HDB code appears independently, which indicates that 0 appears in the original code, and the 0 code should be output; if only two continuous 0 s in the HDB 3code represent two continuous 00 s appearing in the original code, the 00 code should be output; if there are three consecutive 0's in the HDB 3code, it represents three consecutive 000's appearing in the original code, and the 000 codes should be output as well. According to the coding rule, the HDB 3code can not have four continuous 0, when more than four continuous 0 codes appear in the original code, the HDB3 coding rule can replace the four continuous 0 codes by inserting 000V +/-code groups and B +/-00V +/-code groups;

the method for decoding +/-1 code in the currently received HDB 3code comprises the following steps:

specifically, when 1 code appears in the original code, the coding output is +/-1 according to the HDB3 coding rule, so when +/-1 code appears, the decoding output is + 1;

when receiving the code group of 000V plus or minus of HDB 3code and the code group of B plus or minus 1 of B plus or minus 00V plus or minus, 0 code should be output when receiving B plus or minus and V plus or minus; specifically, 000V ± code groups, B ± 00V ± code groups are identified by setting consecutive 0 identifiers, the consecutive 0 identifiers including f20 and f30, when f20 is 1, indicating that consecutive two 0 s are currently received, which is B ± 00V ± code groups of HDB3 codes; when f30 is 1, it indicates that three consecutive 0 s are currently received, and the received is 000V ± code groups in the HDB3 codes; therefore, the decoding method for 000V + -code group and B + -00V + -code group is as follows:

a5, when ± 1 code appears in the current HDB 3code and f30 is 1, indicating that ± 1 code of V ± in 000V ± code groups is currently received, storing the 000V ± code groups by setting a linear sliding window of 4 units, decoding the received ± 1 code as 0 code, and correspondingly decoding 0, 0 and 0 stored in the first three units in the linear sliding window as 0, 0 and 0.

Wherein the linear sliding window is implemented by copying the low address unit data to the next high address unit by the DELAY instruction when programming to implement the decode operation. In order to continuously receive HDB2 code data, when the processing for 000V ± code groups and B ± 00V ± code groups is not performed once, f20 and f30 should be reset to 0 in preparation for receiving the following data.

In the embodiment of the present invention, according to the above decoding rule, the HDB3 code: when decoding is carried out at-1000V-0 +1B-00V-0+10-100, the decoding method comprises the following steps: the-1 decoded output is 1, 000V-code group decoded output is 0000, the +1 decoded output is 1, B-00V-code group decoded output is 0000, the +10-100 decoded output is 10100, resulting in a complete decoded output of 1000010000010100.

Example 2:

an embodiment of the present invention provides an HDB3 decoding apparatus based on C54x, as shown in fig. 2, including:

The signal receiving module in the embodiment comprises a photoelectric receiving tube and a grounding resistor connected with the negative electrode of the photoelectric receiving tube, wherein the negative electrode of the photoelectric receiving tube is used as the output end of the signal receiving module and is connected with the level conversion module; when RLHDB3 lighting and coding signals sent by an external LED lamp are received by a photoelectric receiving tube D of a receiving module, the photoelectric receiving tube D is conducted along with the change of RLHDB3 signals, RLHDB3 coding signal level is obtained on a resistor R, the signals are amplified, shaped and level-converted by an input and level conversion module, then HDB3 codes are output, and then decoding is carried out by a DSP chip of a C54x series.

The signal processing module in this embodiment is a C54x series DSP chip, the RAM in the chip completes temporary storage of relevant data in the HDB decoding process, and the ROM stores a decoding program for decoding by the DSP, and the C54x series DSP chip specifically includes the following functional units:

The decoding output module in the embodiment of the invention comprises a 0-code decoding output mechanism and a +/-1-code decoding output mechanism;

the 0 code decoding output mechanism is used for decoding and outputting 0 codes detected in the input detection unit when the number of the continuous 0 codes does not exceed 3 into corresponding 0 codes; the +/-1 code decoding and outputting mechanism is used for decoding and outputting the +/-1 code detected in the input detection unit to be +1, decoding and outputting the B +/-code and the 0 code in the B +/-00V +/-code group or the 000V +/-code group of the data temporary storage module unit to be 0, and decoding and outputting the V +/-code detected as +/-1 in the B +/-00V +/-code group or the 000V +/-code to be 0.

Example 3:

the embodiment of the invention provides a C54x readable storage medium, wherein the C54x readable storage medium stores a C54x program, and is characterized in that the steps of the RLHDB3 decoding method based on the C54x are realized when the calculation program is executed.

Example 4:

the embodiment of the invention provides a programming flow for executing the HDB3 decoding:

(1) initialization setting:

the allocation of the data memory allocation space in the DSP chip is shown in fig. 4, where (a) is the pre-allocation of the data memory, and (b) is the actual occupation of the data memory after the program is run. The initialization setting is mainly to complete the setting of the page pointer DP equal to 0, the consecutive 0 identifiers include initial values of f20 equal to 0, f30 equal to 0, and two kinds of 0 and +1 in the decoded output of HDB3 may be stored in two units of 64 (named tpv10) and 65 (named tpv11) respectively for calling in outputting. Then, the auxiliary register AR7 stores a count initial value 2 of 2 consecutive 0 detection inputs.

(1) Processing of three states in HDB3 code:

the program implementation flow of the decoding process of the HDB 3code is shown in FIG. 5:

1) inputting new data:

the data to be decoded is input from the input port PA1 to the new _ hdb3 by the instruction PORTR, and the input data is loaded to the accumulator a. Thereafter, it is judged whether or not the input is 0, and the processing is switched to the processing of branch number hdb30 to perform the processing of 0 or the processing of 1 at branch number hdb31, respectively;

2) processing of input 0:

if the HDB 3code input is 0, in the process of branch pair 0 of index HDB3, subtract 1 from AR7, and then determine whether AR7 is 0. If AR7 is not 0, it is determined whether f20 is 0, and if f20 is 0 at this time, it indicates that two consecutive 0 s have not been received, and the process of outputting 0 is branched to out 0. If AR7 is not 0, f20 is 1, indicating that three consecutive 0 s have been received, and f30 is set to 1, and then it branches to out0 to execute the processing with an output of 0. If AR7-1 is 0, indicating that two consecutive 0 s have been received, go to branch zro3 to perform the setting f20 equal to 1, and then go out0 to perform the processing with the output 0.

3) Processing of input ± 1:

if the input HDB 3code is +1 or-1 code, not 0, then in the processing of code + -1 by branch labeled HDB31, it is determined whether f20 is 0. If f20 is equal to 0, it means that the ± 1 code is 1 code in the original code, go to out1 to branch and output as 1 code, and reset flag signal f20 is equal to 0, f30 is equal to 0, AR7 is equal to 2, then go to sliding window via slide to perform shift processing. If f20 is equal to 1, indicating that two-way 0 has been received, the flow branches to df30, and then it is determined whether f30 is 0. If 0, the code is the code of + -1 of the code group of B + -00V + -in HDB3, the branch is shifted to B00V, and the code of + -1 of the code of B + -in the first 3 memory cells is the code of 0. If f30 is 1, the code ± 1 is the code ± 1 of the code V ± in the code 000V ± in the HDB3, and the branch is shifted to the code 000V. After processing the ± 1 code of the HDB3, no matter

output

0 or 1, AR7 should be reset to 2, f20 to 0, and f30 to 0, so as to process the subsequent input HDB 3code stream.

The linear sliding window of the slide branch is 5 units of double addressing data space data, and the data is copied from a low address unit to a next high address unit by using a DELAY instruction DELAY, so that when the V code is processed, the B code is output in the first three codes. By not immediately outputting the B-code but temporarily storing it, the B-code value that is not output can be modified when the V-code occurs, and then the correct B-value is output.

In the embodiment of the present invention, when the above program is run in the CCS development environment, the output 10000010000010100 simulated waveforms when inputting-1000V-0 +1B-00V-0+10-100 are shown in FIG. 6, where the output decoded waveforms and the input HDB3 waveforms have a time delay of M cycles in time. This is because different program branches are taken to decode the input 0, ± 1 code, different numbers of program instructions are executed, and different numbers of cycles are spent, which may result in different durations of the output code, causing bit jitter. The solution is to find out the maximum decoding output cycle number M in the program executed by decoding the input 0 and + -1 codes, and based on this, adjust the time occupied by the output symbol by adding NOP null operation to other output branches with short execution cycle, so that the duration of the 0 and 1 codes output to the 3 kinds of symbols is the same. It should also be considered that the decoding speed of the received code should be the same as the encoding speed of the transmitting end, which also requires the addition of NOP no-operation commands to achieve consistency in the duration of each encoding.

Claims

1. The RLHDB3 decoding method based on the C54x is characterized by comprising the following steps of:

s3, decoding the HDB 3code through the DSP chip of the C54x series, and further realizing the decoding of the RLHDB3 code;

the step S3 specifically includes:

in a DSP chip of a C54x series, the number of continuous 0 codes in the HDB 3code is determined by setting continuous 0 identifiers, the decoding output of 0 and 1 in 000V code groups, B00V code groups, 1 code and 0 code in the HDB 3code is determined according to the number of the continuous 0 codes, the HDB3 is decoded, and then the decoding of RLHDB 3code is realized;

the set consecutive 0 identifiers include f20 and f 30;

when f20=1, it indicates that the currently received HDB 3code is a B00V code group;

when f30=1, it indicates that the received HDB 3code is 000V code group;

the method for determining the decoding output of 0 and 1 in 000V code group, B00V code group, 1 code and 0 code in HDB 3code according to the number of consecutive 0 is specifically as follows:

a1, sequentially detecting each code value of HDB3 codes;

a3, when 1 code appears in the current HBD 3code, decoding and outputting each 1 code as + 1;

a4, when 1 code appears in the current HDB 3code and f20=1, indicating that the currently received 1 code is V in the B00V code group, storing the B00V code group by setting a linear sliding window of 4 units, decoding the received 1 code to 0 code, and correspondingly decoding the B, 0 and 0 stored in the first three units in the linear sliding window to 0, 0 and 0;

a5, when 1 code appears in the current HDB 3code and f30=1, indicating that 1 code of V in 000V code group is currently received, storing 000V code group by setting a linear sliding window of 4 units, decoding the received 1 to 0 code, and correspondingly decoding 0, 0 and 0 stored in the first three units in the linear sliding window to 0, 0 and 0;

2. The RLHDB3 decoding method according to claim 1, wherein in step S1, the signal receiving module includes a photo-receiver and a ground resistor connected to the negative terminal of the photo-receiver, and the negative terminal of the photo-receiver is connected to the level shifting module as the output terminal of the signal receiving module;

the step S1 specifically includes:

3. An RLHDB3 decoding apparatus for implementing the RLHDB3 decoding method based on C54x as claimed in any one of claims 1-2, said apparatus comprising:

4. The RLHDB3 decoding device of claim 3, wherein the signal processing module comprises:

an input detection unit for detecting whether the currently input HDB 3code is 0 or 1;

the identification determining unit is used for identifying the HDB 3code when the current input is 1 and determining that the HDB 3code is a B00V code or a 000V code;

the code bit sliding unit is used for performing code bit moving operation when the input detection module detects 0 or 1 of the HDB3 code;

a data temporary storage unit for temporarily storing the B00V code group or 000V code group in the currently input HDB3 codes;

5. The RLHDB3 decoding device of claim 4, wherein the decoding output unit comprises a 0-code decoding output mechanism and a 1-code decoding output mechanism;

the 1-code decoding output mechanism is used for decoding and outputting the 1 code detected in the input detection unit as +1, decoding and outputting the B code and the 0 code in the B00V code group or the 000V code group of the data temporary storage module unit as 0, and decoding and outputting the V code detected as 1 in the B00V code group or the 000V code as 0.

6. The RLHDB3 decoding device of claim 3, wherein the signal processing module is a DSP chip of the C54x series.

7. A C54x readable storage medium, the C54x readable storage medium storing a C54x program, wherein the steps of the C54x program when executed implement the C54 x-based RLHDB3 decoding method of any one of claims 1 to 2.