JPS5875949A - Timing extracting circuit for cmi code - Google Patents

Abstract

PURPOSE:To extract timing through simple circuit constitution by digital processing which utilizes the features of CMI codes. CONSTITUTION:An input signal (a) of CMI codes is led to a differentiating circuit 1 which detects the trailing edge of the signal CMI, and the output (b) of this circuit 1 is led directly to an OR circuit 12 and also led to a two-time-slot delay circuit 10 and a one-time-slot delay circuit 11; whose outputs (d) and (c) are inputted to the OR circuit 12 respectively. Then, timing pulses (e) appear at the output of the OR circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bit timing extraction method for extracting bit timing in a receiving section of an optical communication system using C to (I code) as a transmission path code.

The CMI code is a transmission line code often used in optical communication systems because it has the following characteristics: (1) timing extraction is easy, (2) it is a balanced code, and (3) it can detect errors. In the CMI code, the signal "1" is "
11[ and “oO” alternately, and the signal “0”
is represented by "01".

Therefore, even if the same signal continues, there will always be a change point in the CMI signal, making timing extraction easier.

The conventional timing extraction circuit for this purpose includes a differentiating circuit 1 that detects the falling edge of the CMI signal, and a differentiating circuit 1 that is connected to the output terminal of this differentiating circuit 1 and extracts the timing frequency component of the differentiating circuit output waveform, as shown in Fig. 1. The limiter circuit 3 is connected to the tank circuit 2 and keeps the tank circuit output at a constant amplitude.

As shown in FIG. 2, the differentiating circuit 1 includes an inverter circuit 4 that inverts an input signal, a delay circuit 5 that is connected to the inverter circuit 4 and delays the output of the inverter circuit 4, and an output and an input of the delay circuit 5. It is composed of a two-man powered NOR gate circuit 6 that calculates the negative OR of signals.

In such a conventional device, after the differentiating circuit 1 generates a differential pulse whose frequency spectrum becomes a line spectrum, the timing frequency component is extracted using the band f-wave characteristic of the tank circuit 2. Furthermore, since the output level of the tank circuit 2 is thick (varies) depending on the input signal series, it is set to a constant amplitude after being sufficiently amplified by the limiter circuit 3. This has the disadvantage that the circuit configuration is complicated.

An object of the present invention is to provide a timing extraction method with a simple circuit configuration that performs timing extraction by digital processing using the characteristics of CMI codes.

The present invention includes a differentiating circuit that detects a falling edge of a digital input signal, a first delay circuit that delays the output of this differentiating circuit by a time equivalent to two time slots of the digital input signal, and It is characterized by including a second delay circuit that delays the digital input signal by one time slot, and an OR circuit that takes the logical sum of the outputs of the first and second delay circuits and the output of the differentiating circuit. shall be.

An embodiment of the present invention will be described based on the drawings.

FIG. 3 is a block diagram of main parts of an embodiment of the present invention. An input signal a of the CMI signal is led to a differentiating circuit 1 that detects the fall of the CMI signal.

The output of this differentiating circuit 1 is led to delay circuits 10 and 11, and also to the input terminal of a three-man OR circuit 12. A delay circuit 10 is connected to the other input terminal of this OR circuit 12.
．． 11 outputs are respectively led. Delay circuit 10 delays the input signal by two time slots, and delay circuit 11 delays the input signal by one time slot.

FIG. 4 is an operation time chart showing the input or output waveforms at the points indicated by the x marks in FIG.

FIGS. 5 and 6 are explanatory diagrams showing the characteristics of the CMI signal that is the input signal. In other words, as shown in Figure 5, when the input signal is "0.0, ......", the best signal sequence with the lowest fall is used at each time. A falling edge of the signal occurs in the slot, and timing can be extracted by detecting this falling edge. Further, as shown in FIG. 6, if the input signal is "1.
1.0.1.1, O......'' is the worst signal sequence in which falling is the rarest. Even in this case, one falling edge occurs every three time slots. CM I (In the case of the Q signal, at least one falling edge occurs in three consecutive time slots also in other random signals.

Therefore, when a differential pulse is generated by the fall of the C'M I signal and a logical sum of consecutive time slots is taken, a differential pulse is generated in each time slot and timing extraction is performed.

Now, the worst signal sequence [1, 1, 0, 1, 1, 0...
The characteristic operation of the present invention will be explained for the case where "..." is input. In other words, the differentiating circuit 1 receives the input CM
(2) Detect the falling edge of the signal and generate a differential pulse (Figure 4b). The delay circuit 10 delays this differential pulse by two time slots and supplies it to the OR circuit 12 (Fig. 4d).
, the delay circuit 11 delays this differential pulse by one time slot and supplies it to the OR circuit 12 (FIG. 4C). OR circuit 12 is the output of this differentiating circuit 1 and delay circuit 10.1
A timing pulse is generated by ORing the outputs of 1 (Fig. 4e). As a result, one pulse is generated at the output of the OR circuit 12 for each time slot.

As explained above, the timing extraction circuit of the present invention can be configured only with a gate circuit and a delay circuit, and has the advantage of being able to perform timing extraction through digital processing.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams of main parts of a conventional device. FIG. 3 is a block diagram of main parts of an embodiment of the present invention. FIG. 4 is an operation time chart showing input or output waveforms at the points indicated by X marks in FIG. FIG. 5 and FIG. 6 are explanatory diagrams of the CMI signal series. 1... Differential circuit, 2... Tank circuit, 3... Limiter circuit, 4... Inverter circuit, 5.10.11.
...Delay circuit, 6...NOR circuit, 12...OR circuit. Patent applicant: NEC Corporation. Agent Patent Attorney Nao Takashi Ide, 兇 1 Ryo 2 Figure M 3 Zuji 4 Zuji 5 Kuchiji 6 Figure

Claims (1)

[Claims] (1) A differentiating circuit that detects the fall of a digital input signal, a first delay circuit that delays the output of this differentiating circuit by a time equivalent to two time slots of the digital input signal, and a first delay circuit that delays the output of this differentiating circuit by a time corresponding to two time slots of the digital input signal; Timing of a CMI code including a second delay circuit that delays an input signal by one time slot, and an OR circuit that ORs the outputs of the first and second delay circuits and the output of the differentiation circuit. extraction circuit.