SU1327305A1 - Device for separating group signal - Google Patents

Abstract

The invention can be used in information transmission systems in parallel code. The purpose of the invention is to improve noise immunity. The device contains a receiver 1, a synchronization unit 2, a shaper 3 receiving addresses, a control unit 4, a register 5, a counter 6, a KOMMV 7, a converter 8, a code analog and N processing channels, each of which contains a multiplier 9 | integrator 10, delay unit 11, analog switch 12, decision unit 13. The output signal of converter 8 corrects the threshold level in each block 13. After the threshold is corrected, the reference voltage from block 11 through the switched input of the switch 12 comes from its output s block 13, where a second decision is made, which through register 5 is provided to the recipient of information by a command from block 4. The same command performs resetting of counter 6, the whole operation of the device is synchronized using block 2, which, according to synchroinform analysis Atsii from the receiver 1 generates sync pulses that synchronize the operation of the imaging unit 3 and the block 4. 1 Il. / 2 / J from € (L

Description

one

The invention relates to radio engineering and communications and can be used in information transmission systems in parallel code.

The purpose of the invention is to increase noise immunity.

The drawing is structural. the electrical circuit of the device for separating the group signal.

The device contains a receiver 1, block 2 synchronization, driver

3address, control block 4, register 5, counter 6, switch 7, code-to-analog converter 8, and N processing channels, each of which contains multiplier 9, integrator 10, delay block 11, analog switch 12 and decision block 13,

The device for separating the baseband signal works as follows.

In receiver 1, the signal from the link is amplified to the required value, demodulated, and together. those with noise n (t) are fed to the input of N parallel processing channels, in each of which it is multiplied in multiplier 9 with the corresponding receive address signal generated in the former 3, integrated into the integrator .10 and at the time of termination of the signal through the second moment commuted the input of the analog switch 12 from its output is fed to the input of the decision block 13 in the form of a reference voltage. In each decision block 13, which is a threshold block, a decision is made on the processing of a symbol on this channel, which is stored in the corresponding register bit 5,

By read signals from the block

The 4 values of the received code are shifted in the register 5 in the direction of the bit and from the output of the register 5 they go to the M-bit counter 6, in which the number of the unit bits of the code is counted.

After that, the command from block 4 opens the switch 7 and the binary code of the number of units is fed to the input of the converter 8, which converts it into a voltage.

The output signal of the converter 8 corrects the threshold level in each decision block 13. After the threshold correction, the reference voltage from the output of block 11 through the switched in data

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At the moment, the first input of the analog commutator 12 from its output goes to decision block 13, where it is produced (- the second decision is repeated, which is sent to the recipient through register 5. information from the command from block 4, the same command clears counter 6,

10 V the operation of the device is synchronized using block 2, which, by analyzing the sync information from receiver 1, generates sync pulses that synchronize the operation of the shaping unit 3 and block 4.

Claims (1)

Invention Formula A device for dividing a group signal, comprising a receiver, the first output of which is connected to the combined first inputs of N processing channels, the second inputs of which are connected to the corresponding N inputs 25 of the receive address generator, the synchronization input of which is connected via the synchronization unit to the second output of the receiver, each of the N processing channels containing a decision block and serially connected multiplier and integrator, the first input of the multiplier is the first input of the processing channel, the second input of which is the second entrance 2g of the multiplier, the output of the decision block is the output of the processing channel, characterized in that, in order to increase: noise immunity, a control block, a register, 40 counter, switch and converter code - analog, and in each of the N processing channels, serially connected delay block and analog switch are entered, with output 45 of the synchronization unit is connected to the input of the control unit, the first output of which is connected to the combined first control inputs of all N processing channels, the combined second ones gQ control 1sh the inputs of which are connected to the output of the converter code - analogue, the M inputs of which through the switch are connected to the corresponding M inputs of the counter, the synchronizing The gg input of which is combined with the first synchronization input of the control unit, the third output of which is connected to the second synchronization input of the register, the output of which is connected to 3 1327305-4 the counter input, the fourth output is a block input of an analog switch, the control card is connected to a control switch of which is connected to the input of the switch input, and the N inputs of the switch unit whose control input is connected to the outputs of the corresponding one is the second control by the entrance processing channels, in each processing channel, by the first control of which the input of the delay unit whose sub-input is control keys to the integrator output and the second input of the analog switch.