RU2103827C1 - Multichannel communication system - Google Patents

Abstract

FIELD: electric and radio communications for multiplexing various communication lines. SUBSTANCE: system has on sending end encoding unit 1, synchronizer 3, time keyer 3, transmitter 4, synchronizing unit 5; on receiving end, it has receiver 6, matching filter 7, comparator 8, first and second storage units 9, 10, decoder 11, signal retrieval and storage unit 12, synchronizing unit 13, pulse shaper 14, binary counter 15, and communication line 16. EFFECT: improved reliability and simplified design of system receiving part. 1 dwg

Description

 The invention relates to electrical and radio communications and can be used to seal wired, radio, radio relay, optical and space communication lines.

A multi-channel communication system is known, comprising on the transmitting side K multipliers, a signal generator of transmission addresses, a logical processing unit, a transmitter and a sync block; on the receiving side - (2 ^to -1) multipliers, integrators, decision blocks, decoder and message recipients (1).

 However, the known communication system has a low noise immunity.

 Closest to the claimed device is a multi-channel communication system (2).

 It contains a coding unit on the transmitting side, consisting of a signal generator of the transmission addresses and a group signal generator, a transmitter and a sync block, and on the receiving side, a receiver, a signal processing unit, a decoding device, a decoder, a sync block and a signal generator of reception addresses.

In the shaper of the group signal, K multipliers and an adder are combined here, in the signal processing unit - 2 ^k processing channels, and in the resolver - adders and decision blocks. The sync blocks on the transmitting and receiving side ensure the system is operational.

 However, this system is complex and expensive, has low reliability and is difficult to manufacture.

 The invention is aimed at simplifying the receiving system to increase its overall reliability and reduce manufacturing costs.

 For this, in a multi-channel communication system on the transmitting side in the coding unit, the group signal generating unit is made in the form of a temporary manipulator, and the transmission address signal generator is made in the form of a synchronizer, the first input of which is connected to the (K + 1) -th input of the temporary manipulator, and the second - with the (K + 2) -th input and with the input of the sync block, and on the receiving side, the processing unit is made in the form of a single signal processing device (matched filter), a comparator and the first and second memory are connected in series devices, a device for sampling and storing the signal, the signal input of which is connected to the output of the matched filter, the clock input is connected to the output of the comparator, and the output is connected to the second signal input of the comparator, and the pulse shaper and the binary counter are connected in series, the outputs of which are connected to the signal inputs of the first a storage device, the clock input of the comparator connected to the output of the pulse shaper, the second clock inputs of the binary counter and the device for sampling and storing the signal are dynamically coupled to the clock input of the second memory device and connected to the output of the sync block connected to the input of the pulse shaper, the outputs of the second memory device are connected to the corresponding inputs of the decoder.

 The drawing shows a functional diagram of the proposed multi-channel communication system.

 The multi-channel communication system contains on the transmitting side an encoding unit 1, consisting of a synchronizer 2 and a temporary manipulator 3, the first K inputs of which are the information inputs of the system, the (K + 1) and (K + 2) -th inputs are connected respectively to the first and the second outputs of the synchronizer 2, the transmitter 4, connected to the output of the temporary manipulator 3, and the sync block 5, the input of which is connected to the second output of the synchronizer 2, and the output is connected to the second input of the transmitter 4, and on the receiving side - series-connected receiver 6, with Glazed filter (SF) 7, comparator 8, first memory (memory) 9, second memory (memory) 10 and decoder 11, a device for sampling and storing the signal (I / O) 12, the signal input of which is connected to the output of the SF 7, clock input - to the output of the comparator 8, and the output is connected to the second signal input of the comparator 8, and a sync block 13 is connected in series, the input of which is connected to the second synchronizing output of the receiver 6, a pulse shaper (FI) 14 and a binary counter (DS) 15, the outputs of which are connected to relevant signal nymi input memory 9, the clock input of comparator 8 is connected to the output of PI 14, SHA second clock inputs 12 and 15 are combined with the CP clock input of the memory 10 and are connected to the output of the sync block 13; the transmitting and receiving sides of the system are connected via a communication line 16, the outputs of the decoder 11 are the outputs of the system.

 The multi-channel system operates as follows.

On the transmitting side K (K = 1,2,3 ...) of synchronous channel signals, consisting of characters "1" and "0" of duration T and representing a K-digit number in binary parallel form, are sent to the temporary manipulator 3, so that at its output at time moment τ _s = ST / 2 ^k (where S is the value of the input binary number in decimal form) relative to the leading edge of the pulse acting on the second output of synchronizer 2 and coinciding in time with the beginning of channel symbols, a rectangular pulse is formed (or pseudo-random signal) of duration T / 2 ^k equal to the period of short pulses from the first output of synchronizer 2. Thus, each combination of input channel symbols corresponds to one of 2 ^k time positions of the signal of block 3 in the time interval 0, T (etc.). The received group signal together with synchronization signals coming from the sync block 5 and carrying information about the beginning of channel symbols are transmitted by transmitter 4 via communication line 16. At the receiving side, the group signal coming along with interference from the output of receiver 6 is optimally processed in SF 7 and arrives at the signal inputs of comparator 8 and UVX 12. At the inputs of FI 14, UVX 12, DS 15 and memory 10, short clock pulses with a period T equal to the duration of the information symbols generated in the sync block 13 on the output sync the receiver 6 signal and coinciding in time with the moments when they are received. When the first clock pulse arrives at its trailing edge, the UVX 12, DS 15 and ZU 10 are zeroed, and 2 ^k short pulses with a period T / 2 ^k corresponding in time to the possible positions of the filtered signal maximums are generated at the output of FI 14. At the time of the first of them (its leading edge), the signal from the output of the SF 7 enters the comparator 8 and is compared in level with the signal supplied to its second signal input from the UVX 12 unit (in this case, zero). If it turns out to be larger than the last, then at the output of the comparator 8 a voltage drop is formed, which opens the input of the UVX 12 and allows it to remember the level of the output signal of the SF 7. This procedure is repeated 2 ^k times. As a result, by the time the second clock pulse arrives from the output of block 13 in the UVX 12, the level of the largest of the output signals of the SF 7 is recorded for a time equal to T. The binary K-bit counter DS 15 is designed to count the number of pulses received from the output of the FI block 14. Each time a voltage drop appears at the output of comparator 8, the readings of K bits of the DS 15 are read in the memory 9. This allows you to record the number of the temporary position of the largest of the output signals of the SF 7 on the time interval T. At the time of arrival the second clock from the output of the sync block 13, the number recorded in the memory 9 is recorded in the memory 10. The decoder 11 uniquely converts the input binary number into channel symbols, which, in the absence of interference, coincide with the transmitted information symbols.

 Thus, the proposed multi-channel communication system allows to simplify its receiving part, to increase the overall reliability and reduce the manufacturing cost.

Sources of information
1. USSR author's certificate N 809611, H 04 J 11/00, dated 02.28.81.

 2. USSR author's certificate N 907834, H 04 J 11/00, dated 23.02.82.

Claims (1)

 A multi-channel communication system comprising, on the transmitting side, a coding unit consisting of a transmission address signal conditioner and a group signal conditioner, a transmitter and a sync block, the first K inputs of a group signal conditioner being information outputs of the system, and K code inputs connected to the corresponding outputs of the transmission address signal conditioner the sync output of which through the sync block is connected to the second input of the transmitter, the first input of which is connected to the output of the shaper group drove, and on the receiving side, a receiver and a signal processing unit connected in series, a sync block, the input of which is connected to the synchronizing output of the receiver, and a decoder, the outputs of which are outputs of the system, the transmitting and receiving sides being connected by a communication line, characterized in that on the transmitting side the coding unit, the shaper of the group signal is made in the form of a temporary manipulator, and the shaper of the addresses of the transmission addresses in the form of a synchronizer, the first output of which is connected to the (K + 1) -th input temporarily about the manipulator, the second with the (K + 2) -th input and with the input of the synchro block, and on the receiving side the signal processing unit is made in the form of a matched filter and serial comparator and first and second memory devices, a signal sampling and storage device, a signal input are introduced which is connected to the output of the matched filter, the clock input to the output of the comparator, and the output is connected to the second signal input of the comparator, and a pulse shaper and a binary counter connected in series, the outputs of which are connected with the signal inputs of the first memory device, the clock input of the comparator connected to the output of the pulse shaper, the second clock inputs of the binary counter and the device for sampling and storing the signal are combined with the clock input of the second memory device and connected to the output of the sync block connected to the input of the pulse shaper, the outputs of the second memory devices are connected to the corresponding inputs of the decoder.