CN111725314A - 多方向沟道晶体管和包括多方向沟道晶体管的半导体器件 - Google Patents
多方向沟道晶体管和包括多方向沟道晶体管的半导体器件 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000002955 isolation Methods 0.000 claims description 60
- 230000002093 peripheral effect Effects 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 description 25
- 210000004027 cell Anatomy 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 13
- 239000006185 dispersion Substances 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 230000001154 acute effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 150000004645 aluminates Chemical class 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 210000002568 pbsc Anatomy 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
提供了具有多方向沟道和拥有增加的有效宽度的栅极的多方向沟道晶体管、以及包括该多方向沟道晶体管的半导体器件,其中该多方向沟道晶体管包括:至少一个鳍,在衬底上的有源区上,并且与在第一方向上延伸的凹陷相邻设置;栅线,在交叉第一方向的第二方向上延伸,并且覆盖所述至少一个鳍和凹陷的至少一部分;源/漏区,在栅线两侧处的有源区上;以及沟道区,在源/漏区之间在栅线下方的有源区中,其中第一方向与第二方向斜交,并且栅线下方的电介质膜在所述至少一个鳍和凹陷两者上具有基本相同的厚度。
Description
技术领域
本发明构思涉及半导体器件,更具体地,涉及包括与凹陷相邻设置的鳍的晶体管和包括该晶体管的半导体器件。
背景技术
随着电子技术的发展,近来半导体器件的按比例缩小正在迅速发展。近来,为了提高操作速度以及关于操作的精度,已经进行了各种研究以优化半导体器件中的晶体管的结构。
发明内容
本发明构思提供了包括多方向沟道和具有增加的有效宽度的栅极的多方向沟道晶体管、以及包括该多方向沟道晶体管的半导体器件。
根据本发明构思的一些示例实施方式,提供了一种多方向沟道晶体管,其包括:至少一个鳍,在衬底上的有源区上,并且与在第一方向上延伸的凹陷相邻设置;第一栅线,覆盖所述至少一个鳍和凹陷的至少一部分,并且在交叉第一方向的第二方向上延伸;源/漏区,在栅线两侧处的有源区中;以及沟道区,在源/漏区之间在栅线下方的有源区中,其中第一方向是相对于第二方向的斜交方向,并且栅线下方的电介质膜在所述至少一个鳍和凹陷两者上具有基本相同的厚度。
根据本发明构思的一些示例实施方式,提供了一种多方向沟道晶体管,其包括第一晶体管和第二晶体管,第一晶体管包括在衬底上的第一有源区上并且与在第一方向上延伸的第一凹陷相邻设置的至少一个第一鳍、以及在交叉第一方向的第二方向上延伸同时覆盖所述至少一个第一鳍和第一凹陷的至少一部分的第一栅线,第二晶体管包括在衬底上的第二有源区上并且与在第三方向上延伸的第二凹陷相邻设置的至少一个第二鳍、以及在第四方向上延伸并且覆盖所述至少一个第二鳍和第二凹陷的至少一部分的第二栅线,其中,在第一有源区中第一方向是与第二方向垂直的方向,在第二有源区上第三方向是与第四方向斜交的方向。
根据本发明构思的一些示例实施方式,提供了一种半导体器件,其包括:衬底,该衬底包括单元区和外围区,单元区包括多个单元,外围区与单元区相邻设置,外围区包括至少一个第一晶体管,其中所述至少一个第一晶体管包括至少一个第一鳍和第一栅线,所述至少一个第一鳍形成在外围区上的第一有源区上并且与在第一方向上延伸的第一凹陷相邻设置,第一栅线在交叉第一方向的第二方向上延伸并且覆盖所述至少一个第一鳍和第一凹陷的至少一部分,在第一有源区上第一方向与第二方向斜交,第一栅线下方的电介质膜在所述至少一个第一鳍和第一凹陷两者上具有基本相同的厚度。
附图说明
本发明构思的一些示例实施方式将由以下结合附图的详细描述被更清楚地理解,附图中:
图1是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图;
图2A至图2D是分别沿图1的线I-I'、II-II'、III-III'和IV-IV'截取的剖视图;
图3A至图3D是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图;
图4是根据本发明构思的一些示例实施方式的多方向沟道晶体管的剖视图;
图5A是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图;
图5B是沿图5A的线V-V'截取的剖视图;
图6和图7是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图;
图8是根据本发明构思的一些示例实施方式的包括多方向沟道晶体管的半导体器件的俯视图;以及
图9A至图9F是用于描述根据本发明构思的一些示例实施方式的制造图1的多方向沟道晶体管的工艺的剖视图。
具体实施方式
在下文中,将参照附图详细描述本发明构思的一些实施方式。相同的附图标记用于附图中相同的构成元件,并且将省略其重复描述。
图1是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图。图2A至图2D是分别沿图1的线I-I'、II-II'、III-III'和IV-IV'截取的剖视图。
参照图1和图2A至图2D,根据本发明构思的一些示例实施方式的多方向沟道晶体管100可以包括衬底101、有源区Act、鳍Fn、栅线110和/或接触140。
衬底101可以包括硅(Si),例如,单晶硅、多晶硅和/或非晶硅。然而,衬底101的材料不限于硅。例如,在一些示例实施方式中,衬底101可以包括:IV族半导体,诸如锗等;IV-IV族化合物半导体,诸如硅锗(SiGe)、硅碳化物(SiC)等;和/或III-V族化合物半导体,诸如镓砷化物(GaAs)、铟砷化物(InAs)、铟磷化物(InP)等。
衬底101可以包括基于硅体衬底的衬底或基于绝缘体上硅(SOI)衬底的衬底。衬底101不限于硅体衬底或SOI衬底,并且可以包括基于外延晶片、抛光晶片、退火晶片等的衬底。取决于所掺杂的杂质离子的类型,衬底101可以被归类为P型衬底或N型衬底。此外,衬底101可以包括各种结构,例如,诸如用杂质掺杂的阱区的导电结构和诸如器件隔离区的绝缘结构。
有源区Act可以形成在衬底101上。有源区Act可以与器件隔离区150相邻设置,并且当从上方观察时在俯视图上可以具有矩形形状,如图1所示。然而,有源区Act的形状不限于矩形。器件隔离区150可以形成为在衬底101中具有预定的(或者作为选择地给定的)深度,并且可以包括绝缘材料。例如,器件隔离区150可以包括氧化物膜、氮化物膜和氮氧化物膜当中的任何一种。
源/漏区120和沟道区130可以形成在有源区Act中。源/漏区120可以通过用杂质离子掺杂栅线110两侧的有源区Act的上部而形成。或者,源/漏区120可以包括用杂质离子重且深地掺杂的重掺杂区、以及用杂质离子轻且浅地掺杂的轻掺杂区。沟道区130可以在栅线110下方形成在源/漏区120之间。
与凹陷Re相邻设置的至少一个鳍Fn可以形成在有源区Act的上部中。如图2D所示,一个鳍Fn可以通过两个凹陷Re形成在有源区Act的上部中。当形成在器件隔离区150中的凹陷Re被一起考虑时,三个鳍Fn可以形成在有源区Act上。凹陷Re的数量以及因此鳍Fn的数量不限于上述数量。例如,三个或更多个凹陷Re可以形成在有源区Act上,因此可以形成两个或更多个鳍Fn。
凹陷Re可以形成为在相对于栅线110的斜交方向上延伸遍及有源区Act的结构。取决于这种凹陷Re的结构,有源区Act上的鳍Fn也可以形成为在相对于栅线110的斜交方向上延伸遍及有源区Act的结构。关于凹陷Re和鳍Fn的斜交方向,这些将在以下对凹陷Re和鳍Fn的延伸方向与栅线110的延伸方向之间的第一角度θ1的说明中被更详细地描述。
如图2D所示,凹陷Re可以包括形成在有源区Act上的有源区凹陷Rea和/或形成在器件隔离区150上的隔离区凹陷Rei。取决于示例实施方式,隔离区凹陷Rei可以被省略。此外,隔离区凹陷Rei可以基本上在与有源区凹陷Rea相同的方向上形成。因此,凹陷Re可以形成在有源区Act和器件隔离区150两者中。凹陷Re的延伸方向将在以下对沟道的方向和栅线110的宽度的说明中被更详细地描述。
栅线110可以在第二方向(Y方向)上延伸。例如,栅线110可以在第二方向(Y方向)上延伸,同时覆盖鳍Fn的顶表面和侧表面以及凹陷Re的底表面。栅线110的具体结构将在以下对图9F的说明中被更详细地描述。
间隔物114可以形成在栅线110的两侧。在图1中,间隔物114被省略。间隔物114可以在与鳍Fn对应的部分中形成在栅线110的两侧上,如图2A所示。然而,间隔物114可以在与凹陷Re对应的部分中形成在栅线110的两侧上且形成在有源区Act的上表面上,如图2B所示。即,在与凹陷Re对应的部分中,间隔物114可以从栅线110的两侧延伸到有源区Act的上表面上。这是因为,首先,用于形成间隔物的材料膜可以在凹陷Re的一部分上比在鳍Fn和栅线110的上表面上形成得厚,然后在通过蚀刻工艺形成间隔物114的工艺中,形成在鳍Fn和栅线110的上表面上的用于形成间隔物的所有材料膜可以被去除,但是形成在凹陷Re上的用于形成间隔物的材料膜的一部分可以保留。例如,在凹陷Re的该部分中的间隔物114可以具有第一厚度D1,并且第一厚度D1可以基本上等于凹陷Re的深度。取决于示例实施方式,间隔物114的第一厚度D1可以小于凹陷Re的深度。
电介质膜112可以设置在栅线110的下表面上。电介质膜112可以在第二方向(Y方向)上延伸,同时以与栅线110相同的方式覆盖鳍Fn的顶表面和侧表面以及凹陷Re的底表面。电介质膜112可以在鳍Fn的顶表面和侧表面上以及在凹陷Re的底表面上具有均一的厚度。例如,当电介质膜112在鳍Fn的顶表面上具有第一厚度T1并且电介质膜112在凹陷Re的底表面上具有第二厚度T2时,第一厚度T1可以基本上等于第二厚度T2。
作为参照,在包括鳍的传统晶体管结构的情况下,鳍可以通过外延生长在有源区上形成为升高的结构。此外,绝缘材料的隔离膜可以形成在鳍之间的下部中。隔离膜可以用作电介质膜,因而电介质膜会在鳍之间的部分中厚地形成,因此沟道在鳍之间的形成可能是困难的。
在根据本发明构思的一些示例实施方式的多方向沟道晶体管100的情况下,凹陷Re可以通过蚀刻工艺形成在有源区Act上,因此鳍Fn可以通过凹陷Re的形成而形成。同时,在鳍Fn之间的凹陷Re中可以不布置单独的隔离膜。因此,电介质膜112可以在鳍Fn的顶表面和凹陷Re的底表面上以基本相同的厚度形成,并且在凹陷Re的位于鳍Fn之间的部分下方的有源区Act可以用作沟道区。
电介质膜112可以包括高k电介质材料。例如,电介质膜112可以包括铪氧化物(HfO2)、铪硅氧化物(HfSiO4)、镧氧化物(La2O3)、镧铝氧化物(LaAlO3)、锆氧化物(ZrO2)、锆硅氧化物(ZrSiO4)、钽氧化物(Ta2O5)、钛氧化物(TiO2)、锶钛氧化物(SrTiO3)、钇氧化物(Y2O3)、铝氧化物(Al2O3)、铅钪钽氧化物(PbSc0.5Ta0.5O3)、铅锌铌氧化物(PbZnNbO3)等。
电介质膜112可以包括金属氧化物、或者其硅酸盐或铝酸盐。此外,电介质膜112可以包括金属氮氧化物、或者其硅酸盐或铝酸盐。此外,电介质膜112可以包括钙钛矿型氧化物、铌酸盐或钽酸盐基系统材料、钨青铜基系统材料和双层钙钛矿基(Bi-layeredperovskite-based)系统材料等。
如图2D所示,电介质膜112也可以形成在器件隔离区150上。取决于示例实施方式,电介质膜112可以不形成在器件隔离区150上。
接触140可以形成在源/漏区120上。接触140可以形成为插入到源/漏区120的上部中的结构。此外,接触140可以形成为穿过形成在凹陷Re的一部分中的间隔物114。换言之,接触140可以穿过凹陷Re的该部分中的间隔物114连接到源/漏区120。
与接触140从源/漏区120或间隔物114的顶表面插入到源/漏区120中的深度对应的第二厚度D2可以大于作为间隔物114的厚度的第一厚度D1。如图2C所示,接触140的下表面可以低于凹陷Re的底表面,而且接触140的所有下表面可以低于凹陷Re的底表面。因此,接触140可以具有可通过与鳍Fn的延伸方向交叉而完全切割鳍Fn的结构。因此,通过具有接触140可完全切割鳍Fn的结构,鳍Fn的切割表面可以与接触140的侧表面的一部分完全接触。因此,可以改善鳍Fn和接触140之间的电特性,因而可以改善晶体管的操作特性。
在包括鳍的传统晶体管的情况下,接触可以形成为这样的结构,其中接触围绕鳍的侧表面的部分和顶表面。因此,鳍和接触之间的电特性以及因此晶体管的操作特性可能不好。相比之下,在一些示例实施方式的多方向沟道晶体管100中,接触140可以被形成为使得鳍Fn结构的整个切割表面与接触140的侧表面接触,因此可以有效地减少或防止传统晶体管的问题。
取决于示例实施方式,接触140的下表面可以形成得高于凹陷Re的底表面。在这种情况下,接触140可以具有这样的结构:接触140可以通过与鳍Fn的延伸方向交叉而切割鳍Fn的上部,使得鳍Fn的上部可以与接触140的侧表面接触。此外,取决于示例实施方式,接触140可以形成为这样的结构,其中接触140可以覆盖鳍Fn的上表面和侧表面和凹陷Re而不切割鳍Fn,与栅线110类似。
当多个凹陷Re形成在有源区Act上时,接触140可以被形成为在一个方向上覆盖全部所述多个凹陷Re。换言之,接触140可以在一个方向上重叠全部所述多个凹陷Re。此外,接触140的下表面可以形成得低于全部所述多个凹陷Re的底表面。因此,由所述多个凹陷Re形成的所有鳍Fn可以与接触140的侧表面接触。
例如,如图1所示,当接触140具有在第二方向(Y方向)上延伸的形状并且两个凹陷Re形成在斜交方向上时,接触140可以在第二方向(Y方向)上一起覆盖全部两个凹陷Re。换言之,接触140可以在第二方向(Y方向)上重叠全部两个凹陷Re。此外,接触140的下表面可以形成得低于这两个凹陷Re两者的底表面,使得由这两个凹陷Re形成的鳍Fn可以与接触140的侧表面接触。此外,如图2C所示,鳍的设置在器件隔离区150和凹陷Re之间的部分也可以与接触140的侧表面接触。
一些示例实施方式的多方向沟道晶体管100可以包括通过凹陷Re形成在有源区Act上的鳍Fn。此外,凹陷Re和由其形成的鳍Fn可以在相对于栅线110的斜交方向上延伸。例如,凹陷Re和鳍Fn延伸的方向可以相对于栅线110沿其延伸的第二方向(Y方向)具有第一角度θ1。第一角度θ1可以是小于90°的锐角。具体地,在一些示例实施方式的多方向沟道晶体管100中,第一角度θ1可以具有30°至70°的角度。然而,第一角度θ1不限于以上数值。例如,第一角度θ1可以小于30°或大于70°。
在一些示例实施方式的多方向沟道晶体管100中,通过借助于由蚀刻工艺形成的凹陷Re而形成鳍Fn,栅线110的有效宽度例如栅极的有效宽度可以增加。通常,在晶体管中,沟道长度可以被限定在电流流动的方向上,并且沟道宽度可以被限定在与电流流动的方向垂直的方向上。此外,沟道长度可以对应于栅极的有效长度,并且沟道宽度可以对应于栅极的有效宽度。例如,在图1中,栅极的沟道长度或有效长度可以被限定在鳍Fn沿其延伸的方向上,并且栅极的沟道宽度或有效宽度可以被限定在第二方向(Y方向)上。
如图2D所示,因为凹陷Re和由其形成的鳍Fn两者可以形成在栅线110下方,所以栅极的有效宽度可以增加。此外,因为凹陷Re和鳍Fn可以形成在相对于栅线110的斜交方向上,所以与其中凹陷Re和鳍Fn形成在与栅线110垂直的方向上的结构相比,栅极的有效长度也可以增加。
当栅极的有效长度增加时,可以减少或防止诸如短沟道效应的问题,并且可以提高可靠性。此外,当栅极的有效宽度增加时,可以改善晶体管的导通/截止操作特性。换言之,在相同的截止电流下,当栅极的有效宽度增加时导通电流增大,从而可以减小阈值电压,因而可以改善晶体管的导通/截止操作特性。
栅极的有效长度和有效宽度的增加可以有助于改善阈值电压的离散σ。这里,阈值电压的离散σ意思是关于相邻晶体管之间阈值电压的差异或不匹配的离散,并且可以由以下等式(1)表示。
σ(Vth-RDF)=Bvt[Tinv(Vth+0.1)/(L*W)]1/2............等式(1)
在等式(1)中,Bvt表示竹内曲线(Takeuchi plot)的斜率,Tinv表示电介质膜的厚度,L和W分别表示栅极长度和栅极宽度。基于等式(1),可以理解,当栅极长度L和/或栅极宽度W增加时,阈值电压的离散σ可以减小。
此外,当将一些示例实施方式的多方向沟道晶体管100的阈值电压的离散(σ)与传统参考晶体管的阈值电压的离散(σ)相比时,阈值电压的离散(σ)可能稍微类似于传统参考晶体管的阈值电压的离散(σ),但与传统参考晶体管相比,与50%的中心值对应的阈值电压的失配值可以减小。最终,与传统参考晶体管相比,可以预期本发明构思的一些示例实施方式的多方向沟道晶体管100的阈值电压的离散σ减小。
在一些示例实施方式的多方向沟道晶体管100中,沟道的方向可以由鳍Fn沿其延伸的方向确定。例如,当凹陷Re和由其产生的鳍Fn形成在相对于栅线110的斜交方向上时,沟道的方向也可以形成在相对于栅线110的斜交方向上。当接触140如图1所示地形成并且电压通过接触140施加到源/漏区120时,有可能大部分电流在导通状态下流过鳍Fn,使得鳍Fn的延伸方向可以对应于沟道的方向。因此,在本发明构思的一些示例实施方式的多方向沟道晶体管100中,术语“多方向”可以意思是沟道方向可取决于凹陷Re和由其产生的鳍Fn的延伸方向被各种各样地确定。在以下示例实施方式的多方向沟道晶体管中,术语“多方向”可以在相同的意义上使用。
图3A至图3D是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图。先前在上面参照图1至图2D给出的描述被简要地提供或者被省略。
参照图3A,一些示例实施方式的多方向沟道晶体管100a可以在凹陷Re1的形式上不同于图1的多方向沟道晶体管100。具体地,在一些示例实施方式的多方向沟道晶体管100a中,凹陷Re1可以仅形成在栅线110下方。因此,与凹陷Re1相邻设置的鳍Fn1可以仅形成在栅线110下方。
或者,凹陷Re1和鳍Fn1的延伸方向可以是相对于栅线110的斜交方向。然而,因为凹陷Re1和鳍Fn1可以仅形成在栅线110下方,所以凹陷Re1和鳍Fn1的延伸方向与栅线110的延伸方向之间的角度可以不显著。例如,凹陷Re1和鳍Fn1可以在相对于栅线110的平行方向或垂直方向上延伸。
尽管未示出,但是因为凹陷Re1可以仅形成在栅线110下方,所以间隔物(参见图2A中的间隔物114)可以仅形成在栅线110的侧表面上。此外,接触140可以形成为这样的结构,其中接触140插入到源/漏区120的上部中,并且接触140可以不具有穿透间隔物114的部分。
参照图3B,一些示例实施方式的多方向沟道晶体管100b可以在凹陷Re2的形式上不同于图1的多方向沟道晶体管100。具体地,在一些示例实施方式的多方向沟道晶体管100b中,凹陷Re2可以形成为从栅线110的下部延伸到栅线110的两侧之外的结构。此外,与凹陷Re2相邻设置的鳍Fn2也可以形成为从栅线110的下部延伸到栅线110的两侧之外的结构。
凹陷Re2和鳍Fn2的延伸方向可以与栅线110斜交。例如,凹陷Re2和鳍Fn2沿其延伸的方向可以相对于栅线110沿其延伸的第二方向(Y方向)具有第一角度θ1。第一角度θ1可以是小于90°的锐角,并且在一些示例实施方式的多方向沟道晶体管100b中,第一角度θ1可以具有30°至70°的角度。然而,第一角度θ1不限于以上数值。
参照图3C,一些示例实施方式的多方向沟道晶体管100c可以在凹陷Re3的形式上不同于图1的多方向沟道晶体管100。具体地,在一些示例实施方式的多方向沟道晶体管100c中,凹陷Re3可以在从栅线110的两侧向外延伸的同时从栅线110的下部延伸到接触140的下部。此外,与凹陷Re3相邻设置的鳍Fn3也可以从栅线110的下部延伸到接触140的下部,同时从栅线110的两侧向外延伸。即使在接触140的区域中与凹陷Re3对应的部分在图3C中被显示为虚线,但是因为接触140的下表面可以形成得比凹陷Re3的底表面深,所以凹陷Re3的底表面实际上可以不存在。此外,由凹陷Re3形成的鳍Fn3可以由于接触140的结构而仅延伸到接触140的侧表面。
凹陷Re3和鳍Fn3的延伸方向可以相对于栅线110斜交。例如,凹陷Re3和鳍Fn3沿其延伸的方向可以相对于栅线110沿其延伸的第二方向(Y方向)具有第一角度θ1。第一角度θ1可以是小于90°的锐角,并且在一些示例实施方式的多方向沟道晶体管100c中,第一角度θ1可以具有30°至70°的角度。然而,第一角度θ1不限于以上数值。
参照图3D,一些示例实施方式的多方向沟道晶体管100d可以在凹陷Re4的形式上不同于图1的多方向沟道晶体管100。具体地,在一些示例实施方式的多方向沟道晶体管100d中,凹陷Re4可以在从栅线110的两侧向外跨过接触140延伸的同时从栅线110的下部延伸到有源区Act之外的器件隔离区150。然而,鳍Fn4可以仅设置在有源区Act中。因此,鳍Fn4可以具有与图1的多方向沟道晶体管100的鳍Fn基本相同的结构。此外,凹陷Re4和鳍Fn4与接触140有关的结构可以与图1至图2D的描述中所述的相同。另外,凹陷Re4和鳍Fn4的延伸方向也可以与图1至图2D的描述中所述的相同。
图4是根据本发明构思的一些示例实施方式的多方向沟道晶体管的剖视图,并且可以对应于图2D。先前在上面参照图1至图3D给出的描述被简要地提供或者被省略。
参照图4,一些示例实施方式的多方向沟道晶体管100e可以在凹陷Re'的形式上不同于图1的多方向沟道晶体管100。具体地,在一些示例实施方式的多方向沟道晶体管100e中,凹陷Re'可以包括形成在有源区Act上的有源区凹陷Rea和形成在器件隔离区150上的隔离区凹陷Rei'。在图1的多方向沟道晶体管100中,有源区凹陷Rea和隔离区凹陷Rei可以形成为具有相同的深度。例如,有源区凹陷Rea和隔离区凹陷Rei两者可以以与第一厚度D1对应的深度形成。或者,在一些示例实施方式的多方向沟道晶体管100e中,隔离区凹陷Rei'可以形成得比有源区凹陷Rea深。例如,有源区凹陷Rea可以形成在与第一厚度D1对应的深度处,隔离区凹陷Rei'可以形成在与第三厚度D3对应的深度处,第三厚度D3可以大于第一厚度D1。
在一些示例实施方式的多方向沟道晶体管100e中,因为凹陷Re'形成为如上所述的结构,所以电介质膜112a的形成在隔离区凹陷Rei'中的部分可以定位得低于电介质膜112a的形成在有源区凹陷Rea中的部分。
取决于示例实施方式,隔离区凹陷Rei'可以形成为比有源区凹陷Rea浅。例如,第三厚度D3可以小于第一厚度D1。此外,如上所述,凹陷可以不形成在器件隔离区150中。
在一些示例实施方式的多方向沟道晶体管100e中,与凹陷Re'的延伸方向有关的结构可以像在图1至图3D的多方向沟道晶体管100和/或100a至100d中那样被各种各样地形成。例如,凹陷Re'可以形成为各种结构,包括仅形成在栅线110a的下部上的结构、在栅线110a的两侧向外延伸的结构、延伸到接触140的结构、延伸遍及有源区Act的结构、以及延伸到器件隔离区150的结构等。
图5A是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图,图5B是沿图5A的线V-V'截取的剖视图。先前在上面参照图1至图4给出的描述被简要地提供或者被省略。
参照图5A和图5B,一些示例实施方式的多方向沟道晶体管100f可以在凹陷Re5的方向上不同于图1的多方向沟道晶体管100。具体地,在一些示例实施方式的多方向沟道晶体管100f中,凹陷Re5可以形成为在栅线110b的下部下方沿栅线110b延伸的方向(即,沿第二方向(Y方向))延伸的结构。由于凹陷Re5以该结构形成,因此可以不形成鳍。
如在图3A的多方向沟道晶体管100a的情况下那样,间隔物(参见图2A中的114)可以仅形成在栅线110b的侧面上。此外,接触140还可以形成为这样的结构,其中接触140插入到源/漏区120的上部中。接触140可以不具有穿透间隔物114的部分。另外,电介质膜112b可以设置在栅线110b的下表面上。
在一些示例实施方式的多方向沟道晶体管100f的情况下,因为凹陷Re5可以形成为在栅线110b的下部下方沿第二方向(Y方向)延伸的结构,所以可以增加栅线110b的有效长度。因此,如上所述,可以抑制短沟道效应,从而可以提高可靠性并且可以改善阈值电压的离散σ。
图6和图7是根据本发明构思的一些示例实施方式的多方向沟道晶体管的俯视图。先前在上面参照图1至图5B给出的描述被简要地提供或者被省略。
参照图6,根据一些示例实施方式的多方向沟道晶体管200可以在衬底(参见图2A中的101)上包括第一区A1中的第一晶体管100-1和/或第二区A2中的第二晶体管100-2。
第一晶体管100-1的结构可以与图1的多方向沟道晶体管100的结构基本相同。因此,将省略其详细描述。第一晶体管100-1的结构不限于图1的多方向沟道晶体管100的结构,并且可以与图3A至图5A的多方向沟道晶体管100a至100f中的任何一个的结构基本相同。
第二晶体管100-2的结构可以在凹陷Rep和由其产生的鳍Fnp的延伸方向上不同于第一晶体管100-1的结构。具体地,在第二晶体管100-2中,凹陷Rep和鳍Fnp可以在与栅线110沿其延伸的第二方向(Y方向)垂直的方向上(即,在第一方向(X方向)上)延伸。间隔物(参见图2A中的114)、电介质膜(参见图2A中的112)和/或接触140等的结构可以与对图1的多方向沟道晶体管100描述的那些相同。
在第二晶体管100-2中,因为凹陷Rep和鳍Fnp形成在与栅线110垂直的方向上,所以栅线110的有效宽度可以增加。因此,可以改善晶体管的导通/截止操作特性,并且可以改善阈值电压的离散σ。
第二晶体管100-2的结构可以与图3A至图4的多方向沟道晶体管100a至100e的结构类似地修改。例如,第二晶体管100-2可以具有以下当中的任何一种结构:其中与图3A的多方向沟道晶体管100a类似,凹陷Rep和鳍Fnp仅形成在栅线110的下部下方的结构;其中与图3B的多方向沟道晶体管100b类似,凹陷Rep和鳍Fnp从栅线110的下部朝向栅线110的两侧之外向外延伸的结构;其中与图3C的多方向沟道晶体管100c类似,凹陷Rep和鳍Fnp从栅线110的下部朝向栅线110的两侧之外向外延伸并且延伸到接触140的结构;以及其中与图3D的多方向沟道晶体管100d类似,凹陷Rep从栅线110的下部朝向栅线110的两侧之外延伸,然后经过接触140延伸到器件隔离区150的结构。此外,第二晶体管100-2可以形成为这样的结构,其中与图4的多方向沟道晶体管100e类似,隔离区凹陷(参见图4中的Rei')形成得比有源区凹陷(参见图4中的Rea)深。
参照图7,根据一些示例实施方式的多方向沟道晶体管300可以在衬底(参见图2A中的101)上包括第一区A1中的第一晶体管100-1、第二区A2中的第二晶体管100-2和/或第三区A3中的第三晶体管100-3。
第一晶体管100-1的结构可以与图1的多方向沟道晶体管100的结构基本相同。然而,第一晶体管100-1的结构不限于图1的多方向沟道晶体管100的结构,并且可以与图3A至图4的多方向沟道晶体管100a至100e中的任何一个的结构基本相同。
第二晶体管100-2的结构可以与图6的第二晶体管100-2的结构基本相同。因此,将省略对第二晶体管100-2的结构的详细描述。第二晶体管100-2的结构可以与图3A至图4的多方向沟道晶体管100a至100e的结构当中的任何一个相似地修改。其中第一晶体管100-1的第一电介质膜和第二晶体管100-2的第二电介质膜具有基本相同的厚度。
第三晶体管100-3的结构可以与图5A的多方向沟道晶体管100f的结构基本相同。也就是,凹陷Re5可以在栅线110b的下部下方沿栅线110b延伸的第二方向(Y方向)延伸。
在一些示例实施方式的多方向沟道晶体管300中,具有对应结构的多个晶体管可以设置在第一区A1至第三区A3中的至少一个中。此外,取决于示例实施方式,第一区A1至第三区A3当中的至少一个可以在衬底101上设置为多个。
在一些示例实施方式的多方向沟道晶体管300中,设置在第一区A1至第三区A3上的第一晶体管100-1至第三晶体管100-3可以同时形成,或者可以针对每个区分开形成。当第一晶体管100-1至第三晶体管100-3同时形成时,第一区A1至第三区A3可以通过使用相同掩模一起执行蚀刻工艺而形成。例如,通过使用一个掩模的一次蚀刻工艺,第一晶体管100-1至第三晶体管100-3中包括的凹陷Re、Rep和Re5以及鳍Fn和Fnp被同时形成。
图8是根据本发明构思的一些示例实施方式的包括多方向沟道晶体管的半导体器件的俯视图。先前在上面参照图1至图7给出的描述被简要地提供或者被省略。
参照图8,一些示例实施方式的半导体器件1000可以包括设置在衬底上的单元区域CA和/或外围区域PA1和/或PA2。在单元区域CA中,多个单元可以布置成阵列结构。例如,在半导体器件1000是DRAM器件或闪速存储器件的情况下,与单元区域CA中的每个器件对应的多个存储单元可以布置成阵列结构。当然,半导体器件1000不限于DARM器件或闪速存储器件。例如,半导体器件1000可以是图像传感器器件。在这种情况下,多个像素可以在单元区域CA中布置成阵列结构。
外围区域PA1和/或PA2可以提供有用于从单元区域CA读取数据或者将数据写入单元区域CA的电路、用于信号处理的电路和/或用于供电的电路。外围区域PA1和/或PA2也可以被称为核心/外围区域。此外,取决于示例实施方式,用于读/写的电路部分可以被称为核心区域,并且用于其它信号处理等的电路部分可以被称为外围区域。在一些示例实施方式的半导体器件1000中,外围区域PA1和/或PA2可以指的是除单元区域CA之外布置在单元区域CA周围的所有区域。同时,即使在图8中在单元区域CA的外围布置了两个外围区域PA1和/或PA2,但是取决于示例实施方式,可以在单元区域CA周围设置一个外围区域或者三个或更多个外围区域。
在一些示例实施方式的半导体器件1000中,至少一个多方向沟道晶体管100可以设置在外围区域PA1和/或PA2中。例如,当一些示例实施方式的半导体器件1000是DRAM器件时,具有多方向沟道晶体管结构的读出放大器(SA)晶体管可以设置在外围区域PA1和PA2中。当然,设置在外围区域PA1和/或PA2中的具有多方向沟道晶体管100结构的晶体管不限于SA晶体管。
多方向沟道晶体管100可以具有图1的多方向沟道晶体管100的结构。然而,这不限于此,外围区域PA1和/或PA2的多方向沟道晶体管100可以具有图3A至图5A的多方向沟道晶体管100a至100f当中的至少一个的结构。此外,取决于示例实施方式,外围区域PA1和/或PA2可以如图6或7的多方向沟道晶体管200或300中那样被划分为多个区,并且第一晶体管100-1至第三晶体管100-3当中的任何一个可以布置在每个区中。
图9A至图9F是示出根据本发明构思的一些示例实施方式的制造图1的多方向沟道晶体管的工艺的剖视图,并且可以对应于图2D。先前在上面参照图1至图2D给出的描述被简要地提供或者被省略。
参照图9A,器件隔离区150可以首先形成在衬底101上,以限定有源区Act。衬底101可以是硅体衬底。然而,衬底101不限于硅体衬底。通过经由蚀刻工艺去除衬底101的上部的预定的(或作为选择地给定的)部分以形成沟槽、以及用氧化物膜、氮化物膜、氮氧化物膜等填充该沟槽,可以形成器件隔离区150。例如,器件隔离区150可以形成为浅沟槽隔离(STI)结构。
与器件隔离区150相邻设置的有源区Act可以在从上方观察时在俯视图上具有矩形形状。然而,有源区Act的结构不限于矩形形状。
参照图9B,在形成器件隔离区150之后,硬掩模170可以形成在衬底101的整个上表面上。硬掩模170可以具有多层结构。例如,硬掩模170可以包括非晶碳层(ACL)172、SiON膜174和/或抗反射涂层(ARC)膜176。然而,硬掩模170的多层结构不限于该结构。
参照图9C,在形成硬掩模170之后,光致抗蚀剂(PR)图案180可以形成在硬掩模170上。PR图案180可以通过光刻工艺形成,并且可以包括暴露硬掩模170的预定的(或作为选择地给定的)部分的开口区域OP。开口区域OP可以对应于稍后将形成在有源区Act中和器件隔离区150中的凹陷Re的部分。取决于示例实施方式,凹陷Re可以不形成在器件隔离区150中。在这种情况下,开口区域OP可以不形成在与器件隔离区150对应的部分处。
例如,开口区域OP可以具有在一个方向上延伸的形状,并且可以具有在相对于稍后将形成的栅线110的斜交方向上延伸的形状。此外,取决于示例实施方式,开口区域OP可以具有与图3A至图3D中的多方向沟道晶体管100a至100d的凹陷Re1至Re4对应的形状。此外,开口区域OP可以具有与图5A的多方向沟道晶体管100f的凹陷Re5对应、或者与图6和图7的多方向沟道晶体管200和300的第二晶体管100-2的凹陷Rep对应的形状。当如在图6和图7的多方向沟道晶体管200和300中那样晶体管100-1至100-3一起同时形成时,PR图案180的开口区域OP可以包括与晶体管100-1至100-3中的每个凹陷对应的形状。
参照图9D,通过经由使用PR图案180和硬掩模170作为蚀刻掩模的干蚀刻而蚀刻有源区Act和器件隔离区150,可以形成凹陷Re。凹陷Re可以包括有源区Act上的有源区凹陷Rea和/或器件隔离区150上的隔离区凹陷Rei。取决于示例实施方式,如上所述,可以不形成隔离区凹陷Rei。此外,取决于示例实施方式,通过改变蚀刻工艺的工艺条件或硬掩模170的材料,隔离区凹陷Rei可以形成得比有源区凹陷Rea深。当凹陷形成为这种结构时,稍后可以实现如图4所示的一些示例实施方式的多方向沟道晶体管100e的结构。
通过凹陷Re的形成,鳍Fn可以形成为在有源区Act中向上突出。鳍Fn可以具有在与凹陷Re相同的方向上延伸的形状。此外,取决于凹陷Re的形状,鳍Fn可以形成为如图3A至图3D的多方向沟道晶体管100a至100d中的各种形状。
参照图9E,在形成凹陷Re之后,覆盖有源区Act和器件隔离区150的上表面的电介质膜112可以被形成。电介质膜112可以包括例如高k电介质材料。电介质膜112可以通过各种沉积工艺形成,诸如化学气相沉积(CVD)、低压CVD(LPCVD)、常压CVD(APCVD)、低温CVD(LTCVD)、等离子体增强CVD(PECVD)、原子层沉积(ALD)和物理气相沉积(PVD)等。
参照图9F,在形成电介质膜112之后,用于栅线的多层可以形成在电介质膜112上。例如,用于栅线的多层可以包括多晶硅膜113、阻挡金属膜115、W膜117和/或SiN膜119。然而,用于栅线的多层的结构不限于以上结构。例如,取决于晶体管的操作特性,用于栅线的多层可以包括各种性质的材料膜。
此后,栅线110可以通过图案化用于栅线的多层而形成。栅线110可以形成为在第二方向(Y方向)上延伸。如上所述,凹陷Re的延伸方向可以对应于相对于栅线110延伸的第二方向(Y方向)的斜交方向。或者,设置在栅线110下方的电介质膜112可以一起被图案化。
在形成栅线110之后,用于形成间隔物的材料膜可以形成在包括栅线110的衬底101的整个表面上,并且栅线110上的材料膜和衬底101上的材料膜可以通过蚀刻工艺被蚀刻,以在栅线110的侧面上形成间隔物114。或者,如上所述,因为用于形成间隔物的材料膜在凹陷Re的部分中形成得较厚,所以间隔物114可以保留在凹陷Re的部分中。
虽然已经参照本发明构思的一些示例实施方式具体显示并描述了本发明构思,但是将理解,可以在其中进行在形式和细节上的各种改变而不背离所附权利要求的精神和范围。
本申请要求享有2019年3月19日在韩国知识产权局提交的韩国专利申请第10-2019-0031473号的权益,其公开通过引用全文在此合并。
Claims (20)
1.一种多方向沟道晶体管,包括:
至少一个鳍,在衬底上的有源区上并且与在第一方向上延伸的凹陷相邻设置;
栅线,覆盖所述至少一个鳍和所述凹陷的至少一部分,并且在交叉所述第一方向的第二方向上延伸;
源/漏区,在所述栅线的两侧的所述有源区中;以及
沟道区,在所述源/漏区之间在所述栅线下方的所述有源区中,
其中所述第一方向是相对于所述第二方向的斜交方向,以及
所述栅线下方的电介质膜在所述至少一个鳍和所述凹陷两者上具有基本相同的厚度。
2.根据权利要求1所述的多方向沟道晶体管,
其中所述鳍仅在所述栅线下方,或者所述鳍延伸到所述栅线的两侧之外。
3.根据权利要求1所述的多方向沟道晶体管,其中,
接触形成在所述源/漏区上,以及
所述鳍延伸到所述接触。
4.根据权利要求3所述的多方向沟道晶体管,其中,
所述接触的下表面比所述凹陷的底表面深,以及
所述鳍与所述接触的侧表面接触。
5.根据权利要求1所述的多方向沟道晶体管,其中,
所述有源区与器件隔离区相邻设置,以及
所述鳍在所述第一方向上延伸遍及整个所述有源区。
6.根据权利要求5所述的多方向沟道晶体管,其中,
所述鳍延伸到所述器件隔离区。
7.根据权利要求1所述的多方向沟道晶体管,其中,
所述有源区与器件隔离区相邻设置,
所述凹陷包括形成在所述有源区上的有源区凹陷和形成在所述器件隔离区上的隔离区凹陷,以及
所述隔离区凹陷比所述有源区凹陷深。
8.根据权利要求1所述的多方向沟道晶体管,其中,
所述第一方向相对于所述第二方向具有30°至70°的角度。
9.根据权利要求1所述的多方向沟道晶体管,其中,
所述多方向沟道晶体管的沟道具有取决于所述凹陷的方向确定的方向。
10.一种多方向沟道晶体管,包括:
第一晶体管,包括:
至少一个第一鳍,在衬底上的第一有源区上,并且与在第一方向上延伸的第一凹陷相邻设置,和
第一栅线,在交叉所述第一方向的第二方向上延伸,并且覆盖所述至少一个第一鳍和所述第一凹陷的至少一部分;以及
第二晶体管,包括:
至少一个第二鳍,在所述衬底上的第二有源区上,并且与在第三方向上延伸的第二凹陷相邻设置,和
第二栅线,在第四方向上延伸,并且覆盖所述至少一个第二鳍和所述第二凹陷的至少一部分,
其中所述第一方向是与所述第二方向垂直的方向,所述第三方向是相对于所述第四方向的斜交方向。
11.根据权利要求10所述的多方向沟道晶体管,其中,
所述第一栅线下方的第一电介质膜在所述至少一个第一鳍和所述第一凹陷两者上具有基本相同的厚度,以及
所述第二栅线下方的第二电介质膜在所述至少一个第二鳍和所述第二凹陷两者上具有基本相同的厚度。
12.根据权利要求11所述的多方向沟道晶体管,其中所述第一电介质膜和所述第二电介质膜具有基本相同的厚度。
13.根据权利要求10所述的多方向沟道晶体管,其中,
所述第一有源区与第一器件隔离区相邻设置,所述第二有源区与第二器件隔离区相邻设置,
第一接触在所述第一晶体管的第一源/漏区上,第二接触在所述第二晶体管的第二源/漏区上,以及
所述第一鳍在所述第一有源区中,所述第二鳍在所述第二有源区中。
14.根据权利要求13所述的多方向沟道晶体管,其中,
所述第一凹陷包括多个第一凹陷,
所述第二凹陷包括多个第二凹陷,
所述第一接触重叠所述多个第一凹陷,
所述第二接触重叠所述多个第二凹陷,
所述第一接触的底表面比所述第一凹陷的底表面深,
所述第二接触的底表面比所述第二凹陷的底表面深,
所述至少一个第一鳍接触所述第一接触的侧表面,以及
所述至少一个第二鳍接触所述第二接触的侧表面。
15.根据权利要求13所述的多方向沟道晶体管,其中,
所述第一凹陷延伸到所述第一有源区之外的所述第一器件隔离区,和/或
所述第二凹陷延伸到所述第二有源区之外的所述第二器件隔离区。
16.根据权利要求13所述的多方向沟道晶体管,其中,
所述第一凹陷包括所述第一有源区上的第一有源区凹陷和所述第一器件隔离区上的第一隔离区凹陷,
所述第二凹陷包括所述第二有源区上的第二有源区凹陷和所述第二器件隔离区上的第二隔离区凹陷,以及
所述第一隔离区凹陷比所述第一有源区凹陷深,所述第二隔离区凹陷比所述第二有源区凹陷深。
17.根据权利要求10所述的多方向沟道晶体管,还包括:
第三晶体管,具有第三栅线和第三凹陷,所述第三栅线在所述衬底上的第三有源区上在第五方向上延伸,所述第三凹陷在所述第三栅线下方在所述第三有源区上在所述第五方向上延伸。
18.一种半导体器件,包括:
衬底,包括单元区和外围区,所述单元区具有多个单元,所述外围区与所述单元区相邻设置,所述外围区包括至少一个第一晶体管,其中,
所述至少一个第一晶体管包括:
至少一个第一鳍,形成在所述外围区上的第一有源区上,并且与在第一方向上延伸的第一凹陷相邻设置,和
第一栅线,在交叉所述第一方向的第二方向上延伸,并且覆盖所述至少一个第一鳍和所述第一凹陷的至少一部分,
在所述第一有源区上,所述第一方向与所述第二方向斜交,以及
所述第一栅线下方的电介质膜在所述至少一个第一鳍和所述第一凹陷两者上具有基本相同的厚度。
19.根据权利要求18所述的半导体器件,还包括:
第二晶体管,包括:
至少一个第二鳍,在所述外围区上的第二有源区上,并且与在第三方向上延伸的第二凹陷相邻设置,以及
第二栅线,在第四方向上延伸,并且覆盖所述第二凹陷的一部分和所述至少一个第二鳍的一部分,其中,
所述第三方向垂直于所述第四方向。
20.根据权利要求18所述的半导体器件,
其中所述半导体器件包括DRAM器件或闪速存储器件。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05110083A (ja) * | 1991-10-15 | 1993-04-30 | Oki Electric Ind Co Ltd | 電界効果トランジスタ |
US20050239254A1 (en) * | 2004-04-24 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-plannar and FinFET-like transistors on bulk silicon |
CN1750269A (zh) * | 2004-06-28 | 2006-03-22 | 三星电子株式会社 | 包括多-沟道鳍形场效应晶体管的半导体器件及其制造方法 |
US20130264621A1 (en) * | 2012-04-04 | 2013-10-10 | Elpida Memory, Inc. | Semiconductor device having fin-shaped field effect transistor and manufacturing method thereof |
CN105960710A (zh) * | 2013-12-23 | 2016-09-21 | 英特尔公司 | 用于迁移率改进的n-mos的拉伸的源极漏极iii-v族晶体管 |
CN107230728A (zh) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | 半导体器件、finfet器件及其形成方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6967351B2 (en) * | 2001-12-04 | 2005-11-22 | International Business Machines Corporation | Finfet SRAM cell using low mobility plane for cell stability and method for forming |
DE10241171A1 (de) * | 2002-09-05 | 2004-03-18 | Infineon Technologies Ag | Wort- und Bitleitungsanordnung für einen FINFET-Halbleiterspeicher |
US20060255412A1 (en) | 2005-05-13 | 2006-11-16 | Nirmal Ramaswamy | Enhanced access devices using selective epitaxial silicon over the channel region during the formation of a semiconductor device and systems including same |
US8466490B2 (en) | 2005-07-01 | 2013-06-18 | Synopsys, Inc. | Enhanced segmented channel MOS transistor with multi layer regions |
KR100673144B1 (ko) | 2005-07-15 | 2007-01-22 | 주식회사 하이닉스반도체 | 반도체소자의 트랜지스터 및 그 형성방법 |
KR100908522B1 (ko) | 2007-06-28 | 2009-07-20 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US8013367B2 (en) | 2007-11-08 | 2011-09-06 | International Business Machines Corporation | Structure and method for compact long-channel FETs |
KR101205037B1 (ko) | 2011-02-28 | 2012-11-26 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 형성방법 |
KR102059118B1 (ko) * | 2013-10-28 | 2019-12-24 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 형성 방법 |
US9634122B2 (en) | 2014-03-12 | 2017-04-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device boost by quasi-FinFET |
US9418896B2 (en) * | 2014-11-12 | 2016-08-16 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
KR102283813B1 (ko) * | 2014-12-04 | 2021-08-03 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR20180075870A (ko) * | 2016-12-27 | 2018-07-05 | 에스케이하이닉스 주식회사 | 더미 워드라인들을 갖는 반도체 메모리 장치 |
-
2019
- 2019-03-19 KR KR1020190031473A patent/KR20200111582A/ko not_active Application Discontinuation
- 2019-08-21 US US16/546,506 patent/US10930740B2/en active Active
- 2019-10-17 CN CN201910987953.4A patent/CN111725314B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05110083A (ja) * | 1991-10-15 | 1993-04-30 | Oki Electric Ind Co Ltd | 電界効果トランジスタ |
US20050239254A1 (en) * | 2004-04-24 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-plannar and FinFET-like transistors on bulk silicon |
CN1750269A (zh) * | 2004-06-28 | 2006-03-22 | 三星电子株式会社 | 包括多-沟道鳍形场效应晶体管的半导体器件及其制造方法 |
US20130264621A1 (en) * | 2012-04-04 | 2013-10-10 | Elpida Memory, Inc. | Semiconductor device having fin-shaped field effect transistor and manufacturing method thereof |
CN105960710A (zh) * | 2013-12-23 | 2016-09-21 | 英特尔公司 | 用于迁移率改进的n-mos的拉伸的源极漏极iii-v族晶体管 |
CN107230728A (zh) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | 半导体器件、finfet器件及其形成方法 |
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US10930740B2 (en) | 2021-02-23 |
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CN111725314B (zh) | 2024-02-23 |
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