CN111725181A - Semiconductor combination structure, control method and electronic product - Google Patents
Semiconductor combination structure, control method and electronic product Download PDFInfo
- Publication number
- CN111725181A CN111725181A CN202010550615.7A CN202010550615A CN111725181A CN 111725181 A CN111725181 A CN 111725181A CN 202010550615 A CN202010550615 A CN 202010550615A CN 111725181 A CN111725181 A CN 111725181A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- positioning
- chip
- positioning film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
The embodiment of the application discloses a semiconductor combination structure, a control method and an electronic product. According to the technical scheme provided by the embodiment of the application, the positioning film with the positioning holes is arranged on the lead frame, and the positioning holes correspond to the solder balls, so that when the solder balls are welded and connected to the lead frame, the solder balls are limited in the range of the positioning holes, the condition that the connection between the solder balls and the lead frame is poor due to the height difference between the lead frame and a chip is reduced, meanwhile, the shape of the solder balls can be improved through the positioning holes, and the product quality is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of semiconductor packaging, in particular to a semiconductor combination structure, a control method and an electronic product.
Background
The semiconductor is a material with the conductivity between a conductor and a non-conductor, and the semiconductor element belongs to a solid element according to the characteristics of the semiconductor material, and the volume of the semiconductor element can be reduced to a small size, so that the power consumption is low, the integration level is high, and the semiconductor element is widely applied to the technical field of electronics.
In the semiconductor device, bonding of a Lead Frame (LF) and a chip (die) is generally performed by a tin (solder) ball, but due to a height difference between the Lead Frame and the chip, poor connection between the solder ball and the Lead Frame may occur, which affects product quality.
Disclosure of Invention
Embodiments of the present application provide a semiconductor bonding structure, a control method, and an electronic product, which can solve the above problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
on the one hand, the semiconductor combination structure comprises a lead frame, a positioning film and a chip, wherein the chip is connected with an internal input/output bonding point through a copper column, the end part of the copper column is connected with a solder ball, the positioning film is coated on the lead frame, a positioning hole is formed in the position, corresponding to the solder ball, of the positioning film, and the solder ball is connected to the lead frame through the positioning hole.
As a preferable technical solution of the semiconductor bonding structure, the positioning film is a photoresist coated on the lead frame.
As a preferable technical solution of the semiconductor bonding structure, the positioning film is provided with positioning holes by exposure and development.
As a preferable technical solution of the semiconductor bonding structure, the solder ball is connected to the lead frame at the positioning hole by means of thermocompression bonding.
On the other hand, the semiconductor combination control method is used for connecting a chip and a lead frame, wherein the chip is connected with an internal input/output bonding point through a copper column, and a solder ball is connected to the end part of the copper column;
the method comprises the following steps:
s1, coating a positioning film on the lead frame;
s2, arranging a positioning hole at the position of the positioning film corresponding to the solder ball on the chip;
and S3, connecting the solder balls to the lead frame at the positioning holes.
As a preferable technical solution of the semiconductor bonding control method, the positioning film is formed by coating a positive photoresist on the lead frame by a spin coating method.
As a preferable technical solution of the semiconductor bonding control method, step S2 specifically includes:
s21, exposing the positions of the positioning films corresponding to the solder balls on the chip;
s22, coating a developing solution on the positioning film to remove the exposed part of the positioning film and form a positioning hole;
and S23, baking the lead frame and the positioning film.
As a preferable technical solution of the semiconductor bonding control method, the exposing at the position where the positioning film corresponds to the solder ball on the chip includes:
s211, aligning a mask to the lead frame, wherein the position of the mask, corresponding to the solder ball on the chip, is set as a light-transmitting area;
and S212, exposing the positioning film in the light-transmitting area.
In another aspect, an electronic product having the semiconductor bonding structure is provided.
In still another aspect, an electronic product is provided, which includes a semiconductor device, and the semiconductor device connects a chip and a lead frame by using the semiconductor bonding control method as described above.
The invention has the beneficial effects that: according to the scheme, the positioning film with the positioning holes is arranged on the lead frame, the positioning holes correspond to the solder balls, so that when the solder balls are connected to the lead frame in a welding mode, the solder balls are limited within the range of the positioning holes, the condition that the connection between the solder balls and the lead frame is poor due to the height difference between the lead frame and a chip is reduced, meanwhile, the shape of the solder balls can be improved through the positioning holes, and the product quality is improved.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
FIG. 1 is a schematic structural diagram of a semiconductor bonding structure according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a process of coating the positioning film on the lead frame according to the embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a forming process of a positioning hole according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a connection process between the chip and the lead frame according to the embodiment of the present invention.
Reference numerals: 1. a lead frame; 2. positioning the film; 3. a chip; 4. a copper pillar; 5. tin balls; 6. and (7) positioning the holes.
Detailed Description
In order to make the technical problems solved, technical solutions adopted, and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention are described in further detail below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
As shown in fig. 1, the present embodiment provides a semiconductor bonding structure including a lead frame 1 (LF), a positioning film 2(film), and a chip 3 (DIE). Wherein, the chip 3 is internally provided with an input/output bonding point (or pin, PAD), and an external device can interact with the chip 3 through the connection with the bonding point. Further, the chip 3 is led out of the internal input/output bonding point through a copper pillar 4(copper pillar), and a solder ball 5(solder) is soldered to an end of the copper pillar 4 away from the chip 3 for bonding with the lead frame 1, so that the input/output bonding point of the chip 3 is led out through the lead frame 1.
Preferably, the copper pillar 4 provided in this embodiment is a cylinder with a diameter and a height of 30 to 80 μm (e.g. 45 μm), and the solder ball 5 soldered on the top of the copper pillar 4 is dome-shaped.
Specifically, a positioning film 2 is coated on the upper surface of the lead frame 1, a positioning hole 6 is formed in the position, corresponding to the connection position of the solder ball 5 and the lead frame 1, of the positioning film 2, and the positioning hole 6 is a through hole communicated with two sides of the positioning film 2. Furthermore, the solder ball 5 is connected to the lead frame 1 at the positioning hole 6, the solder ball 5 is limited within the range of the positioning hole 6 by the positioning film 2, the situation that the connection between the solder ball 5 and the lead frame 1 is poor due to the height difference between the lead frame 1 and the chip 3 is reduced, meanwhile, the shape of the solder ball 5 can be improved through the positioning hole 6, and the product quality is improved. And adjacent solder balls 5 are blocked by the positioning film 2, so that the short circuit problem of different bonding points of the chip 3 can be reduced.
Further, the positioning film 2 provided in the present embodiment is formed of a photoresist coated on the lead frame 1, and the positioning film 2 is provided with the positioning holes 6 by means of exposure development. The photoresist is a resist film material whose solubility changes by irradiation or radiation of light sources such as ultraviolet light, excimer laser, electron beam, ion beam, and X-ray.
Specifically, the photoresist used in this embodiment is a positive photoresist, and the portion of the positive photoresist irradiated with light is soluble in the developing solution, while the portion not irradiated with light is not (or hardly) soluble in the developing solution. The positioning film 2 can be subjected to exposure and development at a position where the positioning hole 6 needs to be provided, thereby dissolving the positioning film 2 to form the positioning hole 6.
Illustratively, the positioning hole 6 in this embodiment has a square shape. It should be noted that the knot shape of the positioning hole 6 is not limited to the square shape described in the above embodiments, and in other embodiments, a circular shape, a trapezoidal shape, an irregular shape, or the like may be adopted.
Specifically, when the solder ball 5 is connected to the lead frame 1, the solder ball 5 is soldered to the lead frame 1 at the positioning hole 6 by a thermocompression bonding method. The chip 3 is clamped or sucked by a hot-pressing head, the hot-pressing head is heated to 300-400 ℃, the solder ball 5 is heated and melted, and then pressure towards the lead frame 1 is applied to the chip 3, so that the solder ball 5 is welded on the connection point of the lead frame 1.
Meanwhile, the embodiment also provides a semiconductor combination control method, which is used for connecting the chip 3 and the lead frame 1, wherein the chip 3 is connected with an internal input/output bonding point through a copper column 4, and the end part of the copper column 4 is connected with a solder ball 5. With reference to fig. 1 to 4, the semiconductor bonding control method specifically includes the following steps:
and S1, coating a positioning film 2 on the lead frame 1.
In the present embodiment, the positioning film 2 is formed by coating a positive photoresist on the lead frame 1 by a spin coating method. Before coating the positive photoresist, cleaning the lead frame 1 and spin-drying the lead frame 1 to remove impurities on the surface of the lead frame 1.
Specifically, referring to fig. 2, a positive photoresist is dripped on the lead frame 1 (the lead frame 1 is fixed by a vacuum negative pressure device), the lead frame 1 is rotated at a high speed, the positive photoresist flows to the edge of the lead frame 1 under the action of centrifugal force and is uniformly distributed on the lead frame 1, and the positive photoresist on the lead frame 1 forms a positioning film 2, so that the positioning film 2 is pasted on the lead frame 1. The rotation speed of the lead frame 1 can be determined according to the viscosity of the positive photoresist and the desired thickness of the positioning film 2.
In order to ensure the consistency of the exposure and development time of the positioning films 2 on different lead frames 1, the thickness uniformity and the thickness consistency of the different positioning films 2 are ensured to be within +/-4-8 nm.
Preferably, after the application of the positive photoresist is completed, the lead frame 1 is subjected to a soft baking operation to evaporate the solvent in the positive photoresist and make the applied positive photoresist thinner. Although the liquid photoresist becomes a solid film (positioning film 2) after spinning at high speed, 10-30% of solvent still exists, and dust is easily polluted. By baking at a higher temperature, the solvent is volatilized from the positive photoresist, thereby reducing contamination by dust, and also reducing film stress due to high-speed rotation, thereby improving the adhesion of the positive photoresist to the lead frame 1.
And S2, arranging positioning holes 6 at the positions of the positioning films 2 corresponding to the solder balls 5 on the chip 3.
Referring to fig. 3, after the positioning film 2 is coated on the lead frame 1, the positioning film 2 is dissolved by means of exposure and development to form the positioning holes 6.
Specifically, step S2 specifically includes:
and S21, exposing the position of the positioning film 2 corresponding to the solder ball 5 on the chip 3.
Since the photoresist used in this embodiment is a positive photoresist, and the exposed position is the position that needs to be dissolved, the position of the positioning film 2 corresponding to the solder ball 5 on the chip 3 is exposed.
Specifically, the exposing at the position of the positioning film 2 corresponding to the solder ball 5 on the chip 3 includes:
and S211, aligning the mask plate to the lead frame 1.
In this embodiment, the position of the mask corresponding to the solder ball 5 on the chip 3 is set as a light-transmitting region (bright field or exposed region). It is understood that the shape of the light-transmitting area is set according to the shape of the positioning hole 6. Furthermore, due to the diffraction effect of light, the size of the positioning hole 6 on the positioning film 2 can be increased by using the combination of the positive photoresist and the bright-field mask, so that the size of a light-transmitting area on the mask can be reduced when the mask is manufactured.
Specifically, the alignment method of the reticle and the lead frame 1 may be zone plate alignment, interference intensity alignment, laser heterodyne interference, moire fringe alignment, and the like. The mask is aligned with the lead frame 1, so that the light-transmitting area on the mask is aligned with the connecting point of the counter-rotating lead frame 1, which is required to be connected with the solder ball 5.
S212, exposing the positioning film 2 in the light-transmitting area.
Specifically, the positioning film 2 is irradiated from above the mask by using light sources such as ultraviolet light, excimer laser, electron beam, ion beam, and X-ray, so that the irradiated area of the positioning film is chemically changed, the solubility of the partial area to the developing solution is greater than that of the non-irradiated area, and the mask pattern can be transferred by using the different solubilities of photosensitive and non-photosensitive photoresist to the developing solution.
S22, coating a developing solution on the positioning film 2 to remove the exposed part of the positioning film 2 and form a positioning hole 6.
Specifically, after the exposure process of the positioning film 2 is finished, the developing solution is coated on the positioning film 2, so that the exposed part of the positioning film 2 is dissolved in the developing solution, and the dissolved part of the positioning film 2 forms the positioning hole 6.
S23, baking the lead frame 1 and the positioning film 2.
After the development process of the positioning film 2 is completed, the positioning holes 6 on the positioning film 2 are basically determined, but the positive photoresist needs to be stabilized by baking. Specifically, the residual solvent (developer and water) in the positioning film 2 is removed by high-temperature treatment, so that the adhesion of the positioning film 2 to the surface of the lead frame 1 is enhanced, and the corrosion resistance and hardness of the positioning film 2 are improved.
And S3, connecting the solder balls 5 to the lead frame 1 at the positioning holes 6.
Specifically, referring to fig. 4, a hot-pressing head is used to clamp or suck a chip 3, the hot-pressing head is moved to align the chip 3 with the lead frame 1, so that the solder balls 5 on the chip 3 are aligned with the positioning holes 6 one by one, the chip 3 is heated by the hot-pressing head to melt the solder balls 5, the chip 3 is moved toward the lead frame 1 and is pressed against the chip 3, and the solder balls 5 are bonded (humpjoin) with the connection points of the lead frame 1 at the positioning holes 6, thereby forming the semiconductor bonding structure shown in fig. 1. The solder ball 5 is limited in the range of the positioning hole 6, the condition that the solder ball 5 is not connected with the lead frame 1 well due to the height difference between the lead frame 1 and the chip 3 is reduced, meanwhile, the shape of the solder ball 5 can be improved through the positioning hole 6, and the product quality is improved.
Meanwhile, the embodiment of the invention also provides an electronic product which is provided with the semiconductor combination structure.
The embodiment of the invention also provides an electronic product which comprises a semiconductor device, wherein the semiconductor device is used for connecting the chip 3 and the lead frame 1 by adopting the semiconductor combination control method.
In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are used in an orientation or positional relationship merely for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, configuration, and operation in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. The semiconductor combination structure is characterized by comprising a lead frame, a positioning film and a chip, wherein the chip is connected with an internal input/output bonding point through a copper column, the end part of the copper column is connected with a solder ball, the positioning film is coated on the lead frame, a positioning hole is formed in the position, corresponding to the solder ball, of the positioning film, and the solder ball is connected to the lead frame at the positioning hole.
2. The semiconductor bonding structure of claim 1, wherein the positioning film is a photoresist coated on the lead frame.
3. The semiconductor bonding structure of claim 2, wherein the positioning film is provided with positioning holes by exposure and development.
4. The semiconductor bonding structure of claim 1, wherein the solder ball is attached to a lead frame at the positioning hole by thermocompression bonding.
5. A semiconductor combination control method is characterized in that the method is used for connecting a chip and a lead frame, the chip is connected with an internal input/output bonding point through a copper column, and the end part of the copper column is connected with a solder ball;
the method comprises the following steps:
s1, coating a positioning film on the lead frame;
s2, arranging a positioning hole at the position of the positioning film corresponding to the solder ball on the chip;
and S3, connecting the solder balls to the lead frame at the positioning holes.
6. The semiconductor bonding control method according to claim 5, wherein the positioning film is formed by coating a positive photoresist on the lead frame by a spin coating method.
7. The semiconductor bonding control method according to claim 5, wherein the step S2 specifically comprises:
s21, exposing the positions of the positioning films corresponding to the solder balls on the chip;
s22, coating a developing solution on the positioning film to remove the exposed part of the positioning film and form a positioning hole;
and S23, baking the lead frame and the positioning film.
8. The semiconductor bonding control method according to claim 7, wherein said exposing at the position where the positioning film corresponds to the solder ball on the chip comprises:
s211, aligning a mask to the lead frame, wherein the position of the mask, corresponding to the solder ball on the chip, is set as a light-transmitting area;
and S212, exposing the positioning film in the light-transmitting area.
9. An electronic product having the semiconductor bonding structure according to any one of claims 1 to 4.
10. An electronic product comprising a semiconductor device, wherein the semiconductor device connects a chip and a lead frame by the semiconductor bonding control method according to any one of claims 5 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010550615.7A CN111725181A (en) | 2020-06-16 | 2020-06-16 | Semiconductor combination structure, control method and electronic product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010550615.7A CN111725181A (en) | 2020-06-16 | 2020-06-16 | Semiconductor combination structure, control method and electronic product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111725181A true CN111725181A (en) | 2020-09-29 |
Family
ID=72567001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010550615.7A Pending CN111725181A (en) | 2020-06-16 | 2020-06-16 | Semiconductor combination structure, control method and electronic product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111725181A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112992692A (en) * | 2021-05-19 | 2021-06-18 | 佛山市联动科技股份有限公司 | Method and system for full-automatic cutting of lead |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI297934B (en) * | 2004-10-22 | 2008-06-11 | Richtek Technology Corp | Package structure module of bump posited type lead frame |
| CN104199209A (en) * | 2014-07-28 | 2014-12-10 | 京东方科技集团股份有限公司 | Mask plate, manufacturing method thereof and manufacturing method of target graph |
| CN104282637A (en) * | 2014-10-31 | 2015-01-14 | 南通富士通微电子股份有限公司 | Flip chip semiconductor encapsulation structure |
| CN104345544A (en) * | 2013-07-31 | 2015-02-11 | 北京京东方光电科技有限公司 | Mask plate |
| CN106206479A (en) * | 2015-03-31 | 2016-12-07 | 南茂科技股份有限公司 | quad flat non-leaded package structure and lead frame structure |
| CN206133181U (en) * | 2016-11-01 | 2017-04-26 | 合肥鑫晟光电科技有限公司 | Mask plate |
| US20180096860A1 (en) * | 2016-09-30 | 2018-04-05 | Texas Instruments Incorporated | Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer |
| US20180190608A1 (en) * | 2016-12-30 | 2018-07-05 | Texas Instruments Incorporated | Packaged semiconductor device with a reflow wall |
-
2020
- 2020-06-16 CN CN202010550615.7A patent/CN111725181A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI297934B (en) * | 2004-10-22 | 2008-06-11 | Richtek Technology Corp | Package structure module of bump posited type lead frame |
| CN104345544A (en) * | 2013-07-31 | 2015-02-11 | 北京京东方光电科技有限公司 | Mask plate |
| CN104199209A (en) * | 2014-07-28 | 2014-12-10 | 京东方科技集团股份有限公司 | Mask plate, manufacturing method thereof and manufacturing method of target graph |
| CN104282637A (en) * | 2014-10-31 | 2015-01-14 | 南通富士通微电子股份有限公司 | Flip chip semiconductor encapsulation structure |
| CN106206479A (en) * | 2015-03-31 | 2016-12-07 | 南茂科技股份有限公司 | quad flat non-leaded package structure and lead frame structure |
| US20180096860A1 (en) * | 2016-09-30 | 2018-04-05 | Texas Instruments Incorporated | Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer |
| CN206133181U (en) * | 2016-11-01 | 2017-04-26 | 合肥鑫晟光电科技有限公司 | Mask plate |
| US20180190608A1 (en) * | 2016-12-30 | 2018-07-05 | Texas Instruments Incorporated | Packaged semiconductor device with a reflow wall |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112992692A (en) * | 2021-05-19 | 2021-06-18 | 佛山市联动科技股份有限公司 | Method and system for full-automatic cutting of lead |
| CN112992692B (en) * | 2021-05-19 | 2021-07-20 | 佛山市联动科技股份有限公司 | Method and system for full-automatic cutting of lead |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI474416B (en) | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing | |
| US20060223313A1 (en) | Copper interconnect post for connecting a semiconductor chip to a substrate and method of fabricating the same | |
| US11156351B2 (en) | Backlight module and method of manufacturing same | |
| WO2000010369A1 (en) | Method of forming solder bump, method of mounting electronic device, and mounting structure of electronic device | |
| KR20020006468A (en) | Method for forming a solder bump, and process for fabricating a semiconductor device | |
| KR20010082601A (en) | Method of forming bumps, electronic components, and solder paste | |
| JPH1116933A (en) | Manufacture of circuit board having metallic bump and semiconductor chip package using this circuit board | |
| JP2009164310A (en) | Electronic parts repair equipment and electronic parts repairing method | |
| JP2013140957A (en) | Printed circuit substrate and manufacturing method of the same | |
| CN111725181A (en) | Semiconductor combination structure, control method and electronic product | |
| JP4477213B2 (en) | Circuit board and circuit board manufacturing method | |
| JP2006210937A (en) | Method for forming solder bump | |
| TW201810454A (en) | Manufacturing method of semiconductor package | |
| CN111668125A (en) | Wafer tin ball printing process | |
| US20060071303A1 (en) | Film substrate of a semiconductor package and a manufacturing method | |
| JP2006173654A (en) | Method for forming solder bump | |
| JP4181236B2 (en) | Intaglio printing method, bump forming method, wiring pattern forming method, and bump and wiring pattern forming method | |
| WO2017179704A1 (en) | Method for forming solder bump | |
| TWI461123B (en) | Membrane substrate and method for making the same | |
| JP3955394B2 (en) | Manufacturing method of spherical semiconductor device | |
| JPH11274209A (en) | Formation of bump electrode | |
| JP4457532B2 (en) | Lead frame manufacturing method | |
| KR100246585B1 (en) | B.g.a semiconductor lead frame and fabrication method of it | |
| JP4507473B2 (en) | Lead frame manufacturing method | |
| KR101884431B1 (en) | Printed circuit board and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200929 |