1297934 九、發明說明： 【發明所屬之技術領域】 ;=ί關於一種導線架封裝結構，特別是 一種有關於凸塊定位式導線 【先前技術】 著多功能電子產品的大量需求盘並 展，先進商用半導體電子元件封裝已“ 以及半導體電子工程的發 構、受限制#電性特性的形式，^簡化製' 裝製程、大尺寸結 度、強化m騎雜及高導散雛之I :構2微梳、高積集密 為將晶片之凸塊直接與預鍍銀之導線架架封裝技術多 號聯結之目的，而這樣的晶片合併冓以達到電性訊 說，將凸塊接合至導線架的過程經常缺3釭2:!:22。舉例來 題’凸塊的潤（沾）祕與流動性健可接合的問 =除造成晶片在電性上之問題，對於整體封二 點的ί裝結目:此極需提種可以解決上述缺 【發明内容】 本發明所欲解決之技術問題係包含因凸塊接合定位生 構内電性聯結性與整體封裝可靠性降低，以及良率下__，成封裝… 本發明所欲解決之技術問題更包含因凸塊的潤（沾）渴付盘 =塊的對位或定位不良所造成晶片在電性上及整體封裝結構性= 本發明解決_之技術手段储供-凸塊定位轉線架半導體封裝結 5 1297934 凸塊晶片合併導線架封裝所造成的 立 線架封裝結構，此結構較傳統凸塊合併導 可降健體封裝製程因晶片偏j j架 2導線架之接合性及整體封裝結構 整體封裝體尺寸等，其應用範圍廣泛j减且了控制调即凸塊尺寸及 -晶實施例中，本發明提供—麵裝結構，此封裝結構包含 體凸塊，'^軸淑穴以容納導 含一 ，中’本發明提供另-種封裝結構，此封裝結構包 體^線架歡位膜片位於該導線架上並具有開孔以容納il 且有i tt明^2施例中’本發明提供另-種封裝結構’此封裝結構 以線架與Γ定位，。該晶片具有導體凸塊，該導線架具有 位於今塊，该晶片藉由導體凸塊與該導線架結合，該定位膜片 ;Λ木上並具有開孔以容納導體凸塊，每一開孔重疊於每一孔穴。 组句出一種封裝結構之導線架模組’該封裝結構之導線架模 納- L 與一定f膜片1該導線架包含引腳，該引腳具有孔穴以容 片朽^體凸塊，該晶片藉由該導體凸塊與該導線架結合，該定位膜 片位於该^線架上並$有開孔以容納導體凸塊，每一開孔重疊於每一孔穴： 明與先前技術之功效，由於本發明提出一凸塊定位式導線架半 定朽二構，细在導翁引腳上預侧孔穴之方式以及外加特殊設計之 導線架上，做為凸塊座落與定位之用，可錢提高晶片凸塊 二Ϊ木間的接合定位特性、晶片可靠度及使用壽命及整體封裝體可靠 性，因此可獲得先前技術所欠缺的功效。 衣篮J罪 上述有關發明的内容及以下的實施方式詳細說明為範例並非限制。其 脫離本發明之精神的等效改變或修飾均應包含在的本發明的專利範圍 1297934 之内。 【實施方式】 件。構與元件並不包含完整之結構與元 元件，。來實施，在此僅提及瞭解本發明所需之 是;極簡化的格a而詳細的說明。必需說明的是圖示 俯視ϊί 的俯棚。在此封裝結構⑽的 含一灌舰、、曰人你電材^ 與一晶片102。此保護介電材料101包 第四八至四3齡麵示三種封裝結構的實施例。 裝結結構觸第—實施例之底視圖。在此封 : 第貫施例之底視圖中，顯示一導線架103與一定位膜片1〇4 ΐ 電ϊϊ 103包含引腳1G5以及一晶片附著基座106。 與ΐ二Λ圖中封裝結構⑽第—實施例的左^局部=圖3 ^實t例中’ Ba片102透過導體凸塊⑽與導線架1〇3結合 具有孔穴11〇 ’而此孔穴11〇係用於凸塊⑽的定位%== fit 4置f布則取決於晶片102上之凸塊108的數量與位置分布。舉 你來=，母一 V線架103之引腳105上可形成一孔穴11〇。而定位膜片1〇4 則具有開孔，關孔重疊於⑽上的孔穴UG做為凸塊座落蚊位， 以期降低凸塊偏移所造成的電性影響，並提高晶片可靠性。保護介 101則形成於晶片102與導線架103之間。引腳上的孔R 11〇以及膜片 104之開孔係用於避免凸塊與導線架接合定位不良、晶片偏移與封裝可g 之問題’此結馳傳統凸塊合併魏架職賴，魏提供—較佳 接合定位於導赫之特性，因此除可降低整體封裝製程因晶片偏 = 的土率損失之外’並可大巾S提高凸塊與導線架之接合性及整體封裝義 可罪性。 、口僻< 參考第十A圖所示，顯示封裝結構100帛二實施例之底視圖 裝結構100第二實施例之底視圖中，顯示導線架1〇3與保護介電材料1〇1、。 7 1297934 腳1G5以及晶片附著基座1G6。第三B圖顯示封裝姓構 10^第例的—截面圖。第三B圖特別顯示 ί^ίίΖ第—實施例的左側局部截面圖。在此第二實施例中;片圖 1^ ί⑴8與導線架⑽結合。導線架1G3的引腳上則ϋ孔 於曰片凸塊108的定位。孔穴110的數量與位置分布則取決 之^腳1〇5 ^开^ 1 量Ϊ位置分布。舉例來說，每一導線架⑽ 移所造成的電性影響，並提高晶片可靠性。保護介電‘ 1〇1 1G2與導線架1G3之間。引腳上的孔穴no可避免 併Ϊ緩:、晶片偏移與封裝可#性之問題，此結構較傳統凸^合 古裝製程因晶片偏移所造成的良率損失之外，並可大幅S 同凸塊與導線架之接合性及整體封裝結構之可靠性。 梦社t圖所示，顯示封裝結構励第三實施例之底視圖。在此封 弟二貫施例之底視圖中，顯示導線架1〇3與定位膜片1〇4，但 j，與保護介電材料101。導線架103包含引腳105以及晶片附著 B _示封裝結構1GG第三實施例的—截面圖。第四b圖 圖與第四a圖中封裝結構觸第三實施例的左側局部截 ，圖。在此弟二實施例中，晶片102透過導體凸塊1〇8與導線架1〇3結合。 ^位膜片1〇4具有開孔，此開孔重疊於導線架1〇3弓丨腳上做為凸塊ϋ盥 疋位之用，以期降低凸塊偏移所造成的電性影響，並提高晶片可靠性。 ，膜片104開孔的數量與位置分布則取決於晶片1〇2上之凸塊1〇8的 一位置分布。保護介電材料101則形成於晶片1〇2與導線架1〇3之間。定 =膜片104之開孔係用於避免凸塊與導線架接合定位不良、晶片偏移盥封 虞可靠性之問題，此結構較傳統凸塊合併導線架封裝結構，更能提供二較 佳的凸塊接合定位於導線架之特性，因此除可降低整體封裝製程因晶片偏 移所造成的良率損失之外，並可大幅提高凸塊與導線架之接合性及整 裝結構之可靠性。 參考第五Α圖所示，顯示第一與二實施例中導線架1〇3 一角的俯視圖。 如第五A圖所示，每一導線架1〇3之引腳105上具有一孔穴11〇。第五B與 五C圖分別顯示一引腳1〇5上具有一孔穴11〇的俯視圖與截面圖。 上述有關發明的實施方式僅為範例並非限制，其他不脫離本發明之精 1297934 神的等效改變或修飾均應包含在的本發明的專利範圍之内。 【圖式簡單說明】 為了能讓本發明上述之其他目的、特徵、和優點能更明顯易懂，下文特舉 一較佳實施例，並配合所附圖式，作詳細說明如下： 第一圖顯示一封裝結構的俯視圖； 第二A圖顯示本發明封裝結構第一實施例之底視圖； 第二B圖顯示本發明封裝結構第一實施例的一截面圖； 第二A圖顯示本發明封裝結構第二實施例之底視圖； 第三B圖顯示本發卿餘構第二實施例的—截面圖； 第四A_示本發明封裝結構第三實施例之底視圖； 弟四B圖顯示本發明封裝結構第三實施例的—截面圖； 第五八圖!爾食軸巾軸俯視圖；及 第五B與五C圖分別顯示一 弓ί腳上具有_孔穴的俯視圖與截面圖 【主要元件符號說明】 100封裝結構 101保護介電材料 102晶片導線架 103導線架 104定位膜片 9 1297934 105引腳 106晶片附者基座 108導體凸塊 110孔穴1297934 IX. Description of the invention: [Technical field to which the invention belongs]; = ί About a lead frame package structure, in particular, a large number of demanding discs for prior art Commercial semiconductor electronic component packaging has "and the development of semiconductor electronic engineering, limited #Electrical characteristics, ^ simplified system" assembly process, large-scale junction, enhanced m riding and high-conduction bulk I: 2 The micro-comb and high-product collection are used for the purpose of directly bonding the bumps of the wafer to the pre-silvered lead frame packaging technology, and the wafers are combined to achieve electrical information, and the bumps are bonded to the lead frame. The process often lacks 3釭2:!:22. For example, the question “Block's moist (dip) secret and fluidity can be joined. = In addition to causing the problem of electrical properties of the wafer, for the overall sealing of two points ί The purpose of the invention is to solve the above-mentioned problems. [Technical Problem] The technical problem to be solved by the present invention is to reduce the internal electrical connection and the overall package reliability due to bump bonding positioning, and the yield under the condition _ _, into a seal The technical problem to be solved by the present invention further includes the electrical properties of the wafer and the overall package structure due to the alignment of the bumps or the poor positioning of the bumps. Means storage-bump positioning transfer frame semiconductor package junction 5 1297934 bump wafer merged lead frame package caused by the vertical frame package structure, this structure is more traditional than the bump combination guide can reduce the body package process due to wafer bias jj 2 The bonding of the lead frame and the overall package size of the whole package structure, etc., the application range is extensively reduced, and the control tone, that is, the bump size and the crystal embodiment, the present invention provides a surface mount structure, the package structure includes the body The bump, the 'axis of the hole to accommodate the lead, the middle of the present invention provides another package structure, the package structure of the package is located on the lead frame and has an opening to accommodate il and In the embodiment of the present invention, the present invention provides another package structure. The package structure is positioned by a wire frame and a crucible. The wafer has a conductor bump, and the lead frame has a current block, and the wafer is supported by a conductor. Bump and the wire tie The positioning diaphragm; the coffin has an opening to receive the conductor bump, and each opening is overlapped with each hole. The lead frame module of the package structure is used. - L and a certain f film 1 The lead frame comprises a lead having a hole for receiving a die bump, the wafer being bonded to the lead frame by the conductor bump, the positioning film being located at the ^ The wire frame has an opening for accommodating the conductor bumps, and each opening is overlapped with each of the holes: the effect of the prior art and the prior art, since the present invention proposes a bump-positioned lead frame semi-definite structure, The method of pre-side holes on the guide pin and the specially designed lead frame are used as the bump seating and positioning, which can improve the joint positioning characteristics, wafer reliability and use of the wafer bumps. Lifetime and overall package reliability, thus achieving the deficiencies of prior art. The sins of the above-mentioned invention and the following embodiments are described in detail as examples and are not limiting. Equivalent changes or modifications that are within the spirit of the invention are intended to be included within the scope of the invention. [Embodiment] A piece. Structures and components do not contain complete structures and components. To carry out, only the need to understand the present invention is mentioned; very simplified and detailed description. It must be stated that the illustration looks down on the shed. In this package structure (10), there is a irrigator, a smashing of the electric material, and a wafer 102. This protective dielectric material 101 package shows an embodiment of three package structures in the fourth to fourth three ages. The mounting structure is in the bottom view of the embodiment. In the bottom view of the first embodiment, a lead frame 103 and a positioning diaphragm 1 〇 4 ΐ are shown to include a lead 1G5 and a wafer attachment base 106. The encapsulation structure (10) of the first embodiment of the encapsulation structure (10) is shown in the left part of the embodiment of the present invention. The Ba piece 102 is connected to the lead frame 1〇3 through the conductor bump (10) and has a hole 11〇' and the hole 11 The 〇 is used for the positioning of the bumps (10). %== fit 4 depends on the number and position distribution of the bumps 108 on the wafer 102. As a result, a hole 11 可 can be formed on the pin 105 of the female V-frame 103. The positioning diaphragm 1〇4 has an opening, and the hole UG which is closed on the (10) hole serves as a bump seating mosquito position, in order to reduce the electrical influence caused by the bump offset and improve the reliability of the wafer. A protective medium 101 is formed between the wafer 102 and the lead frame 103. The hole R 11〇 on the pin and the opening of the diaphragm 104 are used to avoid the problem of poor positioning of the bump and the lead frame, and the problem of the wafer offset and the package g can be gravated. Wei provides that the better bonding is located in the characteristics of the lead, so in addition to reducing the overall packaging process due to the loss of the soil rate of the wafer = 'can increase the bond between the bump and the lead frame and the overall package meaning Sinful. Referring to FIG. 10A, the bottom view of the second embodiment of the bottom view mounting structure 100 of the package structure 100 is shown. The lead frame 1〇3 and the protective dielectric material 1〇1 are displayed. ,. 7 1297934 Foot 1G5 and wafer attachment base 1G6. Figure 3B shows a cross-sectional view of the package name 10^. The third B-picture particularly shows a left side partial cross-sectional view of the first embodiment. In this second embodiment, the picture 1^ ί(1)8 is combined with the lead frame (10). The pins of the lead frame 1G3 are bored at the positioning of the tab bumps 108. The number and location of the holes 110 are determined by the position of the foot 1〇5 ^ open ^ 1 . For example, the electrical effects caused by each lead frame (10) shift and improve wafer reliability. Protect the dielectric between '1〇1 1G2 and lead frame 1G3. The hole no on the pin can be avoided and relieved: the problem of wafer offset and package can be achieved. This structure is larger than the yield loss caused by the wafer offset in the conventional bumping process. The bondability between the bump and the lead frame and the reliability of the overall package structure. As shown in the dream t-picture, the bottom view of the third embodiment is shown. In the bottom view of the second embodiment of the closure, the lead frame 1〇3 and the positioning diaphragm 1〇4, but j, and the protective dielectric material 101 are shown. The lead frame 103 includes a lead 105 and a wafer attachment B - a cross-sectional view of the third embodiment of the package structure 1GG. The fourth b-picture and the fourth a-picture encapsulation structure touch the left side partial cross-sectional view of the third embodiment. In the second embodiment, the wafer 102 is bonded to the lead frame 1〇3 through the conductor bumps 1〇8. ^The film piece 1〇4 has an opening which is overlapped on the lead frame of the lead frame 1〇3 as a bump clamping position, in order to reduce the electrical influence caused by the bump offset, and Improve wafer reliability. The number and positional distribution of the openings of the diaphragm 104 depend on a positional distribution of the bumps 1〇8 on the wafer 1〇2. The protective dielectric material 101 is formed between the wafer 1〇2 and the lead frame 1〇3. The opening of the diaphragm 104 is used to avoid the problem of poor positioning of the bump and the lead frame, and the reliability of the wafer offset and the sealing. The structure is better than the conventional bump and lead frame package structure. The bump bonding is positioned on the characteristics of the lead frame, so that the overall package process can reduce the yield loss caused by the wafer offset, and the bond between the bump and the lead frame and the reliability of the package structure can be greatly improved. . Referring to the fifth drawing, a plan view showing a corner of the lead frame 1〇3 in the first and second embodiments is shown. As shown in FIG. 5A, each lead frame 1〇3 has a hole 11〇 on the pin 105. The fifth and fifth C-pictures respectively show a top view and a cross-sectional view of a pin 1 〇 5 having a hole 11 。. The above-described embodiments of the invention are merely exemplary and not limiting, and other equivalent changes or modifications of the invention are intended to be included within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the other objects, features and advantages of the present invention more comprehensible, the following detailed description of the preferred embodiments A top view of a package structure of the present invention is shown; a second view showing a bottom view of the first embodiment of the package structure of the present invention; a second block view showing a first embodiment of the package structure of the present invention; The bottom view of the second embodiment of the structure; the third B shows the cross-sectional view of the second embodiment of the present invention; the fourth A_ shows the bottom view of the third embodiment of the package structure of the present invention; A cross-sectional view of a third embodiment of the package structure of the present invention; a fifth top view of the food shaft axis; and a fifth and fifth C diagram respectively showing a top view and a cross-sectional view of the hole having a hole. Component Symbol Description 100 Package Structure 101 Protective Dielectric Material 102 Wafer Conductor 103 Lead Frame 104 Positioning Membrane 9 1297934 105 Pin 106 Wafer Attachment Base 108 Conductor Bump 110 Hole