CN111725083A - 一种芯片金属凸块成型方法 - Google Patents

一种芯片金属凸块成型方法 Download PDF

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CN111725083A
CN111725083A CN202010641512.1A CN202010641512A CN111725083A CN 111725083 A CN111725083 A CN 111725083A CN 202010641512 A CN202010641512 A CN 202010641512A CN 111725083 A CN111725083 A CN 111725083A
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layer
photoresist
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梅嬿
陈浩
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Hefei Qizhong Sealing Technology Co ltd
Chipmore Technology Corp Ltd
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Hefei Yisiwei Sealing And Testing Technology Co ltd
Beijing Eswin Technology Co Ltd
Chipmore Technology Corp Ltd
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Abstract

本发明公开了一种芯片金属凸块成型方法,包括如下步骤:提供硅基板,所述硅基板的上表面形成有电极和钝化层,所述电极自钝化层上的钝化层开口向外暴露。在钝化层及电极上表面覆盖种子层。在种子层上表面形成光阻层。去除部分光阻以形成光阻开口,所述光阻开口完全覆盖钝化层开口所在区域。在光阻开口内成型金属柱,金属柱包括自下而上依次成型的金属基层和金属锡层。对成型的金属柱进行芯片探针测试。采用回流工艺将进行芯片探针测试后的金属锡层形成金属帽。本发明能够有效的修复芯片探针测试过程中对金属柱端头的损伤,磨平芯片探针测试形成的针痕从而避免了针痕造成的金属凸块的表面的不平坦进而避免对后续工艺及产品性能的影响。

Description

一种芯片金属凸块成型方法
技术领域
本发明涉及芯片封装技术领域,特别是一种芯片金属凸块成型方法。
背景技术
在半导体封装的过程中,要先在晶片的焊垫区域制备凸块,然后将晶背磨薄到一定的厚度并切割成各个独立的芯片,最后将芯片上的金属凸块与基板焊垫上的引脚结合。金属凸块的制作成型是芯片制造封装中的一个关键技术。
金属凸块的制作一般伴随着将金属凸块顶部的锡柱回流焊形成金属帽而结束。为了保证凸块制造工艺良率相对稳定同时为了节约封装成本,通常要在金属凸块成型后进行芯片探针测试(CP,chip probing),以对晶圆进行筛选,挑出不合格的芯片。但是在进行CP测试时,探针需要与金属凸块的金属帽接触,这可能导致金属帽的损坏以形成测试针痕。该测试针痕使得金属凸块表面不平坦,这对后续工艺及产品性能带来困难。
因此,为解决上述技术问题,有必要提出一种新的芯片金属凸块成型方法。
发明内容
本发明的目的是提供一种芯片金属凸块成型方法,以解决现有技术中的不足,它能够有效的修复芯片探针测试过程中对金属柱端头的损伤,磨平芯片探针测试形成的针痕从而避免了针痕造成的金属凸块的表面的不平坦进而避免对后续工艺及产品性能的影响。
本发明提供了一种芯片金属凸块成型方法,包括如下步骤:
提供硅基板,所述硅基板的上表面形成有电极和钝化层,所述电极自钝化层上的钝化层开口向外暴露;
在钝化层及电极上表面覆盖种子层;
在种子层上表面形成光阻层;
去除部分光阻以形成光阻开口,所述光阻开口完全覆盖钝化层开口所在区域;
在光阻开口内成型金属柱,金属柱包括自下而上依次成型的金属基层和金属锡层;
对成型的金属柱进行芯片探针测试;
采用回流工艺将进行芯片探针测试后的金属锡层形成金属帽。
作为本发明的进一步改进,在“采用回流工艺将进行芯片探针测试后的金属锡层形成金属帽”之前还具有如下步骤:
去除剩余光阻和与剩余光阻对于的种子层。
作为本发明的进一步改进,“去除部分光阻以形成光阻开口,所述光阻开口完全覆盖钝化层开口所在区域”包括如下步骤:
曝光:用曝光机对需要形成金属柱的位置的光阻进行曝光照射使之发生光溶解反应;
显影:用显影机和显影液,通过浸泡产生化学反应,去除掉曝光的光阻,以将需要形成金属柱的位置形成光阻开口。
作为本发明的进一步改进,所述显影液的质量含量为2.3-2.4%的四甲基氢氧化铵水溶液;
所述曝光机所用的照射光的波长为405-436纳米。
作为本发明的进一步改进,所述种子层为通过溅射工艺成型的金属溅射层,该金属溅射层为钛钨合金材质。
作为本发明的进一步改进,所述金属柱的高度低于所述光阻层的高度。
作为本发明的进一步改进,所述金属柱通过电镀工艺成型在所述光阻开口内。
作为本发明的进一步改进,所述金属锡层为银锡合金或铅锡合金。
作为本发明的进一步改进,所述金属基层为铜柱。
作为本发明的进一步改进,所述金属柱还包括设置在所述金属基层与所述金属锡层之间的镍层。
与现有技术相比,本发明在成型金属柱之后在将金属柱的端头通过回流工艺成型金属帽之前进行芯片探针测试,在芯片探针测试完成之后再进行回流工艺将金属柱端头形成球形的金属帽。在该过程中能够有效的修复芯片探针测试过程中对金属柱端头的损伤,磨平芯片探针测试形成的针痕从而避免了针痕造成的金属凸块的表面的不平坦进而避免对后续工艺及产品性能的影响。
附图说明
图1是本发明实施例公开的芯片金属凸块成型方法的流程示意图;
图2是本发明实施例公开的芯片金属凸块成型方法中形成钝化层开口的结构示意图;
图3是本发明实施例公开的芯片金属凸块成型方法中形成种子层后的结构示意图;
图4是本发明实施例公开的芯片金属凸块成型方法中形成光阻开口后的结构示意图;
图5是本发明实施例公开的芯片金属凸块成型方法中形成金属柱后的结构示意图;
图6是本发明实施例公开的芯片金属凸块成型方法中去除剩余光阻后的结构示意图;
图7是本发明实施例公开的芯片金属凸块成型方法中芯片探针测试过程中的结构示意图;
图8是本发明实施例公开的芯片金属凸块成型方法中芯片探针测试后的结构示意图;
图9是本发明实施例公开的芯片金属凸块成型方法中形成金属帽后的结构示意图;
附图标记说明:1-硅基板,11-电极,12-钝化层,13-钝化层开口,2-种子层,3-光阻层,31-光阻开口,4-金属柱,41-金属基层,42-金属锡层,43-镍层,100-探针,101-针痕。
具体实施方式
下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
本发明的实施例:如图1所示,公开了一种芯片金属凸块成型方法,包括如下步骤:
步骤101:提供硅基板1,所述硅基板1的上表面形成有电极11和钝化层12,所述电极11自钝化层12上的钝化层开口13向外暴露。硅基板1上形成电极11,钝化层12覆盖在硅基板1及部分电极11之上,钝化层12搭接在部分电极11的边沿位置,电极11上未被钝化层12覆盖的区域向外暴露,以形成钝化层开口13,如图2所示。
S103:如图3所示,在钝化层12及电极11上表面覆盖种子层2。所述种子层2为通过溅射工艺成型的金属溅射层,该金属溅射层为钛钨合金材质。
S105:在种子层2上表面形成光阻层3。用光阻涂布机在种子层2上表面涂覆厚度为20-120微米的光阻;该步涂布的光阻主要成分为酚醛树脂和感光剂,是一种对特定波长的光有光溶解特性的有机物,以便于下步定点曝光,去除需要用于成型金属柱4位置的光阻。
S107:去除部分光阻以形成光阻开口31如图4所示,所述光阻开口31完全覆盖钝化层开口13所在区域。光阻开口31的区域用于形成金属柱4。去除光阻的具体步骤如下:
曝光:用曝光机对需要形成金属柱4的位置的光阻进行曝光照射使之发生光溶解反应;在本实施例中可以使用波长405-436纳米的光照射10-150秒以方便的实现光阻的溶解。
显影:用显影机和显影液,通过浸泡产生化学反应,去除掉曝光后的光阻,以将需要形成金属柱4的位置形成光阻开口31。所述显影液可以为质量含量为2.3-2.4%的四甲基氢氧化铵水溶液。
S109:在光阻开口31内成型金属柱4如图5所示,其中金属柱4包括自下而上依次成型的金属基层41和金属锡层42。金属基层41和金属锡层42可以采用蒸发沉积法、电镀法、钉头凸块法或者微球法成型设置,在本实施例中所述金属柱4通过电镀工艺成型在所述光阻开口31内,具体的,金属基层41直接电镀成型在种子层2上表面,金属锡层42直接电镀成型在金属基层41上表面。
设置金属锡层42银锡合金或铅锡合金。所述金属锡层42设置的目的是方便后续回流过程中形成金属帽以及方便实现成型后的金属凸块的焊接固定。
在成型金属柱4后金属柱4的高度一般设置为低于所述光阻层3的高度。
在本实施例中金属基层41为铜凸块。
进一步的,所述金属柱4还包括设置在所述金属基层41与所述金属锡层42之间的镍层43。
S111:对成型的金属柱4进行芯片探针测试。探针测试的探针100下压在金属柱4上上端如图7所示,由于金属柱4的上端为金属锡层42其硬度较低,而在进行芯片探针测试的时候为了保证探针与金属柱4充分的接触需要探针100下压在金属柱4上,因此在金属柱4的顶端容易被探针100压出针痕101如图8所示,该针痕101的存在会影响后期的封装等相关制程。本实施例在芯片探针测试之后再进行回流焊使金属柱4上的金属锡层42形成金属帽从而能够有效的修复芯片探针测试造成的针痕。
S113:采用回流工艺将进行芯片探针测试后的金属锡层42形成金属帽如图9所示。在金属帽的成型过程中需要重新融化金属锡层42然后再次成型,在这个过程中能够对针痕进行修复。
在本实施例中在进行完芯片探针测试之后再通过回流工艺将金属锡层42形成金属帽,能够有效的修复芯片探针测试过程中形成的针痕,从而有效的避免了对后续制程的影响。
在“采用回流工艺将进行芯片探针测试后的金属锡层42形成金属帽”之前还具有如下步骤:
S110:去除剩余光阻和与剩余光阻对于的种子层2如图6所示。该步骤需要在成型金属柱4之后,在芯片探针测试之前进行,其中去除的剩余的光阻一般为金属柱4的外围的光阻,同时也去除金属柱4外围的种子层。
以上依据图式所示的实施例详细说明了本发明的构造、特征及作用效果,以上所述仅为本发明的较佳实施例,但本发明不以图面所示限定实施范围,凡是依照本发明的构想所作的改变,或修改为等同变化的等效实施例,仍未超出说明书与图示所涵盖的精神时,均应在本发明的保护范围内。

Claims (10)

1.一种芯片金属凸块成型方法,其特征在于,包括如下步骤:
提供硅基板,所述硅基板的上表面形成有电极和钝化层,所述电极自钝化层上的钝化层开口向外暴露;
在钝化层及电极上表面覆盖种子层;
在种子层上表面形成光阻层;
去除部分光阻以形成光阻开口,所述光阻开口完全覆盖钝化层开口所在区域;
在光阻开口内成型金属柱,金属柱包括自下而上依次成型的金属基层和金属锡层;
对成型的金属柱进行芯片探针测试;
采用回流工艺将进行芯片探针测试后的金属锡层形成金属帽。
2.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:在“采用回流工艺将进行芯片探针测试后的金属锡层形成金属帽”之前还具有如下步骤:
去除剩余光阻和与剩余光阻对于的种子层。
3.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:“去除部分光阻以形成光阻开口,所述光阻开口完全覆盖钝化层开口所在区域”包括如下步骤:
曝光:用曝光机对需要形成金属柱的位置的光阻进行曝光照射使之发生光溶解反应;
显影:用显影机和显影液,通过浸泡产生化学反应,去除掉曝光的光阻,以将需要形成金属柱的位置形成光阻开口。
4.根据权利要求3所述的芯片金属凸块成型方法,其特征在于:所述显影液的质量含量为2.3-2.4%的四甲基氢氧化铵水溶液;
所述曝光机所用的照射光的波长为405-436纳米。
5.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:所述种子层为通过溅射工艺成型的金属溅射层,该金属溅射层为钛钨合金材质。
6.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:所述金属柱的高度低于所述光阻层的高度。
7.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:所述金属柱通过电镀工艺成型在所述光阻开口内。
8.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:所述金属锡层为银锡合金或铅锡合金。
9.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:所述金属基层为铜柱。
10.根据权利要求1所述的芯片金属凸块成型方法,其特征在于:所述金属柱还包括设置在所述金属基层与所述金属锡层之间的镍层。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01281756A (ja) * 1988-05-07 1989-11-13 Seiko Epson Corp 半導体素子の製造方法
JPH10308406A (ja) * 1997-03-03 1998-11-17 Sony Corp 半導体装置の製造方法及びこれに用いる低温熱処理装置
CN103413770A (zh) * 2013-08-30 2013-11-27 南通富士通微电子股份有限公司 凸点的制造方法
CN105225977A (zh) * 2015-11-03 2016-01-06 中芯长电半导体(江阴)有限公司 一种铜柱凸块结构的制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01281756A (ja) * 1988-05-07 1989-11-13 Seiko Epson Corp 半導体素子の製造方法
JPH10308406A (ja) * 1997-03-03 1998-11-17 Sony Corp 半導体装置の製造方法及びこれに用いる低温熱処理装置
CN103413770A (zh) * 2013-08-30 2013-11-27 南通富士通微电子股份有限公司 凸点的制造方法
CN105225977A (zh) * 2015-11-03 2016-01-06 中芯长电半导体(江阴)有限公司 一种铜柱凸块结构的制作方法

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