CN111725083A - 一种芯片金属凸块成型方法 - Google Patents
一种芯片金属凸块成型方法 Download PDFInfo
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- CN111725083A CN111725083A CN202010641512.1A CN202010641512A CN111725083A CN 111725083 A CN111725083 A CN 111725083A CN 202010641512 A CN202010641512 A CN 202010641512A CN 111725083 A CN111725083 A CN 111725083A
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- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
- H01L2224/0362—Photolithography
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/03849—Reflowing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/11618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive bump material, e.g. of a photosensitive conductive resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/11622—Photolithography
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11825—Plating, e.g. electroplating, electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN202010641512.1A CN111725083A (zh) | 2020-07-06 | 2020-07-06 | 一种芯片金属凸块成型方法 |
Applications Claiming Priority (1)
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CN202010641512.1A CN111725083A (zh) | 2020-07-06 | 2020-07-06 | 一种芯片金属凸块成型方法 |
Publications (1)
Publication Number | Publication Date |
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CN111725083A true CN111725083A (zh) | 2020-09-29 |
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CN202010641512.1A Pending CN111725083A (zh) | 2020-07-06 | 2020-07-06 | 一种芯片金属凸块成型方法 |
Country Status (1)
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CN (1) | CN111725083A (zh) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01281756A (ja) * | 1988-05-07 | 1989-11-13 | Seiko Epson Corp | 半導体素子の製造方法 |
JPH10308406A (ja) * | 1997-03-03 | 1998-11-17 | Sony Corp | 半導体装置の製造方法及びこれに用いる低温熱処理装置 |
CN103413770A (zh) * | 2013-08-30 | 2013-11-27 | 南通富士通微电子股份有限公司 | 凸点的制造方法 |
CN105225977A (zh) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体(江阴)有限公司 | 一种铜柱凸块结构的制作方法 |
-
2020
- 2020-07-06 CN CN202010641512.1A patent/CN111725083A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01281756A (ja) * | 1988-05-07 | 1989-11-13 | Seiko Epson Corp | 半導体素子の製造方法 |
JPH10308406A (ja) * | 1997-03-03 | 1998-11-17 | Sony Corp | 半導体装置の製造方法及びこれに用いる低温熱処理装置 |
CN103413770A (zh) * | 2013-08-30 | 2013-11-27 | 南通富士通微电子股份有限公司 | 凸点的制造方法 |
CN105225977A (zh) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体(江阴)有限公司 | 一种铜柱凸块结构的制作方法 |
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PB01 | Publication | ||
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CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant after: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant after: Xi'an yisiwei Material Technology Co.,Ltd. Applicant after: Hefei Qizhong Sealing Technology Co.,Ltd. Address before: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant before: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant before: Beijing yisiwei Material Technology Co.,Ltd. Applicant before: Hefei Qizhong Sealing Technology Co.,Ltd. Address after: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant after: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant after: Beijing yisiwei Material Technology Co.,Ltd. Applicant after: Hefei Qizhong Sealing Technology Co.,Ltd. Address before: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant before: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant before: Beijing yisiwei Technology Co.,Ltd. Applicant before: Hefei yisiwei sealing and Testing Technology Co.,Ltd. |
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TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20210609 Address after: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant after: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant after: Hefei Qizhong Sealing Technology Co.,Ltd. Address before: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant before: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant before: Xi'an yisiwei Material Technology Co.,Ltd. Applicant before: Hefei Qizhong Sealing Technology Co.,Ltd. |
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CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant after: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant after: Hefei Qizhong Technology Co.,Ltd. Address before: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province Applicant before: CHIPMORE TECHNOLOGY Corp.,Ltd. Applicant before: Hefei Qizhong Sealing Technology Co.,Ltd. |
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RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200929 |