CN111722031A - Direct current traction protection tester device based on FPGA - Google Patents
Direct current traction protection tester device based on FPGA Download PDFInfo
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Abstract
The invention relates to the technical field of rail transit, in particular to a direct current traction protection tester device based on an FPGA (field programmable gate array), which comprises hardware peripheral resources, a core control board and a power panel, wherein the power panel is used for supplying power for the tester device; the core control board comprises a CPU chip, an FPGA chip and an SDRAM, the CPU chip and the FPGA chip share the SDRAM to realize data reading and writing of the SDRAM by the CPU chip, and the CPU chip realizes control of the tester device on each test unit in the FPGA chip and reading of test parameters through register configuration. The tester device greatly improves the response speed of the device, and ensures the accuracy of the returned fault value and the fault time when the tested device breaks down, thereby being convenient and fast.
Description
Technical Field
The invention relates to the technical field of rail transit, in particular to a direct current traction protection tester device based on an FPGA (field programmable gate array).
Background
The rail transit industry in China is developing vigorously, a direct current traction protection system also becomes an important component of rail transit, the direct current traction protection system is mainly protected by direct current switch equipment, and a direct current circuit is divided into two types, namely a rectifier circuit breaker and a feeder circuit breaker according to different functional conditions.
Under the background that subway power supply equipment is increasingly made into a country, high value-added products such as a direct current transmitter, a direct current traction protection device and the like attract many universities and equipment manufacturers to increase research and development investment on the products. However, no suitable test equipment can be found in the market at present to comprehensively test the direct current traction protection device system.
Although the existing relay protection device test system has realized the automation of the test and improved the comprehensiveness of the test items to a certain extent, the existing relay protection device test system has certain limitations in the test item execution process, slow test response time, large test action value error and the like. And the existing relay protection tester devices are large and heavy in size, inconvenient to carry and more unfavorable for use in narrow space on site.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a direct current traction protection tester device based on an FPGA (field programmable gate array), which has compact modular circuit design and structural design, is light and small in size, solves the problems of large size, heavy weight, inconvenience in carrying and the like of the conventional tester, and realizes the function test design of a direct current relay protection device, such as basic electrical quantity test, overcurrent/voltage protection test, di/dt current rise rate protection test and the like, through the combined action of a CPU (central processing unit) + FPGA (field programmable gate array) chip architecture, an analog quantity output module, an analog quantity input module, a network port communication module and other devices.
In order to achieve the purpose, the invention provides the following technical scheme:
a direct current traction protection tester device based on FPGA comprises hardware peripheral resources, a core control panel and a power panel, the power panel is used for supplying power for the tester device, the hardware peripheral resources are connected with the core control panel through double rows of pins, the hardware peripheral resources comprise an analog quantity output module, an analog quantity input module, a switching value input module and a switching value output module, the analog quantity output module is used for converting digital signals sent out under the core control board into analog signals, the analog quantity input module is used for converting the acquired analog quantity into a digital signal and then transmitting the digital signal to the core control panel, the switching value input module is used for capturing the action signal of the device to be tested and transmitting the acquired level change to the core control board, the switching value output module converts the action signal transmitted by the core control panel into a switching action signal and outputs the switching action signal to an external port;
the core control panel comprises a CPU chip, an FPGA chip and an SDRAM memory, the CPU chip and the FPGA chip share the SDRAM memory to realize data reading and writing of the CPU chip to the SDRAM memory, the CPU chip realizes control of the tester device on each test unit in the FPGA chip and reading of test parameters through register configuration, and the core control panel is further provided with a network port communication module which is used for connecting the tester device with a PC end.
Furthermore, the analog output module comprises an optical coupling isolation module, a digital-to-analog conversion module and an output quantity conditioning module, the FPGA chip sends a control signal to the optical coupling isolation module, the optical coupling isolation module filters out high-frequency and electromagnetic interference signals and transmits the signals to the digital-to-analog conversion module, a DAC chip in the digital-to-analog conversion module converts digital signals into analog signals and outputs the analog signals to the output quantity conditioning module, and the output quantity conditioning module converts the analog signals into standard signals.
Furthermore, the analog input module comprises an optical coupling isolation module, an analog-to-digital conversion module and a switch control module, the analog-to-digital conversion module comprises a programmable analog-to-digital converter (ADC) chip, the FPGA chip receives information collected by a Central Processing Unit (CPU) chip, the FPGA chip sends a control signal to the optical coupling isolation module, interference signals such as high frequency and electromagnetism are filtered out by the optical coupling isolation module and transmitted to the analog-to-digital conversion module, and the ADC chip in the analog-to-digital conversion module receives the control signal and converts the control signal into a digital signal, and then the digital signal is transmitted to the FPGA chip.
Further, the switch control module comprises a switch chip, and the CPU chip controls the on and off of the switch chip so as to control the on and off of the analog input module.
Furthermore, the switching value input module comprises a photoelectric coupling module and a switching value acquisition module, the switching value acquisition module is responsible for sensing action signals of the device to be tested, and when the high and low levels change, the action levels are immediately output and transmitted to the core control panel through the photoelectric coupling module, and the FPGA chip receives the action signals, so that the current fault of the device to be tested is judged, and the current fault output analog value and the action time are immediately transmitted back to the CPU chip for processing.
Furthermore, the switching value output module comprises a relay control module and a switching value output module, the CPU chip controls the relay in the relay control module to act, and the switching value output module outputs an on/off action level to the external port.
Further, the hardware peripheral resources further include a small signal (+/-600 mV) output module connected behind the output quantity conditioning module, and the small signal output module is used for converting the voltage analog quantity signal (+/-10V) into a small signal (+/-600 mV) to be output.
Further, the CPU chip adopts STM32F407 series, the FPGA chip adopts Cyclone IV E series, and the SDRAM chip adopts 16M memory chip.
Further, the core control board further comprises a status indicator light, and the status indicator light is connected with the CPU chip.
Further, the relay control module mainly comprises a small relay and has the high-voltage switching capacity of 10A and 300 VDC.
In the invention, a hardware peripheral resource analog quantity output module is used for receiving control signals and parameters issued by an FPGA (field programmable gate array), wherein an optical coupling isolator comprises an isolation chip, the isolation chip adopts a 4-channel digital isolator, interference signals such as high frequency, electromagnetism and the like are filtered out by the isolator and then transmitted to a digital-to-analog conversion module, the digital signals isolated by the isolation module are converted into analog signals and then transmitted to an output quantity conditioning module, and the analog quantity output by the DAC chip is conditioned into standard type signals such as +/-20 mA and 4-20 mA;
the hardware peripheral resource analog quantity input module is used for receiving control signals and parameters issued by the FPGA through an optical coupling isolator, transmitting the signals to an analog-to-digital conversion module after isolation, starting work after an ADC chip receives the control signals, transmitting converted digital quantity values back to a core control through the optical coupling isolator, and finally controlling the start of the whole module work through a switch control module;
the CPU chip and the FPGA chip share the SDRAM memory, the SDRAM memory is controlled by the FPGA chip, data read-write in the SDRAM memory by the CPU chip is realized, the CPU chip realizes control of each test unit in the FPGA chip and reading of test parameters through a parallel data bus, the FPGA chip can be used as an off-chip NORRAM of the CPU chip, the CPU chip can directly access a memory in the FPGA chip through the parallel data bus, meanwhile, a network port communication module on a core control panel supports TCP/IP, a tester device is connected with a PC end through an Ethernet interface, and meanwhile, an instruction of the PC end can be received, so that bidirectional communication is realized.
In the invention, the DAC chip and the ADC chip greatly improve the response speed of the device and ensure the accuracy of the returned fault value and the fault time when the tested device has a fault.
Compared with the prior art, the invention has the following beneficial effects:
1. the direct current traction protection tester device based on the FPGA is compact in structural design, light and small in size, and solves the problems that an existing tester is large in size, heavy, inconvenient to carry and the like;
2. the invention adopts the FPGA chip, the digital-to-analog conversion module, the analog-to-digital conversion module and other modules, enriches the input/output interface types of the device, for example, tests under the conditions of +/-20 mA, 4-20mA and +/-10V, and leads the application places of the tester to be wider;
3. the invention provides a method for realizing the function test design of a direct current relay protection device by adopting the combined action of devices such as an analog quantity output module, an analog quantity input module, a network port communication module and the like, such as a basic electric quantity test, an overcurrent/voltage protection test, a di/dt current rise rate protection test and the like.
Drawings
FIG. 1 is a hardware structure diagram of the DC traction protection tester device based on FPGA of the present invention;
FIG. 2 is an application diagram of a typical structure of the DC traction protection tester device based on FPGA of the present invention;
FIG. 3 is a schematic diagram of an FPGA functional logic register of the FPGA-based DC traction protection tester apparatus of the present invention;
FIG. 4 is a FPGA implementation flowchart of an overcurrent/voltage function test unit of the FPGA-based DC traction protection tester apparatus of the present invention;
FIG. 5 is a flow chart of an FPGA implementation of a di/dt functional test unit of the FPGA-based DC traction protection tester apparatus of the present invention;
fig. 6 is a flow chart of the FPGA implementation of the custom curve function test unit of the dc traction protection tester apparatus based on the FPGA of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The direct current traction protection tester device based on the FPGA of the invention, referring to figure 1, comprises a hardware peripheral resource, a core control board and a power board, wherein the hardware peripheral resource and the core control board are connected by double-row pins, the hardware peripheral resource comprises an analog quantity output module, an analog quantity input module, a switching quantity input module and a switching quantity output module, the core control board comprises a CPU chip (adopting STM32F407 series), an FPGA chip (Field Programmable Gate Array, adopting Cyclone IV E series) and an SDRAM memory (adopting 16M memory chip as SDRAM chip), the power board receives 220V alternating current to output +/-5V and +/-24V direct current to supply power for other modules, the analog quantity output module (AO module) is used for converting digital signals sent by the FPGA chip into analog signals, the analog quantity input module (AI module) is used for converting collected analog quantities into digital signals, and the switching value input module (BI module) is used for capturing the action signal of the device to be tested and transmitting the acquired level change to the core control board so that the tester can know the current action time and action value, and the switching value output module (BO module) converts the action signal transmitted by the core control board into a switching action signal to be output to an external port.
Referring to fig. 1, the analog output module (AO module) includes an optical coupling isolation module, a digital-to-analog conversion module, and an output conditioning module, wherein a DAC core is disposed in the digital-to-analog conversion module and communicates with an FPGA chip through an SPI protocol, the FPGA chip sends a control signal to the optical coupling isolation module, the optical coupling isolation module includes an isolation chip (a 4-channel digital isolator is adopted), interference signals such as high frequency and electromagnetism are filtered out through the optical coupling isolation module and transmitted to the digital-to-analog conversion module, the DAC chip in the digital-to-analog conversion module converts the digital signal into an analog signal and outputs the analog signal to the output conditioning module, the output conditioning module includes an adjustment chip (a 1550 max series is adopted), the analog signal is converted into a standard signal corresponding to the standard signal and outputs the standard signal, and the.
Referring to fig. 1, Analog input module (AI module) includes opto-coupler isolation module, Analog-to-digital conversion module, on-off control module, Analog-to-digital conversion module includes programmable ADC chip (Analog-to-digital converter), the ADC chip passes through SPI protocol and FPGA chip communication, the FPGA chip receives CPU chip information collection, the FPGA chip sends control signal to opto-coupler isolation module, filters out interference signals such as high frequency, electromagnetism through opto-coupler isolation module and transmits to Analog-to-digital conversion module, ADC chip among the Analog-to-digital conversion module receives control signal and turns into digital signal after, and rethread opto-coupler isolation module transmits to the FPGA chip in, and the FPGA chip receives the digital value after the passback and handles for the CPU chip.
The switch control module mainly comprises external circuits such as a switch chip and the like, and the CPU chip controls the on-off of the switch chip so as to control the on-off of the analog input module.
Referring to fig. 1, the switching value input module (BI module) includes a photoelectric coupling module and a switching value acquisition module, the switching value acquisition module is responsible for sensing an action signal of the device to be tested, and when a high level and a low level change, an action level is immediately output and transmitted to the core control board through the photoelectric coupling module, and after the FPGA chip receives the action signal, the current fault of the device to be tested is judged, and an analog value and an action time of the current fault are immediately output and transmitted back to the CPU chip for processing.
In this embodiment, the switching value acquisition module is composed of a PNP-type triode and the like, when the external input port is closed, the triode is turned on to close the photoelectric coupler, and the FPGA chip receives the low level sent by the photoelectric coupling module, so as to judge the action of the switching value input module; when the external input port is opened, the triode is in a cut-off state, the photoelectric coupler is enabled to be in an open state, and the FPGA chip receives a high level sent by the photoelectric coupling module, so that the switching value input module is judged to be in a static state.
Referring to fig. 2, the switching value output module (BO module) includes a relay control module and a switching value output module, and the CPU chip controls the relay in the relay control module to operate, and outputs an on/off operation level to the external port through the switching value output module. The relay control module mainly comprises a small relay and has the capability of switching between 10A and 300VDC direct current high voltage.
In this embodiment, the switching value output module is composed of a PNP type triode, and when the relay is closed, the triode is turned on and outputs a high level signal to the interface; when the relay is disconnected, the triode is cut off, and a low level signal value interface is output.
The hardware peripheral resources further comprise a small signal (+ -600 mV) output module which is arranged behind the output quantity conditioning module and connected with the output quantity conditioning module, and the small signal output module is used for converting the voltage analog quantity signal (+ -10V) into a small signal (+ -600 mV) to be output.
Referring to fig. 1, the core control board further includes a status indicator light, and the status indicator light is connected to the CPU chip.
Referring to fig. 1 and 2, the CPU chip and the FPGA chip share an SDRAM memory, the CPU chip implements control of a tester process and reading of test parameters through register configuration, the CPU chip and the FPGA chip implement data interaction by using a parallel data bus interface, and the CPU chip issues each function parameter to the FPGA chip in an addressing manner; and the FPGA chip transmits the current test result parameters to the CPU chip through the data line. The SDRAM memory comprises an SDRAM chip, the SDRAM chip is divided into 4 memory areas, each memory area is divided into 4M memories, and the characteristic of synchronous dynamic storage of the SDRAM chip is utilized, so that the waiting time required by a system bus when the system bus operates the asynchronous SDRAM memory is avoided, and the data transmission speed is accelerated. And the FPGA chip is used as a medium to realize the operation of the SDRAM by the CPU chip. The core control panel is also provided with a network port communication module, the network port communication module mainly comprises a network port chip, and the network port communication module connects the tester device with the PC end through an Ethernet interface.
Referring to fig. 2, the analog output module is provided with an AO port (analog output port), the analog input module is provided with an AI port (analog acquisition port), the tester outputs a standard ± 20mA or 4-20mA analog current signal to the AI port of the dc relay protection device through the AO port, and if the input current signal value exceeds the trip action value set by the dc relay protection device, the dc relay protection device outputs a high/low level signal to a BI port (switching value acquisition port) of the tester through a BO port (switching value output port). The tester obtains the current action time node and the current or voltage value during action of the direct current relay protection system according to the level change of the BI port, and then the current or voltage value is transmitted to the PC end interface for display, and a user can judge the characteristics of the current tested direct current relay protection system according to the action value returned by the tester.
Referring to fig. 3, the register setting module is an interface for communication between the CPU chip and the FPGA chip, and the CPU chip writes data into the corresponding register in an addressing manner. The register setting module comprises an electric quantity register module, a system parameter configuration register module and a public configuration register module, the electric quantity register module realizes the output of a self-defined current/voltage value of the tester, the system parameter configuration register module mainly configures specific parameters required for realizing various functional logics, such as an analog quantity input/output type parameter, an experiment duration parameter, an experiment start-stop value range and the like, and the register setting module can learn the current experiment input/output real-time value, the action time and the action value of the direct current relay protection system during action by reading a parameter register in the module. The common configuration register area mainly comprises function selection parameters, experiment starting/stopping parameters, experiment current state parameters and the like, the register setting module realizes the division and starting and stopping of various protection test functions by configuring the register parameters in the module, and can also read the parameter register in the module so as to obtain the current experiment state. The bottom layer is mainly provided with various protection test units, when function selection parameters in a public configuration register area receive basic electric quantity function parameters, an FPGA chip enters the logic of the basic electric quantity test unit, corresponding output types such as +/-20 mA, +/-10V and the like are selected in the unit according to analog quantity output type parameters in a system configuration register module, and when a start-stop signal issued by the public configuration register area is received, parameter values in the electric quantity register module are transmitted to an AO port, so that customized electric quantity value output is realized; when the function selection parameter receives an overcurrent/voltage test function parameter, the FPGA chip enters the logic of an overcurrent/voltage test unit, before an experiment starting parameter is issued in a public configuration register area, the test unit needs to receive the overcurrent/voltage test experiment parameter issued in a system parameter configuration area, such as the output change range, the AO change duration, the step length and the like of an AO port, after the experiment is started, the parameter is transmitted to the AO port according to the set experiment parameter, meanwhile, the system can also obtain the simulation output value of the current experiment and the simulation input action value and action time when the experiment acts by reading a register in an overcurrent test register module, and the test unit is mainly used for testing the overcurrent action response characteristic of the direct current relay protection device;
when the function selection parameter receives a di/dt test function parameter, the FPGA chip enters the logic of a di/dt test unit, the test unit is mainly used for testing the response characteristic of a current rise rate protection experiment performed by a direct current relay protection system, the parameter configuration is the same as that of an overcurrent/voltage test unit, namely, before issuing a starting parameter, the di/dt experiment parameter needs to be issued first, such as an analog output initial value, a current slope change range, a current slope step length, time length and the like, after the experiment is started, the changed analog input value is transmitted to an AO port to be output according to a set parameter, and finally, the operation slope parameter and the operation time parameter when the direct current relay protection system generates di/dt actions are mainly contained in a di/dt test register module;
when the function selection parameters receive the self-defined curve test function parameters, the FPGA chip enters the logic of a self-defined curve test unit, the logic is different from an overcurrent/voltage and di/dt test unit, when the function of the self-defined curve is performed, SDRAM (synchronous dynamic random access memory) is needed to store data, namely, before the experiment starting parameters are sent, a system parameter configuration area sends a self-defined curve value first, the test unit writes the received curve values into the SDRAM one after another, after the experiment is started, the data are read out from the SDRAM one after another according to set time points and are finally transmitted to an AO (automatic output) port to be output, and the unit can be used for simulating action fault waveforms of various direct-current relay protection systems so as to observe relay protection responses.
Referring to fig. 4, when the FPGA system logic enters the overcurrent/voltage test unit, the unit logic is in an idle state, and receives the parameter value issued by the system parameter configuration register area and the start signal parameter issued by the waiting common configuration register area in the idle state. When the test unit detects the initial mark, it enters into the mode selection state, the mode selection parameter is issued through the system configuration register region, if it is the automatic mode, i.e. the auto flag is 1, the test unit enters into the parameter update 2 state, updating the current output AO value according to the set change step length and the range in the state, entering the state detection 2 after the completion, starting time counting of each step of change duration in the state and judging whether the current AO value exceeds the maximum value of the set range, when receiving a stop signal parameter (StopFlag ═ 1) issued by the public configuration register area or the current AO value exceeds the set value or receiving an action signal (tripFlag ═ 1) issued by the direct current relay protection, the state jumps to idle, waits for the next start, if the three signals are not received, judging whether the current time meets the requirement of the duration of each step, and if the current time meets the requirement of the duration of each step, entering the state into the parameter updating 2 to update the AO value for the next time; if the manual mode is adopted, namely the manual flag is 1, the test unit enters a parameter updating 1 state, after a current AO output value is updated, the state is jumped to the state detection 1, when a stop signal parameter (StopFlag ═ 1) issued by a public configuration register area is detected or an action signal (tripFlag ═ 1) issued by a direct current relay is received, the state is jumped to idle, the next experiment is waited to start, if the stop signal parameter and the action signal are not issued, whether the AO value parameter issued only by a system parameter configuration area is updated or not is judged, if yes, bufferUpdata ═ 1 is judged, the state is jumped to the parameter updating 1, and the manual mode has no parameter requirements such as each step duration, starting range and the like.
Referring to fig. 5, when the function selection parameter of the common configuration register region receives a di/dt function parameter, the system logic enters a di/dt test unit, the unit logic is initially in an idle state, in which the unit logic receives a di/dt test parameter value issued by the system configuration register, such as a di/dt slope start value, an AO output start value, a di/dt slope change range, a slope per-step duration, a slope per-step length, and other parameters, after receiving the start parameter issued by the common configuration register region, that is, a startflag is equal to 1, a jump is made to an initial start state, a slope per-step duration is started, and then the unit logic enters a state monitor 1, if a stop parameter (that is, a stopflag is equal to 1) is detected in this state or a trip action signal issued by a dc relay (that is, or a current di/dt slope value exceeds a set maximum value, the state jumps to an idle waiting for the next start, otherwise, when the timing reaches the Time1out mark set value, the state jumps to an AO increasing state, the current output AO value in the increasing state increases according to the current di/dt slope value, and returns to the state detection 1 after operation once, if the state monitoring 1 detects that the current timing reaches the slope and the Time set value of each step, namely the Time2out is 1, the state jumps to the state monitoring 2, in the state, the state monitoring 1 is the same, when the stopflag is 1 or the tripflag is 1 or the current slope exceeds the set value, the state jumps to the idle state, otherwise, when the timing reaches the Time1out mark set value, the state jumps to an AO decreasing state, in the decreasing state, the current output AO value decreases according to the current di/dt slope value, returns to the state monitoring 2 after operation once, if the current AO value decreases to the issued start value of the system parameter configuration register, the AO jumps to a di/dtvalue updating state, when the timing reaches the setting value of the flag that Time3out is 1, in the process of jumping to the state monitoring 1, the slope is increased progressively according to the slope step value set by the system parameters, and the output AO value is changed next Time according to the updated slope.
Referring to FIG. 6, when the common register allocation area function selection parameter receives the custom curve function parameter, the system logic enters the custom curve test unit. The method comprises the steps that an initial state is idle, after an output AO value is issued by a system parameter configuration area (namely, writeflag is 1) is detected, unit logic enters a writing state, in the state, an SDRAM address and a current AO value are issued to an SDRAM operation state, meanwhile, the state jumps to a writing response, in the operation state, the AO value is written into the SDRAM according to the issued address, after the operation is completed, a writing response signal (writereply) is returned, in the writing response state, the writing response signal is detected in real time, if a signal returns, the state jumps to idle, and the next AO value is stored; if detecting the initial parameter issued by the public configuration register area in the idle state (namely startflag is 1), the unit logic enters a reading state, in the state, issuing a corresponding address of data to be read to an SDRAM operation state, simultaneously, jumping to a read response state, when receiving the read address in the operation state, immediately reading the corresponding address data, returning a read response signal (readreply) to the read response state, and after detecting a signal mark in the read response state, returning to the idle state to wait for the next data reading operation.
The embodiments of the present invention are preferred embodiments of the present invention, and the scope of the present invention is not limited by these embodiments, so: all equivalent changes made according to the structure, shape and principle of the invention are covered by the protection scope of the invention.
Claims (10)
1. A direct current traction protection tester device based on FPGA is characterized by comprising hardware peripheral resources, a core control panel and a power panel, the power panel is used for supplying power for the tester device, the hardware peripheral resources are connected with the core control panel through double rows of pins, the hardware peripheral resources comprise an analog quantity output module, an analog quantity input module, a switching value input module and a switching value output module, the analog quantity output module is used for converting digital signals sent out under the core control board into analog signals, the analog quantity input module is used for converting the acquired analog quantity into a digital signal and then transmitting the digital signal to the core control panel, the switching value input module is used for capturing the action signal of the device to be tested and transmitting the acquired level change to the core control board, the switching value output module converts the action signal transmitted by the core control panel into a switching action signal and outputs the switching action signal to an external port;
the core control panel comprises a CPU chip, an FPGA chip and an SDRAM memory, the CPU chip and the FPGA chip share the SDRAM memory to realize data reading and writing of the CPU chip to the SDRAM memory, the CPU chip realizes control of the tester device on each test unit in the FPGA chip and reading of test parameters through register configuration, and the core control panel is further provided with a network port communication module which is used for connecting the tester device with a PC end.
2. The FPGA-based DC traction protection tester device according to claim 1, wherein the analog output module comprises an optical coupling isolation module, a digital-to-analog conversion module, and an output conditioning module, the FPGA chip sends a control signal to the optical coupling isolation module, the optical coupling isolation module filters out a high-frequency and electromagnetic interference signal and transmits the signal to the digital-to-analog conversion module, a DAC chip in the digital-to-analog conversion module converts a digital signal into an analog signal and outputs the analog signal to the output conditioning module, and the output conditioning module converts the analog signal into a standard signal.
3. The FPGA-based DC traction protection tester device according to claim 1, wherein the analog input module comprises an optical coupling isolation module, an analog-to-digital conversion module and a switch control module, the analog-to-digital conversion module comprises a programmable ADC chip, the FPGA chip receives information collected by a CPU chip, the FPGA chip sends a control signal to the optical coupling isolation module, the optical coupling isolation module filters out high-frequency and electromagnetic interference signals and transmits the signals to the analog-to-digital conversion module, and the ADC chip in the analog-to-digital conversion module receives the control signal and converts the signals into digital signals, and then transmits the digital signals to the FPGA chip through the optical coupling isolation module.
4. The FPGA-based DC traction protection tester device of claim 3, wherein the switch control module comprises a switch chip, and the CPU chip controls the start and pause of the analog input module by controlling the on/off of the switch chip.
5. The FPGA-based DC traction protection tester device according to claim 1, wherein the switching value input module comprises a photoelectric coupling module and a switching value acquisition module, the switching value acquisition module is responsible for sensing an action signal of the device to be tested, when a high level and a low level change, an action level is immediately output and transmitted to the core control board through the photoelectric coupling module, and after the FPGA chip receives the action signal, the current fault of the device to be tested is judged, and an analog value and an action time of the current fault output are immediately transmitted back to the CPU chip for processing.
6. The FPGA-based DC traction protection tester device according to claim 1, wherein the switching value output module comprises a relay control module and a switching value output module, the CPU chip controls the relay of the relay control module to operate, and the switching value output module outputs an on/off operation level to the external port.
7. The direct current traction protection tester device according to claim 2, wherein the hardware peripheral resources further comprise a small signal (± 600mV) output module connected behind the output quantity conditioning module, and the small signal output module is configured to convert the voltage analog quantity signal (± 10V) into a small signal (± 600mV) for output.
8. The direct-current traction protection tester device according to claim 1, wherein the CPU chip employs STM32F407 series, the FPGA chip employs Cyclone IV E series, and the SDRAM chip employs a 16M memory chip.
9. The direct current traction protection tester device according to claim 1, wherein the core control board further comprises a status indicator light, and the status indicator light is connected with the CPU chip.
10. The FPGA-based DC traction protection tester device of claim 7, wherein the relay control module is mainly composed of a small relay with 10A, 300VDC DC high voltage switching capability.
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