CN106843023A - A kind of electric power data acquisition system based on FPGA - Google Patents
A kind of electric power data acquisition system based on FPGA Download PDFInfo
- Publication number
- CN106843023A CN106843023A CN201510883570.4A CN201510883570A CN106843023A CN 106843023 A CN106843023 A CN 106843023A CN 201510883570 A CN201510883570 A CN 201510883570A CN 106843023 A CN106843023 A CN 106843023A
- Authority
- CN
- China
- Prior art keywords
- module
- data
- eeprom
- fpga
- mixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25314—Modular structure, modules
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The present invention provides a kind of electric power data acquisition system based on FPGA, and the system includes FPGA module, Analog Data Acquistion Module, mixed-media network modules mixed-media, EEPROM module and switching value acquisition module；The Analog Data Acquistion Module is used to send the FPGA module to after analog input signal is processed；The switching value acquisition module is used to send the FPGA module to after on-off model is processed；The FPGA module is used to process the analog input signal and the on-off model；The EEPROM module is used to store the configuration information of the mixed-media network modules mixed-media, and the mixed-media network modules mixed-media is used to realize system and extraneous transmission data.It is master devices that the present invention uses FPGA, substantially increase the precision of speed and the A/D conversion of data acquisition, the features such as system has simple design, low cost, low in energy consumption and small volume, can carry out live modification according to different requirements, increase success rate and the flexibility of system design.
Description
Technical field
The present invention relates to a kind of electric power data acquisition system, and in particular to a kind of electric power data acquisition system based on FPGA.
Background technology
China's rapid development of economy has driven every profession and trade to the wilderness demand of electric power, therefore, in the urgent need to supply of electric power
The management of the science of carrying out, the basic link that electric power data acquisition system is managed as power supply and demand, plays an important role,
The development of power system is proposed requirement higher to the accuracy of electric power data acquisition system, real-time and reliability.
Traditional design method is changed by the A/D that software control data is gathered using MCU or DSP, so will
The operation of system is frequently interrupted, so that the data operation ability of attenuation systems, the speed of data acquisition is also restrained.With
MCU is compared with DSP, and FPGA has a clear superiority in terms of Multi-Channel Parallel Acquisition.Single-chip microcomputer receives instruction cycle and place
Manage the influence of speed, it is difficult to which the array to multiple passages, A/D compositions is controlled, and its highway width is limited, for
For multi-channel data acquisition, there is the not enough bottleneck of data bandwidth.According to multiple single-chip microcomputer parallel forms, then make again
Into system complex, the fatal defects such as power consumption is high, volume is big.Although DSP can realize the data acquisition of higher speed,
While its speed is improved, also increasing the various functions of the hardware cost of system, particularly DSP needs by software
Operation realizes that its time loss proportion in the whole sampling time is bigger than normal, therefore its speed for performing and efficiency are not
It is high.
The content of the invention
In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a kind of electric power data acquisition system based on FPGA,
The present invention increases success rate and the flexibility of system design by introducing FPGA module, and with low in energy consumption, volume
Small the advantages of.
In order to realize foregoing invention purpose, the present invention is adopted the following technical scheme that：
A kind of electric power data acquisition system based on FPGA, the system includes FPGA module, analog data collection
Module, mixed-media network modules mixed-media, EEPROM module and switching value acquisition module；The Analog Data Acquistion Module is used for mould
The FPGA module is sent to after intending input signal treatment；The switching value acquisition module is used to process on-off model
After send the FPGA module to；The FPGA module is used to process the analog input signal and switching value letter
Number；The EEPROM module is used to store the configuration information of the mixed-media network modules mixed-media, and the mixed-media network modules mixed-media is used to realize system
With external world's transmission data.
Preferably, the acquisition system also includes GPS module, and the GPS module is used to obtain temporal information, there is provided string
Mouth pulse per second (PPS) and 10ms pulses.
Preferably, the Analog Data Acquistion Module is used to use 4 16 8 passage motor synchronizing analog converters, and
Integrated simulation input clamping protection, second order frequency overlapped-resistable filter, tracking hold amplifier, 16 Charge scalings are gradually forced
Plesiotype ADC kernels, digital filter, 2.5V reference voltage sources and buffering, high speed serialization and parallel interface.
Preferably, the mixed-media network modules mixed-media has been internally integrated ICP/IP protocol stack, ethernet mac layer and PHY layer, supports
8 independent Socket communications, the transmission/reception buffering area of internal 128K bytes quickly carries out data exchange, in TCP
Under agreement, network rate is up to 80Mbps.
Preferably, the FPGA module includes that Data correction module, time control module, AD control modules, collection are surveyed
Amount module, SDU group bags module, PDU group bags module, data migration module, ethernet control module and EEPROM
Control module, the AD control modules are used to obtain the analog input signal；The Data correction module is used to utilize
Correction factor obtains final analogue data after being corrected to the analog input signal；The collection measurement module is used for
Gather the on-off model；The SDU groups bag module be used for by the GPS module provide temporal information, it is described most
Whole analogue data and on-off model composition Service Data Unit SDU；The PDU groups bag module is by described in multiple
SDU constitutes a protocol Data Unit PDU；The data migration module is used for the PDU data bag content and number
Content First Input First Output Data FIFO and byte length First Input First Output Size FIFO are respectively written into according to byte length；
The ethernet control module is used to obtain network configuration information and send the PDU data by network interface,
The time control module is sampled by counter controls AD and the SDU packets are sent to the sequential of module；It is described
EEPROM control modules are used to read the configuration information of the EEPROM module and write command to the EEPROM
Module.
Preferably, the AD control modules include starting control module, for being configured according to different sample frequencys, to
A/D chip sends sampling marker pulse；Postpone control module and delay control for data, the data that will be collected simultaneously are led to
Delay control is crossed, allows it to stagger in time；S2P modules are used to for AD sampled datas to carry out serial-to-parallel 16 changes
Change.
Preferably, the collection measurement module includes frequency test module, according to 4 drive test frequency signals, by counter control
Frequency input signal processed, by 4 Counter Value packing write-in SDU data of 32bit；I/O channel signal is controlled
Module, for the on-off model to be input into by DI passages, is exported by DO passages.
Preferably, the EEPROM control modules include that EEPROM interface control module, EEPROM data write
Module and EEPROM data read modules, the FPGA module and described during the EEPROM interface control module
The interface module of EEPROM module；The EEPROM Data write. modules write enable it is effective when, by write order, write
Address and write during data write the EEPROM module by serial mode；When reading to enable effective, by read command, read
Address is write in the EEPROM module by serial mode；The EEPROM data read modules, for from institute
State the configuration information that AD correction factors and the mixed-media network modules mixed-media are read out in EEPROM module.
Compared with prior art, the beneficial effects of the present invention are：
It is master devices that the present invention uses FPGA, substantially increases the precision of speed and the A/D conversion of data acquisition, should
The features such as system has simple design, low cost, low in energy consumption and small volume, can repair according to the different requirement scenes of carrying out
Change, increase success rate and the flexibility of system design.
Brief description of the drawings
Fig. 1 is a kind of structure chart of electric power data acquisition system based on FPGA that the present invention is provided
Fig. 2 is the structure chart of FPGA module in the electric power data acquisition system that the present invention is provided
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.
As shown in figure 1, a kind of electric power data acquisition system based on FPGA, including FPGA module, analog data
Acquisition module, mixed-media network modules mixed-media, EEPROM module, switching value acquisition module and GPS module.
With FPGA as core, analog input signal is processed the system by Analog Data Acquistion Module, by data signal
Export to FPGA；The on-off model of input is exported to FPGA by after switching value acquisition module treatment.In FPGA
Analog signal and on-off model to gathering are processed, and temporal information is obtained using GPS module, use EEPROM
Module stores the configuration information of mixed-media network modules mixed-media, and system and extraneous transmission data are realized eventually through network interface.
1st, FPGA module
As shown in Fig. 2 FPGA module includes：Data correction module, time control module, AD control modules, collection
Measurement module, SDU group bags module, PDU group bags module, data migration module, ethernet control module and EEPROM
Control module.Data correction module is obtained after analogue data is corrected to AD control modules using correction factor and obtained most
Whole analogue data.Temporal information, final analogue data and collection measurement module that SDU group bag modules provide GPS
The on-off model for obtaining constitutes Service Data Unit (SDU).PDU group bag modules are by SDU data packet groups into protocol data
Unit (PDU), by data migration module by PDU data bag through giving ethernet control module.Ethernet control module
Network configuration information is obtained from EEPROM control modules, and PDU data is sent by network interface.
1.1st, AD control modules
This module is the control module of A/D chip, including starts control module, postpones control module and S2P modules.It is real
Existing major function is：Configured according to different sample frequencys, sampling marker pulse is sent to A/D chip；Read AD
Sampled data, and make serial-to-parallel 16 bit map；Data delay control, the data that will be collected simultaneously, by postponing
Control, allows them to stagger in time；The AD sampled datas of non-natural order are converted into natural order (according to passage
It is number ascending) AD sampled datas.
1.2nd, measurement module is gathered
The module includes frequency test module and I/O channel signal control module.Frequency measuring block major function is according to 4
Drive test frequency signal, frequency input signal is measured by counter controls, by 4 Counter Value packing write-in SDU of 32bit
In data；I/O channel signal control module major function is that the switching value data of input is input into by DI passages, is written into
It is transmitted in SDU packets；Host computer sends output switch amount data and completes output switch amount data by DO passages
Output.
1.3rd, SDU groups bag module
The module major function is to set up the pack arrangement of SDU data.SDU group bag modules are surveyed from AD control modules, collection
Amount module and GPS module obtain data below：
1) AD sampled datas：AD sampled datas, most 32 tunnels；
2) input switch amount：Most 16 tunnels；
3) frequency counting：Most 4 tunnels；
4) GPS time information：Year, month, day, hour, min, second.
These data are continuously transmitted by 16 bit data bus.In fact, the module is not it should be understood that data content,
Control field is added after data only need to be received, by AD sampled datas, switching value, and frequency count data merge
Into a continuous data block, complete SDU is set up.Then add SDU field, data structure description field and
GPS time information.
1.4th, PDU groups bag module
This module major function is to set up PDU.In order to improve efficiency of transmission, multiple SDU are constituted into a PDU, PDU
To be transmitted as the load of IP network.The data of PDU mainly include：Head field, sequence number, length, SDU quantity,
SDU length, PDU types.
Host computer can at any time by the data structure of configuration change SDU.So it is possible to be included in a PDU
The different SDU of various structures.Obviously, it is unfavorable so for building on parsing PDU, realizes that difficulty is larger.So,
Such situation should be avoided to occur in design.Ensure SDU integralities first, when configuration change, when SDU's
Make configuration take-effective when counter is zero again.Ensure PDU uniformity, after parameter change, will when next SDU arrives
The SDU historical datas of caching are packaged into PDU.Next PDU is packaged according to the SDU that new parameter is generated.
1.5th, data migration module
This module major function is to call the First Input First Output (FIFO) in IP core (IP kernel), according to PDU data
Content design Data FIFO, Size FIFO are designed according to PDU data byte length；Write by producing corresponding FIFO
Request signal, PDU data bag content and data byte length are respectively written into Data FIFO and Size FIFO；Root
Sending data according to mixed-media network modules mixed-media needs, and produces corresponding FIFO read requests to read PDU data in ethernet control module
Bag data and byte length.So design sends data packet messages angle and says from actual Transmission Control Protocol, can solve sending
The packet loss problem caused due to waiting ACK overlong time during data message.
1.6th, ethernet control module
The initialization of mixed-media network modules mixed-media, three steps of initialization are completed during the major function of the module：HPI setting,
The network information sets the distribution with inside TX/RX memories, the middle configuration related register in the mif files of ROM
Address and data.
In code chip selection signal by write enable and read enable control, when write enable it is effective when, write register address and
Data；When reading to enable effective, the address of correspondence register is read.Due to the particularity of mixed-media network modules mixed-media read-write sequence,
During write operation, piece select CS must at least continue 50ns low levels.And after the completion of a write operation, it is necessary to piece is selected
CS signals put high level and continue at least 28ns, and write operation next time or read operation are then carried out again；During read operation,
Piece select CS must at least continue 65ns low levels.And after the completion of a read operation, it is necessary to select CS signals to put high level piece
Continue at least 28ns, write operation next time or read operation are then carried out again.
1.7th, EEPROM control modules
The module includes that EEPROM interface control module, EEPROM Data write. modules and EEPROM data are read
Modulus block.Wherein EEPROM interface control module is the interface module of FPGA and EEPROM module, the master of realization
It is that the configuration information of AD correction factors and W5300 is read out from EEPROM to want function, there is provided made to other modules
With.Concrete function is as follows：
1) work clock, the chip selection signal of EEPROM are produced；
2) the busy Busy signals of EEPROM states are produced, control is written and read by Busy signal designations；
3) write enable it is effective when, by write order, write address and write data by serial mode write-in EEPROM in；
4) when reading to enable effective, by read command, address is read by serial mode write-in EEPROM.
1.8th, Data correction module
The module major function is that AD sampled datas do computing with corresponding AD correction factors, and the data after correction are write
In entering SDU packets.The AD sampled datas and correction factor of 16bit are carried out into data Bits Expanding first, is changed into
17bit；Then suitable correction calculation parameter is selected, AD sampled datas and correction factor is done into subtraction treatment, warp
The data value crossed after computing：A high position is 0, then according to positive correction parameter correction；A high position is 1, then according to negative correction parameter school
Just.Finally will complete correction after AD sampled datas write-in SDU packets in.
1.9th, time control module
This module is sampled and SDU packet sending module sequential by counter controls AD.When mixed-media network modules mixed-media receives upper
When machine data are completed, AD sampled point count values are locked, and start to count sample counter, when count value reaches
After certain value, produce AD samplings to enable signal and give AD_inf modules；Regular hour time delay is done according to AD samplings, when
AD starts to count transmitting counter after starting sampling, after reaching regulation delay count value, produces and sends enable signal, and
Carry out SDU data group bags.
2nd, Analog Data Acquistion Module
This module uses 4 A/D chips, realizes 32 circuit-switched data acquisition functions.A/D chip be a kind of 16 8 passages from
Synchronized AD converter, on piece integrated simulation input clamping protection, second order frequency overlapped-resistable filter, tracking hold amplifier,
16 Charge scaling SAR ADC kernel, digital filter, 2.5V reference voltage sources and buffering, high speeds are gone here and there
Row and parallel interface.AD7606 is powered using 5V single supplies, it is no longer necessary to negative and positive dual power, and supports real ± 10V
Or the bipolar signal of ± 5V is defeated.All of passage can be sampled with being up to the speed of 200kSPS, while input
Clamp protection circuits can bear the voltage of up to ± 16.5V.With cost performance is high, high precision, energy consumption be low, conversion is fast
The advantages of spending fast, is particularly suitable for the measurement of relay protection data.
3rd, mixed-media network modules mixed-media
In order to more intuitively monitor electric power data acquisition, system needs the data for collecting to be uploaded to the PC of control centre,
Computer networking shared data has been also convenient for it simultaneously.The inside modules be integrated with high mature ICP/IP protocol stack, with
Too network MAC layer and PHY layer etc., support 8 independent Socket communications, the transmission/reception of internal 128K bytes
Buffering area can quickly carry out data exchange, and under Transmission Control Protocol, network rate highest can reach 80Mbps.The module branch
The data/address bus of 8/16 is held, can be attached using parallel mode connected directly or indirectly.It is greatly
The workload of hardware interface design and network programming is reduced, and the remote data communication of reliable and stable operation can be realized
System.
4th, EEPROM module
EEPROM module is from the 25AA640 of Microchip companies, and the chip capacity is 64K, serial using SPI
Bus transfer data, maximum clock frequency is 1MHz.Correction factor when wherein storage AD samples, for FPGA corrections
Adc data.
5th, on-off value data acquisition module
Due to FPGA IO voltages be 3.3V, so on-off model need to via voltage conversion chip carry out voltage conversion it
FPGA is just can connect to afterwards.The system employs 2 SN74ALVC164245 and 1 SN74AVC4T245PW
Chip realizes the voltage conversion of 5V and 3.3V, and realizes 16 input and output of way switch and 4 road frequency countings.
6th, GPS module
GPS module as can arrangement, Main Function for provide temporal information.GPS provides serial ports pulse per second (PPS) or 10ms
Pulse, FPGA safeguards the markers of higher precision accordingly, and resolution ratio is 10us, and precision is 1us.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention rather than its limitations, although
The present invention is described in detail with reference to above-described embodiment, those of ordinary skill in the art should be understood：Still
Specific embodiment of the invention can be modified or equivalent, and appointing without departing from spirit and scope of the invention
What modification or equivalent, it all should cover in the middle of scope of the presently claimed invention.
Claims (8)
1. a kind of electric power data acquisition system based on FPGA, it is characterised in that the system include FPGA module,
Analog Data Acquistion Module, mixed-media network modules mixed-media, EEPROM module and switching value acquisition module；The FPGA module with
The Analog Data Acquistion Module, the mixed-media network modules mixed-media, the EEPROM module and the switching value acquisition module it
Between to be bi-directionally connected；The Analog Data Acquistion Module is used to send the FPGA to after analog input signal is processed
Module；The switching value acquisition module is used to send the FPGA module to after on-off model is processed；The FPGA
Module is used to process the analog input signal and the on-off model；The EEPROM module is used to store the net
The configuration information of network module, the mixed-media network modules mixed-media is used to realize system and extraneous transmission data.
2. acquisition system according to claim 1, it is characterised in that the acquisition system also includes GPS module, institute
GPS module is stated for obtaining temporal information, there is provided serial ports pulse per second (PPS) and 10ms pulses.
3. acquisition system according to claim 1, it is characterised in that the Analog Data Acquistion Module is used to use
4 16 8 passage motor synchronizing analog converters, and integrated simulation input clamping protection, second order frequency overlapped-resistable filter, with
Track hold amplifier, 16 Charge scaling SAR ADC kernels, digital filter, 2.5V reference voltage sources
And buffering, high speed serialization and parallel interface.
4. acquisition system according to claim 1, it is characterised in that the mixed-media network modules mixed-media has been internally integrated TCP/IP
Protocol stack, ethernet mac layer and PHY layer, support 8 independent Socket communications, the hair of internal 128K bytes
Sending/receive buffering area quickly carries out data exchange, and under Transmission Control Protocol, network rate is up to 80Mbps.
5. acquisition system according to claim 2, it is characterised in that the FPGA module include Data correction module,
Time control module, AD control modules, collection measurement module, SDU group bags module, PDU group bags module, data turn
Shifting formwork block, ethernet control module and EEPROM control modules, the AD control modules are defeated for obtaining the simulation
Enter signal；The Data correction module is used to obtain final after being corrected the analog input signal using correction factor
Analogue data；The collection measurement module is used to gather the on-off model；The SDU groups bag module is used for institute
Temporal information, the final analogue data and the on-off model composition Service Data Unit of GPS module offer are provided
SDU；Multiple SDU are constituted a protocol Data Unit PDU by the PDU groups bag module；The data transfer
Module is used to for the PDU data bag content and data byte length to be respectively written into content First Input First Output Data FIFO
With byte length First Input First Output Size FIFO；The ethernet control module is used to obtain network configuration information and by institute
State PDU data to be sent by network interface, the time control module is sampled and described by counter controls AD
SDU packets are sent to the sequential of module；The EEPROM control modules are used to read the EEPROM module
Configuration information and write command to the EEPROM module.
6. acquisition system according to claim 5, it is characterised in that the AD control modules include starting control mould
Block, for being configured according to different sample frequencys, sampling marker pulse is sent to A/D chip；Postponing control module is used for
Data delay control, the data that will be collected simultaneously, by postponing control, allow it to stagger in time；S2P modules are used for
AD sampled datas are carried out into serial-to-parallel 16 bit map.
7. acquisition system according to claim 5, it is characterised in that the collection measurement module includes frequency test mould
Block, according to 4 drive test frequency signals, by counter controls frequency input signal, the Counter Value packing of 4 32bit is write
In entering the SDU data；I/O channel signal control module, for the on-off model to be input into by DI passages,
Exported by DO passages.
8. acquisition system according to claim 5, it is characterised in that the EEPROM control modules include
EEPROM interface control module, EEPROM Data write. modules and EEPROM data read modules, it is described
The interface module of the FPGA module and EEPROM module during EEPROM interface control module；It is described
EEPROM Data write. modules write enable it is effective when, by write order, write address and write data by serial mode write
In the EEPROM module；When reading to enable effective, by read command, read address by described in serial mode write-in
In EEPROM module；The EEPROM data read modules, for reading out AD from the EEPROM module
The configuration information of correction factor and the mixed-media network modules mixed-media.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510883570.4A CN106843023B (en) | 2015-12-03 | 2015-12-03 | A kind of electric power data acquisition system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510883570.4A CN106843023B (en) | 2015-12-03 | 2015-12-03 | A kind of electric power data acquisition system based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106843023A true CN106843023A (en) | 2017-06-13 |
| CN106843023B CN106843023B (en) | 2019-08-06 |
Family
ID=59148798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510883570.4A Expired - Fee Related CN106843023B (en) | 2015-12-03 | 2015-12-03 | A kind of electric power data acquisition system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106843023B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109521719A (en) * | 2019-01-14 | 2019-03-26 | 深圳灿态信息技术有限公司 | Intelligent collector |
| CN109782209A (en) * | 2019-03-11 | 2019-05-21 | 上海精密计量测试研究所 | Pulse power calibration factor calibration method |
| CN111722031A (en) * | 2020-05-13 | 2020-09-29 | 广州市扬新技术研究有限责任公司 | Direct current traction protection tester device based on FPGA |
| CN113742268A (en) * | 2021-09-14 | 2021-12-03 | 北京坤驰科技有限公司 | High-speed pulse acquisition system based on Ethernet optical fiber |
| CN114019850A (en) * | 2021-10-18 | 2022-02-08 | 中国舰船研究设计中心 | Auxiliary equipment IO signal modular processing device of boats and ships |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350036A (en) * | 2008-08-26 | 2009-01-21 | 天津理工大学 | High speed real-time data acquisition system |
| CN102253295A (en) * | 2011-06-03 | 2011-11-23 | 安徽继远电网技术有限责任公司 | High-speed data acquiring and digital signal processing board based on FPGA (Field Programmable Gate Array) |
| CN203054841U (en) * | 2012-12-20 | 2013-07-10 | 北汽福田汽车股份有限公司 | Data collection and transmission device |
| CN103389670A (en) * | 2013-07-31 | 2013-11-13 | 成都电业局双流供电局 | Data acquisition and power monitoring device for transformer station |
| CN104570855A (en) * | 2014-12-18 | 2015-04-29 | 文曲 | FPGA-based data acquisition system and method |
-
2015
- 2015-12-03 CN CN201510883570.4A patent/CN106843023B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350036A (en) * | 2008-08-26 | 2009-01-21 | 天津理工大学 | High speed real-time data acquisition system |
| CN102253295A (en) * | 2011-06-03 | 2011-11-23 | 安徽继远电网技术有限责任公司 | High-speed data acquiring and digital signal processing board based on FPGA (Field Programmable Gate Array) |
| CN203054841U (en) * | 2012-12-20 | 2013-07-10 | 北汽福田汽车股份有限公司 | Data collection and transmission device |
| CN103389670A (en) * | 2013-07-31 | 2013-11-13 | 成都电业局双流供电局 | Data acquisition and power monitoring device for transformer station |
| CN104570855A (en) * | 2014-12-18 | 2015-04-29 | 文曲 | FPGA-based data acquisition system and method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109521719A (en) * | 2019-01-14 | 2019-03-26 | 深圳灿态信息技术有限公司 | Intelligent collector |
| CN109521719B (en) * | 2019-01-14 | 2023-09-26 | 深圳灿态信息技术有限公司 | Intelligent collector |
| CN109782209A (en) * | 2019-03-11 | 2019-05-21 | 上海精密计量测试研究所 | Pulse power calibration factor calibration method |
| CN111722031A (en) * | 2020-05-13 | 2020-09-29 | 广州市扬新技术研究有限责任公司 | Direct current traction protection tester device based on FPGA |
| CN113742268A (en) * | 2021-09-14 | 2021-12-03 | 北京坤驰科技有限公司 | High-speed pulse acquisition system based on Ethernet optical fiber |
| CN113742268B (en) * | 2021-09-14 | 2023-12-08 | 北京坤驰科技有限公司 | High-speed pulse acquisition system based on Ethernet optical fiber |
| CN114019850A (en) * | 2021-10-18 | 2022-02-08 | 中国舰船研究设计中心 | Auxiliary equipment IO signal modular processing device of boats and ships |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106843023B (en) | 2019-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106843023A (en) | A kind of electric power data acquisition system based on FPGA | |
| CN202870808U (en) | FPGA realization device of SPI serial port module | |
| CN201859537U (en) | Multifunctional bandwidth power carrier concentrator | |
| CN103218323B (en) | A kind of high-speed data acquisition and transmitting device | |
| CN103425614B (en) | Synchronous serial data dispensing device and method thereof for Single Chip Microcomputer (SCM) system | |
| CN109583013B (en) | Active power distribution network real-time simulator output module design method based on FPGA | |
| CN101726708B (en) | Battery voltage data acquisition system | |
| CN203551796U (en) | Network system for measuring three-dimensional resistivity data | |
| CN104267312B (en) | A kind of embedded traveling wave ranging device based on LVDS high-speed sampling | |
| CN104730328A (en) | Intelligent wireless voltage collecting instrument | |
| CN103454687B (en) | Three-dimensional electrical resistivity data measurement network system and addressing method thereof | |
| CN102368611B (en) | Board card for flexible alternating-current power transmission device | |
| CN107015496A (en) | A kind of intelligent data acqusition system and device | |
| CN205081867U (en) | Video acquisition circuit based on CPLD disposes multi -disc video decoder | |
| CN107491009A (en) | A kind of angular transducer signal synchronous collection method | |
| CN207529165U (en) | A kind of electric network data handles acquisition system | |
| CN102355264B (en) | A kind of analog to digital conversion circuit for portable electric energy monitoring device | |
| CN203192220U (en) | Intelligent meter reading concentrator | |
| CN205485457U (en) | Intelligent data acquisition system and device | |
| CN202979026U (en) | Industrial-Ethernet multi-function double serial port server based on MCF52233 chip | |
| CN207440998U (en) | A kind of meter reading terminal based on low-power consumption Internet of Things | |
| CN203340053U (en) | Device using FPGA to achieve synchronization of multi-channel serial ADC | |
| CN113051200A (en) | Double-path-based data acquisition parallel data transmission and storage device and method | |
| CN202059410U (en) | Electrical network concentrator | |
| CN202171606U (en) | Power system electricity quantity collector time-sharing collection switching device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190806 Termination date: 20211203 |