CN204256325U

CN204256325U - Realize the MIPI module group test system of two kinds of patterns

Info

Publication number: CN204256325U
Application number: CN201420718970.0U
Authority: CN
Inventors: 彭骞; 邹峰; 雷程程; 陈凯; 沈亚非
Original assignee: Wuhan Jingce Electronic Technology Co Ltd
Current assignee: Wuhan Jingce Electronic Technology Co Ltd
Priority date: 2014-11-25
Filing date: 2014-11-25
Publication date: 2015-04-08
Anticipated expiration: 2024-11-25

Abstract

The utility model discloses a kind of MIPI module group test system realizing two kinds of patterns, comprise PG pictcure generator, MCU and FPGA, PG pictcure generator is connected with MCU and FPGA respectively, MCU and FPGA is connected by EBI interface, MCU is connected by SPI interface with bridging chip, FPGA is connected with MIPI module by bridging chip, and the utility model can realize the some screen test of VIDEO pattern and COMMAND pattern two kinds of pattern MIPI modules; Except basic some screen test function, the Vcom that the technical program provides COMMAND pattern MIPI module regulates, module ID reads and preserve, the multiple test function such as MTP data edition and burning, adapted to the multiple demand in MIPI production run.

Description

Realize the MIPI module group test system of two kinds of patterns

Technical field

The utility model belongs to display field and the technical field of measurement and test of liquid crystal module, refers to a kind of MIPI module group test system realizing two kinds of patterns particularly.

Background technology

The display screen with MIPI interface is widely used in the modern electronic equipment such as smart mobile phone, flat board.Show in the large-scale production run of module at MIPI, configuration testing before MIPI module dispatches from the factory is a very important link, need to use the technology reading and arrange MIPI module internal register, carried out the production procedures such as some screen test, Vcom adjustment, MTP burning.The signal of input is sent to the MIPI module displays of VIDEO pattern or COMMAND pattern by inner changing the mechanism by bridging chip under VIDEO pattern or COMMAND pattern.VIDEO pattern refers to that Host Transfer arrives liquid crystal module and adopts real-time pixel stream, and is the pattern with high-speed signal transmission, and COMMAND pattern refers to adopt and sends order and data to the pattern of signal transmission of controller with display buffer.

Present stage MIPI module group test system is only applicable to the MIPI module of VIDEO pattern, the scheme be configured bridging chip adopts SPI passage and RGB data passage two autonomous channels transformation parameter configuration data and view data respectively, but, when bridging chip works in COMMAND pattern, it is in closed condition for the SPI interface transmitting configuration parameter, and therefore current MIPI module group test system can not carry out the some screen test of COMMAND pattern MIPI module.

Summary of the invention

For defect of the prior art, the utility model proposes the some screen test that can complete VIDEO pattern and COMMAND pattern two kinds of MIPI modules, and the MIPI module group test system realizing two kinds of patterns of the functions such as Vcom adjustment, module ID setting, the burning of MTP information can be carried out the MIPI module of COMMAND pattern.

For achieving the above object, a kind of test macro realizing two kinds of pattern MIPI signals designed by the utility model, its special character is, comprise PG pictcure generator, MCU and FPGA, described PG pictcure generator is connected with MCU and FPGA respectively, described MCU and FPGA is connected by EBI interface, described MCU is connected by SPI interface with bridging chip, described FPGA is connected with MIPI module by bridging chip, described PG pictcure generator is used for the register configuration parameter and the view data that arrange VIDEO pattern or COMMAND pattern according to the type of MIPI module, and the register configuration parameter of VIDEO pattern or COMMAND pattern is sent to MCU, the view data of VIDEO pattern or COMMAND pattern is sent to FPGA, described MCU is used for the register configuration parameter of VIDEO pattern being converted into DCS instruction and being sent to bridging chip by SPI interface, the register configuration parameter of COMMAND pattern is converted into DCS instruction and is sent to FPGA by EBI interface, described FPGA is used for the view data of VIDEO pattern being sent to bridging chip by rgb interface, is sent to bridging chip after the DCS instruction of COMMAND pattern and view data being packed.

Further, described FPGA comprises VIDEO mode data processing module, image interface circuit, EBI module, COMMAND mode data processing module and sequential interface circuit, described VIDEO mode data processing module is sent to image interface circuit after PG pictcure generator receives the image real time transfer of VIDEO pattern, the view data of VIDEO pattern is sent to bridging chip by described image interface circuit, the DCS instruction of the COMMAND pattern received from MCU is sent to sequential interface circuit by described EBI module, described COMMAND mode data processing module is sent to sequential interface circuit after PG pictcure generator receives the image real time transfer of COMMAND pattern, described sequential interface circuit is sent to bridging chip after the DCS instruction of COMMAND pattern and view data being packed.

Further, described FPGA arranges the IFSEL pin of bridging chip by GPIO interface, and when level is low, bridging chip works in VIDEO pattern, and when level is high, bridging chip works in COMMAND pattern.

The beneficial effects of the utility model are:

(1) the some screen test of VIDEO pattern and COMMAND pattern two kinds of pattern MIPI modules can be realized;

(2) for the MIPI module of COMMAND pattern, by FPGA image data generating, MCU forwards the register configuration parameter of MIPI module by FPGA, can realize register configuration parameter and view data sends at same passage, improves transfer efficiency;

(3) multi-functional: except basic some screen test function, the Vcom that the technical program provides COMMAND pattern MIPI module regulates, module ID reads and preserve, the multiple test function such as MTP data edition and burning, adapted to the multiple demand in MIPI production run.

Accompanying drawing explanation

Fig. 1 is the structural representation that the utility model realizes the test macro of two kinds of pattern MIPI signals.

In figure: 1.PG pictcure generator, 2.MCU, 3.FPGA, 3-1.VIDEO mode data processing module, 3-2. image interface circuit, 3-3.EBI module, 3-4.COMMAND mode data processing module, 3-5. sequential interface circuit, 4. bridging chip, 5.MIPI module.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

As shown in Figure 1, a kind of test macro realizing two kinds of pattern MIPI signals of the utility model, comprise PG pictcure generator 1, MCU2 and FPGA3, PG pictcure generator 1 is connected with MCU2 and FPGA3 respectively, MCU2 and FPGA3 is connected by EBI interface, MCU2 is connected by SPI interface with bridging chip 4, and FPGA3 is connected with MIPI module 5 by bridging chip 4.

PG pictcure generator 1 is for arranging register configuration parameter and the view data of VIDEO pattern or COMMAND pattern according to the type of MIPI module 5, and by 485 interfaces, the register configuration parameter of VIDEO pattern or COMMAND pattern is sent to MCU2, the view data of VIDEO pattern or COMMAND pattern is sent to FPGA3 by LVDS interface.

MCU2 is used for the register configuration parameter of VIDEO pattern being converted into DCS instruction and being sent to bridging chip 4 by SPI interface, the register configuration parameter of COMMAND pattern is converted into DCS instruction and is sent to FPGA3 by EBI interface.

FPGA3 is used for, in VIDEO pattern, view data is sent to bridging chip 4 by rgb interface, after DCS instruction and view data are packed by COMMAND pattern, be sent to bridging chip 4.

FPGA3 comprises VIDEO mode data processing module 3-1, image interface circuit 3-2, EBI module 3-3, COMMAND mode data processing module 3-4 and sequential interface circuit 3-5, VIDEO mode data processing module 3-1 is sent to image interface circuit 3-2 after the image real time transfer of the LVDS interface VIDEO pattern of PG pictcure generator 1, the view data of VIDEO pattern is sent to bridging chip 4 by image interface circuit 3-2, the DCS instruction of the COMMAND pattern received from MCU2 is sent to sequential interface circuit 3-5 by EBI module 3-3, COMMAND mode data processing module 3-4 is sent to sequential interface circuit 3-5 after the image real time transfer of the LVDS interface COMMAND pattern of PG pictcure generator 1, sequential interface circuit 3-5 is sent to bridging chip 4 after the DCS instruction of COMMAND pattern and view data being packed.Bridging chip 4 completes to configure and show view data according to DCS instruction and realizes some screen.

The concrete steps that the MIPI module utilizing above-mentioned test macro to complete two kinds of patterns is tested are as follows:

MIPI module is that the performing step under VIDEO pattern is as follows:

1) PG pictcure generator 1 obtains register configuration parameter and the view data of VIDEO pattern from upper layer software (applications).

2) the register configuration parameter of VIDEO pattern is sent to MCU2 by PG pictcure generator 1, and the view data of the VIDEO pattern transmitted continuously is sent to FPGA3.

3) the register configuration parameter of VIDEO pattern is converted into DCS instruction and is sent to bridging chip 4 by SPI interface by MCU2, and the MIPI D0 passage that DCS instruction is sent to MIPI module 5 by bridging chip 4 completes the transmission of configuration parameter.FPGA3 sends bridging chip 4 to by rgb interface after the view data that the LVDS data bus interface (LVDS Data Bus Interface) from PG pictcure generator 1 receives is converted into TTL signal, view data is converted into MIPI signal and is sent to MIPI module 5 by bridging chip 4, MIPI module 5 shows the view data of MIPI signal, and the test of some screen completes.

MIPI module is that the performing step under COMMAND pattern is as follows:

1) PG pictcure generator 1 obtains register configuration parameter and the view data of COMMAND pattern from upper layer software (applications).

2) the register configuration parameter of COMMAND pattern is sent to MCU2 by PG pictcure generator 1, and the view data of the COMMAND pattern of discontinuous transmission is sent to FPGA3, the register configuration parameter of COMMAND pattern is converted into DCS instruction and is sent to FPGA3 by EBI interface by MCU2.

5) FPGA3 receives the view data of COMMAND pattern by LVDS data bus interface (LVDS Data Bus Interface), then is sent to bridging chip 4 after DCS instruction and view data being packed; Bridging chip 4 sends DCS instruction configuration MIPI module 5 to MIPI module 5, and is sent to MIPI module 5, MIPI module 5 after the view data of COMMAND pattern is converted into MIPI signal according to MIPI Signal aspects view data, and test completes.

Vcom regulates testing procedure: MCU2 to forward to bridging chip 4 the Vcom register parameters that DCS instruction regulates MIPI module 5 by FPGA3, makes screen flicker degree minimum.Vcom register belongs to the internal register of MIPI module 5, is used for the film flicker effect of MIPI module 5, can first read Vcom parameter, regulate Vcom numerical value, make the flicker level of picture minimum at upper layer software (applications) by +/-by reading order.

Module ID, Gamma parameter of MIPI module 5, Vcom parameter and Power parameter are converted into DCS instruction and are sent to bridging chip 4 by FPGA3 by MTP burning step: MCU2, received module ID, Gamma parameter, Vcom parameter and Power parameter are sent to MIPI module 5 according to DCS instruction by bridging chip 4, and are burned onto the OTP region of MIPI module 5 by module burning flow process.MIPI module 5 provides one piece of OTP region and can be used for preserving module ID, Gamma parameter, Vcom parameter, Power parameter, by arranging corresponding parameter at upper layer software (applications), and be issued to MIPI module 5, then module register is set by specific order, parameter can be burnt to OTP region, after power-down rebooting, corresponding parameter can read the corresponding registers of MIPI module 5 automatically from OTP region.

Read module ID step: MCU2 forwarded to bridging chip 4 by FPGA3 the OTP region of DCS instruction fetch MIPI module 5 module ID, Gamma parameter, Vcom parameter is with Power parameter and one by one compared with setting value, if identical, test terminates; If different, repeat MTP burning step.At host computer by DCS instruction fetch module ID, the keeping records of every block MIPI module 5 programming parameters can be realized, be convenient to analytic statistics module information.There is provided comparing window at host computer, MCU2 turns back to upper strata after the inner parameter reading MIPI module 5, guarantees desired parameters correctly burning, avoids occurring this burning and not burning, and detects the situation of burning mistake in time.

The above is only preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the utility model principle; can also design some improvement, these improvement also should be considered as protection domain of the present utility model.

Claims

1. one kind realizes the MIPI module group test system of two kinds of patterns, it is characterized in that: comprise PG pictcure generator (1), MCU (2) and FPGA (3), described PG pictcure generator (1) is connected with MCU (2) and FPGA (3) respectively, described MCU (2) is connected by EBI interface with FPGA (3), described MCU (2) is connected by SPI interface with bridging chip (4), described FPGA (3) is connected with MIPI module (5) by bridging chip (4)

Described PG pictcure generator (1) is for arranging register configuration parameter and the view data of VIDEO pattern or COMMAND pattern according to the type of MIPI module (5), and the register configuration parameter of VIDEO pattern or COMMAND pattern is sent to MCU (2), the view data of VIDEO pattern or COMMAND pattern is sent to FPGA (3);

The register configuration parameter of COMMAND pattern, for the register configuration parameter of VIDEO pattern being converted into DCS instruction and being sent to bridging chip (4) by SPI interface, is converted into DCS instruction and is sent to FPGA (3) by EBI interface by described MCU (2);

Described FPGA (3), for view data being sent to bridging chip (4) by rgb interface in VIDEO pattern, is sent to bridging chip (4) after DCS instruction and view data are packed by COMMAND pattern.

2. the MIPI module group test system realizing two kinds of patterns according to claim 1, it is characterized in that: described FPGA (3) comprises VIDEO mode data processing module (3-1), image interface circuit (3-2), EBI module (3-3), COMMAND mode data processing module (3-4) and sequential interface circuit (3-5), described VIDEO mode data processing module (3-1) is sent to image interface circuit (3-2) after PG pictcure generator (1) receives the image real time transfer of VIDEO pattern, the view data of VIDEO pattern is sent to bridging chip (4) by described image interface circuit (3-2), the DCS instruction of the COMMAND pattern received from MCU (2) is sent to sequential interface circuit (3-5) by described EBI module (3-3), described COMMAND mode data processing module (3-4) is sent to sequential interface circuit (3-5) after PG pictcure generator (1) receives the image real time transfer of COMMAND pattern, described sequential interface circuit (3-5) is sent to bridging chip (4) after the DCS instruction of COMMAND pattern and view data being packed.

3. the MIPI module group test system realizing two kinds of patterns according to claim 1 and 2, it is characterized in that: described FPGA (3) arranges the IFSEL pin of bridging chip (4) by GPIO interface, when level is low, bridging chip (4) works in VIDEO pattern, and when level is high, bridging chip (4) works in COMMAND pattern.