DE10110627A1 - Controlling test functions for activating rambus dynamic random accecss memory (RDRAM) component - Google Patents

Abstract

A memory controller (20) reads-in data sequences, via an interface (2), into a configuration register (4) of the RDRAM component (1). A data frequenncy, determining the RDRAM test function, is read-in into a free memory section (6) of the configuration register.The input data frequency, or its parts, are transmitted into a test option register (7) via a llink (6b). The test option register controls the selected test functions of the RDRAM in accordance with data frequency. Independent claims are included for the control executing circuit.

Description

The invention relates to a method and a switching arrangement for controlling test functions in a memory chip, especially for activating test functions in one 7. RDRAM module according to the preamble of claims 1 and 7 respectively.

Memory chips are usually created using an ent speaking test system of a function and performance test subjected. From the results of these functional and Performance testing can then be done using an error analysis Problems and design weaknesses with the memory chip closed will be. During the test process, the memory chip is removed from Test system placed in a predetermined operating mode to then a desired test pattern, furthermore also test mode designated to activate.

To run a manufacturer-specific test mode can become more common with conventional memory chips from an external memory controller via a serial les interface of the block a corresponding data sequence created. This way of activating a manufacturer spec Fishing test mode in the memory chip is called direct access mode called. The manufacturer-specific test mode can the memory chip z. B. Specify parameters such as Internal voltage should be varied to match the radio tion of the memory module.

In addition to the shown direct access mode for activation of manufacturer-specific test modes in the memory chip the test mode can also be sent directly via the data bus, if the memory chip does not have a serial interface. This applies, for example, to the SDRAM module. This However, activating the manufacturer-specific test mode has  the disadvantage that in order to run the test mode during the runtime of the To be able to execute SDRAM components in the PC system, in the SDRAM A further memory area are available must have a corresponding application program stores that is used to activate customer-specific Test functions are required. This storage area can z. B. be an SRAM expansion card.

With an RDRAM memory chip, there is a serial In interface available. Customized test functions can however, again not activated when the memory module is operated in a PC system. The store controller of the PC system controls the whole Initialization via the serial communication interface. The memory controller has via the serial interface only access to the internal configuration register of the RDRAM memory chips with which the chip in the correct Operating mode is set and function settings before be taken. He has no access to a test option register with which the test functions in the RDRAM block can be controlled. Since there is no direct access mode in RDRAM module is possible, the memory controller can data set required for a customer-specific test mode not via the serial interface from the RDRAM module transfer.

The method according to the invention and the circuit arrangement for controlling test functions with the characteristic notes Painting claims 1 and 7, on the other hand, have the advantage that even with memory modules such as an RDRAM, the acti vation of test modes is possible, although not a direct one There is access to the test options register. As special before It is considered partial that access to the test Options register for activating the test modes even during the Runtime of the memory chip in a computer system (PC System). This can, for example, internal chip can be adjusted to full performance, error control  or the functionality of the memory chip to reach.

Through the measures listed in the dependent claims are advantageous further developments and improvements of the in the independent claims 1 and 7 mentioned method or given the circuit arrangement. As a special advantage It is considered that the test options register has a controls several voltage generators. By one step wise change of voltages via the test modes can now also by the user of the memory block during operation be checked. Malfunctions can thus be advantageous Check directly and without removing the memory module.

In particular via a fine adjustment of the voltage generator ren can be a functional in a simple and inexpensive check of the memory module. Erforder Only the program with the customer-specific is required Test mode.

Another advantage is seen in the fact that Test option register defined signal paths on or off can be switched. This allows you to easily repairs can also be carried out. For example, lets such a defective voltage generator switch off and the circuit part not supplied by another voltage Advantageously supply generator.

By linking the configuration according to the invention registers with the test option register can almost be set any test functions so that manufacturing conditional errors or errors that occurred during operation Memory module can be recognized more easily.

The test functions can thus both be advantageous Monitoring as well as fault diagnosis of the memory module use.  

In the circuit arrangement, the above are before share with un by simply linking a register used bits of the configuration register with the test option register achieved. There is only one ent speaking line connection between the two registers and logic needs to be combined. About these Line connection can then be the corresponding data sequence a test function in the test options register the.

With an RDRAM module in particular, one achieves with the above circuit arrangement during operation one Access to the test option register that was not previously used Was available.

The invention is based on the object with a Spei block, especially in the case of an RDRAM block Access to a test option register to create on hand of test functions to control and close the memory module check. This task comes with the characteristics of the next ordered claims 1 and 7 solved.

An embodiment of the invention is in the drawing shown and the following description in more detail tert.

Fig. 1 shows a block diagram of a schematic measuring arrangement and

Fig. 2 in part shows the schematic structure of a RDRAM device.

The block diagram with the schematic measuring arrangement according to FIG. 1 shows a test system 31 known per se, in which a program with test functions for testing memory modules 1 is preferably stored. The test system 31 has all the necessary units that are required for controlling, reading, displaying and evaluating data. It is connected to a memory controller 20 which is connected to the memory module 1 to be tested via a serial interface 21 and a serial bus 22 . A plurality of memory modules 1 , which are controlled serially by the memory controller 20, can also be connected to the serial bus 22 . In Fig. 1 z. B. 3 memory modules 1 is closed.

The invention is particularly suitable for building blocks such as RDRAM (Rambus Dynamic Random Access Memory), as this no direct access, for example via the direct access mode to the test options register of the Offer memory chip.

Fig. 2 shows an embodiment of the invention, in which the circuit parts essential to the invention were shown schematically Darge. For reasons of clarity, the memory controller 20 with its serial interface 21 was shown again in the upper part of FIG. 2. The serial interface 21 is connected via a serial bus 22 to an on-chip serial interface 2 of the memory module 1 to be tested. The serial bus 22 has data lines 23 and clock lines 24 , via which the serial data sequences are sent to the memory module 1 . For example, the data sequence receives address and control commands with which an on-chip configuration register 4 can be addressed.

For a better understanding of FIG. 2, it should be pointed out that the modules and lines below the horizontal dashed line are located within the memory module 1 and are not accessible from the outside. Direct measurements are therefore not possible.

The serial interface 2 is first connected to a comparison circuit 3 , which filters the incoming data sequence. The comparison circuit 3 , on the one hand, allows direct access to a test option register 7 via a serial read-parallel shift register 5 in a direct access mode 13 . However, this direct access is only possible by the manufacturer with an appropriate test system (memory tester). After the memory module 1 has been installed in a computer system, the activation of customer-specific test modes via the direct access mode 13 is no longer possible, since the command sequence on the serial bus 22 cannot be freely configured through the connection to the modules of the computer system which are also connected. This means that the memory controller 20 can only create the transmission protocol for the configuration register 4 , but not for the test option register 7 .

The comparison circuit 3 , on the other hand, is connected to the configuration register 4 for the reasons mentioned above. In the corresponding register, for example with the addresses 0x021. , , 0x077. , , 0x0FF of the configuration register 4 , the data sequence of the memory controller 20 is written in and is then available for control purposes.

In order to be able to use these registers for test modes, a register 6 , which contains unused bits 6 a, is connected via a link 6 b to the test option register 7 according to the invention. For example, register 6 with address 0x077 was selected, in which the test modes for test options register 7 are written.

In an alternative embodiment of the invention, provision is made to set up a new unoccupied register with free bits, which is then connected to the test option register 7 . Link 6 b of register 6 with test options register 7 gives direct access to test options register 7 . As a result, test functions or chip-internal settings can now be controlled with a simple write access. In this way, for example

• 1. chip-internal voltage generators 8 , 9 controlled,
• 2. Defined signal paths switched on and off or
• 3. Operating modes and settings

to be changed.

As can also be seen in FIG. 2, the test options register 7 is connected to both a voltage generator 8 and a second voltage generator 9 . That is, depending on the programming of the data sequence, the two voltage generators 8 , 9 are set to the desired voltage values. The voltages are preferably programmed in stages, so that the two voltage generators 8 , 9 can be adjusted for fine adjustment. This can be necessary in order to detect errors in the memory module 1 and, if necessary, to 'repair' them by switching on and off defined signal paths.

The voltage generators 8 , 9 are connected according to FIG. 2 from the output side to circuits 10 , 11 and 12 , each circuit 10 , 11 , 12 being supplied by both the voltage generator 8 and the voltage generator 9 . For example, the voltage generator 8 supplies the voltage +5 volts and the voltage generator 9 the voltage -5 volts to the circuits 10 , 11 , 12 , so that all circuits 10 , 11 , 12 are supplied with the controllable voltages +/- 5 volts.

Of course, the invention is not limited by the described embodiment. It is essential to the invention that, by linking the configuration register 4 with the test option register 7, a new possibility has been created to be able to start test functions on the memory chip during normal computer operation.

LIST OF REFERENCE NUMBERS

1

memory chip

2

on-chip interface of the memory chip

3

comparison circuit

4

configuration register

5

shift register

6

register

6

a unused bits

6

b Link

7

Test option register

8th

first voltage generator

9

second voltage generator

10

circuit

11

circuit

12

circuit

13

Direct access mode

20

memory controller

21

Serial interface of the memory controller

22

Serial bus

23

data lines

24

clock lines

30

test generator

31

test system

Claims (10)

1. A method for controlling test functions in a memory module ( 1 ), in particular for activating test functions in an RDRAM module, with data sequences via an interface ( 2 ) in a configuration register ( 4 ) of the memory module by means of a memory controller ( 20 ) ( 1 ) be marked , characterized in that
a data frequency that defines test functions for the memory module is read into a free memory area ( 6 ) of the configuration register ( 4 ),
that the read data frequency or parts thereof are transmitted via a link ( 6 b) to a test option register ( 7 ), and
that the test option register ( 7 ) controls selected test functions of the memory module ( 1 ) according to the data frequency. 2. The method according to claim 1, characterized in that the test option register ( 7 ) controls at least one voltage generator ( 8 , 9 ). 3. The method according to claim 2, characterized in that the test option register ( 7 ) performs a fine adjustment of the generator voltage. 4. The method according to any one of the preceding claims, characterized in that the test option register ( 7 ) switches defined signal paths on or off. 5. The method according to any one of the preceding claims, characterized in that the test option register ( 7 ) controls predetermined test modes. 6. The method according to claim 5, characterized in that the test modes used for monitoring and fault diagnosis become. 7. Switching arrangement for performing the method according to one of the preceding claims in a memory chip ( 1 ) with an interface ( 2 ), a configuration register ( 4 ) and a test option register ( 7 ), characterized in that at least one register ( 6 ) in the configuration register ( 4 ) is logically connected to the test option register ( 7 ) via a link ( 6 b). 8. Circuit arrangement according to claim 7, characterized in that the register ( 6 ) has unused bits ( 6 a) in normal operation. 9. Circuit arrangement according to one of claims 7 or 8, characterized in that the interface ( 2 ) has a serial interface. 10. Circuit arrangement according to one of claims 7 to 9, characterized in that the memory chip ( 1 ) is an RDRAM chip.