CN111710662A - Universal multi-die silicon stacking interconnection structure - Google Patents

Universal multi-die silicon stacking interconnection structure Download PDF

Info

Publication number
CN111710662A
CN111710662A CN202010620259.1A CN202010620259A CN111710662A CN 111710662 A CN111710662 A CN 111710662A CN 202010620259 A CN202010620259 A CN 202010620259A CN 111710662 A CN111710662 A CN 111710662A
Authority
CN
China
Prior art keywords
silicon
die
chip
dies
connection point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010620259.1A
Other languages
Chinese (zh)
Other versions
CN111710662B (en
Inventor
范继聪
徐彦峰
单悦尔
闫华
陈波寅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Zhongwei Yixin Co Ltd
Original Assignee
Wuxi Zhongwei Yixin Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Zhongwei Yixin Co Ltd filed Critical Wuxi Zhongwei Yixin Co Ltd
Priority to CN202010620259.1A priority Critical patent/CN111710662B/en
Publication of CN111710662A publication Critical patent/CN111710662A/en
Application granted granted Critical
Publication of CN111710662B publication Critical patent/CN111710662B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a universal multi-die silicon stacking interconnection structure, which relates to the technical field of semiconductors and comprises a substrate, a silicon connection layer on the substrate and a plurality of dies stacked on the silicon connection layer in a two-dimensional stacking mode, wherein the dies are internally provided with special silicon stacking connection points for leading out signals and connected to connection point leading-out ends through RDL (remote description) layers, the die signals are led out to the connection point leading-out ends through the silicon stacking connection points, and the connection point leading-out ends can be connected to other dies through die-crossing connection wires in two directions in the silicon connection layer; the interconnection mode between the bare chips in the structure is more flexible, different system-level packaging can be quickly realized, the input and output ports of the bare chips do not need to be occupied, the connecting channels are not limited by the number of the input and output ports, and the structure has the characteristics of high connectivity, high speed, stability, low power consumption and miniaturization.

Description

Universal multi-die silicon stacking interconnection structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a universal multi-die silicon stacked interconnection structure.
Background
With the continuous improvement of the level of the integrated circuit manufacturing process and the continuous increase of the chip scale, more and more functional modules are integrated into one chip to form a system on chip (soc), so that the reliability of the whole system can be improved. However, as the integrated circuit process reaches below 10nm node, the tape-out cost increases sharply, and SOC is not easy to integrate some MEMS or optical devices, so that a systematic packaging sip (system in a package) technology appears, and from the packaging standpoint, a side-by-side or stacked packaging manner is performed on different chips, and a plurality of active electronic components with different functions and optional passive devices are preferentially assembled together to realize a single standard package with a certain function. SIP is from the angle of encapsulation, with many types of bare chip encapsulation together, the chip realizes the connection through input/output port, and the connecting channel is restricted by input/output port quantity, and occupies a large amount of input/output interface, has the shortcoming that the consumption is big, the speed is low.
Some patents have proposed a method for designing chip interconnects by using silicon-on-chip (SSI), for example, the patent with application number 2016800598883 proposes a stacked die interconnect without interposer, which uses a plurality of discrete interconnect dies to implement signal interconnects between two adjacent dies; another example is patent application No. 2017800501825, which proposes a separate interface for silicon stacked interconnect technology integration that uses an entire interposer as an interconnect carrier to achieve signal interconnection of two adjacent IC dies. However, the above two patents are limited by the defects of the chip itself and the structure design, and both can only interconnect two adjacent IC dies arranged side by side, and can only implement signal interconnection in a single direction, so that the structure is very limited in practical application, and the complex circuit requirements of the large-scale integrated circuit are difficult to meet.
Disclosure of Invention
The present invention provides a general multi-die silicon stacked interconnect structure for solving the above problems and technical requirements, and the technical solution of the present invention is as follows:
a universal multi-die silicon stacking interconnection structure comprises a substrate, a silicon connection layer stacked on the substrate and a plurality of dies stacked on the silicon connection layer, wherein the dies are arranged on the silicon connection layer in a two-dimensional stacking mode, and the silicon connection layer covers all the dies;
each bare chip comprises a circuit module, a silicon stacking connection point, a connection point leading-out end and an input/output port, the circuit module is connected to the silicon stacking connection point and the input/output port, and the silicon stacking connection point in the bare chip is connected with the corresponding connection point leading-out end through a connection line in a rewiring layer;
the connection point leading-out terminal in each bare chip is connected with the corresponding connection point leading-out terminal in other bare chips through a cross bare chip connecting wire in the silicon connecting layer, and each bare chip can be connected with any other bare chip through the cross bare chip connecting wire in the silicon connecting layer; the cross-die connecting lines which are communicated with the dies are arranged crosswise along a first direction and a second direction in the silicon connecting layer, and the first direction and the second direction are vertical to each other in the horizontal direction; the input/output port in the bare chip is connected to the substrate through the silicon through hole on the silicon connecting layer.
The further technical scheme is that the connection point leading-out terminals in each bare chip are arranged in a row-column structure along the first direction and the second direction.
The further technical scheme is that a plurality of rows of connection point leading-out terminals are distributed in each bare chip along the first direction, and/or a plurality of columns of connection point leading-out terminals are distributed along the second direction.
Its further technical scheme does, has laid a plurality of rows of tie point terminals in every bare chip along first direction, includes:
a plurality of rows of connection point leading-out ends are uniformly distributed in each bare chip along the first direction at the same intervals; or, a plurality of rows of connection point terminals are randomly arranged in each bare chip along the first direction.
The further technical scheme is that the cross-bare chip connecting wires which are communicated with all the bare chips are arranged in a silicon connecting layer in a layered mode.
The further technical scheme is that for any two bare chips connected by cross-bare chip connection lines:
the two dies are located in the same row in the first direction but in different columns in the second direction, and the two dies are adjacent or separated by at least one die;
alternatively, the two dies are located in the same column in the second direction but in different rows in the first direction, and the two dies are adjacent or separated by at least one die;
alternatively, the two dies are located in different rows in the first direction and in different columns in the second direction.
The further technical scheme is that a plurality of bare chips are arranged on the silicon connecting layer according to the shape and the area of each bare chip; and/or a plurality of bare chips are arranged on the silicon connection layer according to the chip functions of the bare chips.
The further technical scheme is that a convex ball grows on each bare chip, a connection point leading-out end on each bare chip is connected to the convex ball, the convex ball on each bare chip is connected to one side surface of a silicon connection layer, the convex ball grows on the other side surface of the silicon connection layer, the convex ball on the silicon connection layer is connected to a substrate, and a silicon through hole communicated with the bare chips and the substrate is formed in the silicon connection layer.
The further technical scheme is that at least one bare chip is a Processor chip, and the Processor chip comprises at least one of a Processor chip such as an ARM chip or a RISC-V chip;
and/or at least one bare chip is a DSP chip;
and/or, at least one die is an AI chip;
and/or, at least one bare chip is a memory chip, and the memory chip comprises at least one of SRAM, DRAM, ROM, FLASH, MRAM and RRAM;
and/or at least one bare chip is a data conversion chip, and the data conversion chip comprises at least one of an analog-to-digital conversion chip and a digital-to-analog conversion chip;
and/or, at least one die is a radio frequency chip;
and/or, at least one die comprises an HBM, RAMBUS or NOC interface;
and/or, at least one die includes a PCIE, Ethernet MAC, XUAI, SONET/SDH, or INTERLAKEN interface.
The beneficial technical effects of the invention are as follows:
1. the universal multi-die silicon stacked interconnection structure comprises a substrate, a silicon connection layer and a plurality of dies, wherein the silicon connection layer covers all the dies, multilayer cross-die connecting lines in two directions are distributed in the whole or partial region of the silicon connection layer according to circuit requirements, and therefore each die can be connected with any other die through the cross-die connecting lines of the silicon connection layer, two-dimensional interconnection communication of the plurality of dies is achieved through the cross-die connecting lines arranged in the silicon connection layer along the two directions, the interconnection mode between the dies is more flexible, and different system-level packaging can be achieved quickly.
2. When the bare chips are interconnected through the silicon connecting layer, signal leading-out and interconnection are achieved through the special silicon stacking connecting points in the bare chips, the input and output ports of the bare chips do not need to be occupied, connecting channels are not limited by the number of the input and output ports, and the circuit has the advantages of being high in connectivity, high in speed, stable, low in power consumption and small in size.
Drawings
Fig. 1 is a cross-sectional schematic view of a generalized multi-die silicon stacked interconnect structure of the present application.
Fig. 2 is an enlarged view of a portion of the structure in fig. 1.
Fig. 3 is a top down two-dimensional schematic view of a generalized multi-die silicon stacked interconnect structure of the present application.
Fig. 4 is a schematic diagram of the connections between the die internal silicon stack connection points and the circuit module in the present application.
Fig. 5 is a schematic diagram of a connection point terminal on a die according to the present application.
Fig. 6 is a two-dimensional schematic diagram of an interconnect structure formed between dies through connection point leadouts in the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application provides a general multi-die silicon stacked interconnect structure, fig. 1 is a schematic cross-sectional view of the interconnect structure of the application, fig. 2 is an enlarged view of a part of the structure in fig. 1, and fig. 3 is a corresponding schematic top view of fig. 1. The general multi-die silicon stacked interconnect structure comprises a substrate 1, a silicon connection layer 2 and a plurality of dies which are sequentially stacked from bottom to top, for example, the structure shown in fig. 1 to 3 comprises 6 dies, which are respectively represented by dies 1 to 6. In practical implementation, the general multi-die silicon stacked interconnect structure further includes a package housing for protecting each component, which is packaged outside the substrate 1, the silicon connection layer 2 and the die, and further includes pins for signal extraction and the like connected to the substrate, which conventional structures are not shown in detail in fig. 1 and 2.
The interconnect structure of the present application includes a plurality of bare chips, the bare chips are all stacked on the same silicon connection layer 2, and the bare chips are arranged on the silicon connection layer 2 in a two-dimensional stacking manner, that is, arranged along two directions, i.e., horizontal and vertical directions, in a horizontal plane, as shown in fig. 3. The multiple bare chips can be reasonably arranged on the silicon connection layer 2 according to actual needs, and can be compactly arranged on the silicon connection layer 2 according to the shape and the area of each bare chip, so that the whole area of the whole interconnection structure is smaller; the silicon connection layer can be arranged according to the chip functions of the dies, so that the interconnection performance among the whole dies is better.
The silicon connection layer 2 is internally provided with the cross-die connecting wires 3, the cross-die connecting wires 3 are distributed in the whole area or partial area of the silicon connection layer 2, and the silicon connection layer 2 covers all the dies, so that each die can be connected to any other die through the cross-die connecting wires 3 according to the circuit requirements, the circuit interconnection between the dies is almost unlimited in space, and the flexibility is far better than the structures of the two patents mentioned in the background art. The inter-die connection lines 3 arranged inside the silicon connection layer 2 are arranged crosswise along a first direction and a second direction, and the first direction and the second direction are mutually vertical in the horizontal direction, namely, the first direction and the second direction are two directions of the horizontal direction and the vertical direction matched with the die arrangement structure. Therefore, each die can be connected with other dies in the first direction and the second direction simultaneously through the cross-die connecting lines 3 in the two directions, so that a two-dimensional interconnection structure is formed among a plurality of dies, and particularly, the following conditions exist for any two dies connected through the cross-die connecting lines:
1. the two dies are located in the same row in the first direction but in different columns in the second direction, and the two dies are adjacent, such as between die 1 and die 2, between die 2 and die 3, between die 4 and die 5, etc. in fig. 3, which are interconnected by the cross-die connection 3 in the first direction.
2. The two dies are located in the same row in the first direction but in different columns in the second direction, and the two dies are separated by at least one die, such as between the die 1 and the die 3 in fig. 3, which is the structure, and the two dies separated by the die 2 are interconnected by the cross-die connecting line 3 in the first direction. Similarly, the die 4 and the die 6 belong to the structure.
3. The two dies are located in the same column in the second direction but in different rows in the first direction, and the two dies are adjacent, such as between the die 1 and the die 4, between the die 2 and the die 5, and so on in fig. 3, which are interconnected by the cross-die connecting line 3 in the second direction.
4. The two dies are located in the same column in the second direction but in different rows in the first direction and are separated by at least one die, which is similar to the case 2 above, and the schematic diagram is not given in detail in this application.
5. The two dies are located in different rows in the first direction and in different columns in the second direction, and the two dies are connected by the cross-die connection 3 in both directions at the same time, for example, between the die 1 and the die 6 in fig. 3.
It should be noted that fig. 3 shows the inter-die connection lines between the spaced dies as crossing the surface of the middle die, such as the inter-die connection lines between the die 1 and the die 3 crossing the surface of the die 2, but this is only for convenience of illustration of the connection relationship, and practically all the inter-die connection lines 3 are inside the silicon connection layer 2, as shown in fig. 1 and 2. The cross-die connecting lines 3 are arranged in the silicon connecting layer 2 in a layered and crossed mode, and the cross-die connecting lines 3 in the same direction and the cross-die connecting lines 3 in different directions can be arranged in a layered and crossed mode, so that the cross-die connecting lines 3 are not influenced with each other. It should be noted that although the present application claims such a two-dimensional stacking scheme, the technical solution is also applicable to a one-dimensional stacking scheme, but only there is a die-crossing wire 3 in one direction (lateral or longitudinal) inside the silicon connection layer 2. The manufacturing process of the silicon connection layer 2 can be different from that of a bare chip, and only the cross-die connection line 3 consisting of a plurality of layers of metal lines is arranged inside the silicon connection layer 2 without active devices, so that the manufacturing is easy and the cost is low.
Compared with the conventional bare chip, the bare chip in the present application is different, the conventional bare chip mainly includes a circuit module and an input/output port connected to the circuit module, and on the basis of the bare chip in the present application, a silicon stack connection point 4 dedicated to signal extraction is also built in the bare chip, the silicon stack connection point 4 is also connected to the circuit module for extracting a circuit signal of the circuit module, the silicon stack connection point 4 can be arranged at any position inside the bare chip according to circuit requirements, fig. 4 takes the case that the silicon stack connection points 4 are arranged in a column, and actually there is no such limitation.
In addition, the die in the present application further includes connection point terminals 5 corresponding to the silicon stack connection points 4, the connection point terminals 5 are generally arranged in a row-column structure along the first direction and the second direction according to the requirement of the stack interconnection, and the structural diagram can be referred to as fig. 5. The silicon stack connection points 4 in the die are connected to corresponding connection point terminals 5 by connection lines in the redistribution layer (RDL layer), as shown in fig. 2. With this structure, the die signal of the die has been connected by the silicon stack connection point 4 to the connection point lead-out 5. The connection point terminals 5 can be connected to corresponding connection point terminals of other dies through the cross-die connection wires 3 in the silicon connection layer 2, so as to realize interconnection between dies. Specifically, a micro-bump ball grows on the bare chip, the connection point leading-out terminal 5 is connected with the silicon connection layer 2 through the micro-bump ball and is connected to other bare chips through the cross-bare chip connection wire 3 inside the silicon connection layer 2, the micro-bump ball structure at the bottom of the bare chip can be seen in fig. 2, and the micro-bump ball structure is not marked in detail in the application. Since the die is provided with the connection point terminals 5 along the first direction and the second direction, the die can be connected with other dies in two dimensions by using the connection point terminals 5 in the two directions and the cross-die connection line 3 in the two directions, please refer to the schematic diagram shown in fig. 6.
In addition, in order to achieve a higher communication bandwidth, multiple rows/multiple columns of connection point leading-out terminals 5 may be arranged, that is, multiple rows of connection point leading-out terminals 5 are arranged in each bare chip along the first direction, and/or multiple columns of connection point leading-out terminals 5 are arranged along the second direction, so that efficient two-dimensional cascading of multiple rows and multiple columns is achieved. When the plurality of rows/columns of the connection point leading-out terminals 5 are arranged along each direction, they may be arranged at regular intervals or at random.
It should be noted that the present application employs a die with a built-in dedicated silicon stack connection point as described above, and signal extraction and die interconnection are performed through separate silicon stack connection points. However, the structure is also compatible with a conventional bare chip, and at this time, the input/output ports in the bare chip directly perform signal extraction and bare chip interconnection through the silicon connection layer 2, but compared with the structure directly adopting input/output port interconnection, the structure adopting silicon stacking connection point interconnection has the advantages of higher bandwidth, lower delay, lower power consumption and the like.
Referring to fig. 1 and 2, a silicon connection layer 2 is stacked on a substrate 1, specifically, a micro-bump is grown on a side of the silicon connection layer 2 away from a die, and the silicon connection layer 2 is connected to the substrate 1 through the micro-bump. The silicon connecting layer 2 is further provided with a silicon through hole 6, and the input/output port in the bare chip is connected to the substrate 1 through the silicon through hole 6 on the silicon connecting layer 2 so as to finally lead out signals.
The dies included in the generalized multi-die silicon stacked interconnect structure may be one or more different types of dies, wherein:
at least one die is a Processor chip including at least one of a Processor chip such as an ARM chip or a RISC-V chip;
and/or at least one bare chip is a DSP chip;
and/or, at least one die is an AI chip;
and/or, at least one bare chip is a memory chip, and the memory chip comprises at least one of SRAM, DRAM, ROM, FLASH, MRAM and RRAM;
and/or at least one bare chip is a data conversion chip, and the data conversion chip comprises at least one of an analog-to-digital conversion chip and a digital-to-analog conversion chip;
and/or, at least one die is a radio frequency chip;
and/or, at least one die comprises an HBM, RAMBUS or NOC interface;
and/or at least one die includes a PCIE, Ethernet MAC, XUAI, SONET/SDH, or INTERLAKEN interface.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (9)

1. A universal multi-die silicon stacked interconnection structure is characterized by comprising a substrate, a silicon connection layer stacked on the substrate and a plurality of dies stacked on the silicon connection layer, wherein the dies are arranged on the silicon connection layer in a two-dimensional stacking mode, and the silicon connection layer covers all the dies;
each bare chip comprises a circuit module, a silicon stacking connection point, a connection point leading-out end and an input/output port, the circuit module is connected to the silicon stacking connection point and the input/output port, and the silicon stacking connection point in the bare chip is connected with the corresponding connection point leading-out end through a connection line in a rewiring layer;
the connection point leading-out terminal in each bare chip is connected with the corresponding connection point leading-out terminal in other bare chips through a cross bare chip connecting wire in the silicon connecting layer, and each bare chip can be connected with any other bare chip through the cross bare chip connecting wire in the silicon connecting layer; the cross-die wires connecting the dies are arranged crosswise along a first direction and a second direction in the silicon connecting layer, and the first direction and the second direction are mutually vertical in the horizontal direction; and the input/output port in the bare chip is connected to the substrate through the silicon through hole on the silicon connecting layer.
2. The universal multi-die silicon stack interconnect structure of claim 1 wherein the connection point terminals in each die are arranged in a row and column configuration along the first and second directions.
3. The universal multi-die silicon stack interconnect structure of claim 2 wherein each die has rows of connection point terminations routed along the first direction and/or columns of connection point terminations routed along the second direction.
4. The universal multi-die silicon stack interconnect structure of claim 3 wherein each die has rows of connection point terminations routed along the first direction, comprising:
a plurality of rows of connection point leading-out ends are uniformly distributed in each bare chip along the first direction at the same intervals; or, a plurality of rows of connection point terminals are randomly distributed in each bare chip along the first direction.
5. The universal multi-die silicon stack interconnect structure of claim 1,
cross-die wires connecting the dies are arranged in layers within the silicon connection layer.
6. The universal multi-die silicon stack interconnect structure of claim 1 wherein for any two dies connected by a cross-die wire:
the two dies are in the same row in the first direction but in different columns in the second direction, and the two dies are adjacent or separated by at least one die;
alternatively, the two dies are in the same column in the second direction but in different rows in the first direction, and the two dies are adjacent or separated by at least one die space;
alternatively, the two dies are located in different rows in the first direction and in different columns in the second direction.
7. The generic multi-die silicon stack interconnect structure of any of claims 1-6,
a plurality of bare chips are arranged on the silicon connection layer according to the shape and the area of each bare chip;
and/or a plurality of bare chips are arranged on the silicon connection layer according to the chip functions of the bare chips.
8. The generic multi-die silicon stack interconnect structure of any of claims 1-6,
each bare chip is grown with a convex ball, a connection point leading-out end on the bare chip is connected to the convex ball, the convex ball on each bare chip is connected to one side surface of the silicon connection layer, the convex ball is grown on the other side surface of the silicon connection layer, the convex ball on the silicon connection layer is connected to the substrate, and a silicon through hole which is communicated with the bare chip and the substrate is formed in the silicon connection layer.
9. The generic multi-die silicon stack interconnect structure of any of claims 1-6,
at least one die is a Processor chip including at least one of a Processor chip such as an ARM chip or a RISC-V chip;
and/or at least one bare chip is a DSP chip;
and/or, at least one die is an AI chip;
and/or, at least one die is a memory chip comprising at least one of SRAM, DRAM, ROM, FLASH, MRAM, and RRAM;
and/or at least one bare chip is a data conversion chip, and the data conversion chip comprises at least one of an analog-to-digital conversion chip and a digital-to-analog conversion chip;
and/or, at least one die is a radio frequency chip;
and/or, at least one die comprises an HBM, RAMBUS or NOC interface;
and/or, at least one die includes a PCIE, Ethernet MAC, XUAI, SONET/SDH, or INTERLAKEN interface.
CN202010620259.1A 2020-07-01 2020-07-01 Universal multi-die silicon stacking interconnection structure Active CN111710662B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010620259.1A CN111710662B (en) 2020-07-01 2020-07-01 Universal multi-die silicon stacking interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010620259.1A CN111710662B (en) 2020-07-01 2020-07-01 Universal multi-die silicon stacking interconnection structure

Publications (2)

Publication Number Publication Date
CN111710662A true CN111710662A (en) 2020-09-25
CN111710662B CN111710662B (en) 2022-03-22

Family

ID=72544347

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010620259.1A Active CN111710662B (en) 2020-07-01 2020-07-01 Universal multi-die silicon stacking interconnection structure

Country Status (1)

Country Link
CN (1) CN111710662B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113301717A (en) * 2021-05-21 2021-08-24 维沃移动通信有限公司 Circuit board structure and electronic equipment
CN114996201A (en) * 2022-07-28 2022-09-02 沐曦科技(成都)有限公司 Routing system based on Die interconnection
CN116303191A (en) * 2023-05-15 2023-06-23 芯耀辉科技有限公司 Method, equipment and medium for interconnecting wafer-to-wafer interfaces
WO2024093965A1 (en) * 2022-10-31 2024-05-10 上海嘉楠捷思信息技术有限公司 Chip and manufacturing and encapsulation method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104350595A (en) * 2012-07-17 2015-02-11 华为技术有限公司 Large sized silicon interposers overcoming the reticle area limitations
CN106206557A (en) * 2015-05-25 2016-12-07 华亚科技股份有限公司 Silicon intermediary layer
CN109564914A (en) * 2016-08-15 2019-04-02 赛灵思公司 For stacking the stand-alone interface of silicon interconnection (SSI) Integration ofTechnology
CN110010510A (en) * 2017-12-19 2019-07-12 恩智浦有限公司 Multi-core array apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104350595A (en) * 2012-07-17 2015-02-11 华为技术有限公司 Large sized silicon interposers overcoming the reticle area limitations
CN106206557A (en) * 2015-05-25 2016-12-07 华亚科技股份有限公司 Silicon intermediary layer
CN109564914A (en) * 2016-08-15 2019-04-02 赛灵思公司 For stacking the stand-alone interface of silicon interconnection (SSI) Integration ofTechnology
CN110010510A (en) * 2017-12-19 2019-07-12 恩智浦有限公司 Multi-core array apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113301717A (en) * 2021-05-21 2021-08-24 维沃移动通信有限公司 Circuit board structure and electronic equipment
WO2022242670A1 (en) * 2021-05-21 2022-11-24 维沃移动通信有限公司 Circuit board structure and electronic apparatus
CN114996201A (en) * 2022-07-28 2022-09-02 沐曦科技(成都)有限公司 Routing system based on Die interconnection
CN114996201B (en) * 2022-07-28 2022-09-30 沐曦科技(成都)有限公司 Routing system based on Die interconnection
WO2024093965A1 (en) * 2022-10-31 2024-05-10 上海嘉楠捷思信息技术有限公司 Chip and manufacturing and encapsulation method therefor
CN116303191A (en) * 2023-05-15 2023-06-23 芯耀辉科技有限公司 Method, equipment and medium for interconnecting wafer-to-wafer interfaces
CN116303191B (en) * 2023-05-15 2023-09-15 芯耀辉科技有限公司 Method, equipment and medium for interconnecting wafer-to-wafer interfaces

Also Published As

Publication number Publication date
CN111710662B (en) 2022-03-22

Similar Documents

Publication Publication Date Title
CN111710662B (en) Universal multi-die silicon stacking interconnection structure
US7888806B2 (en) Electrical connections for multichip modules
CN111710663B (en) Multi-die silicon stacking interconnection structure FPGA
CN111755437B (en) FPGA device for forming network on chip by utilizing silicon connecting layer
US11302674B2 (en) Modular stacked silicon package assembly
US8933561B2 (en) Semiconductor device for semiconductor package having through silicon vias of different heights
KR20160090706A (en) Semiconductor package with narrow width interposer
US11158621B2 (en) Double side mounted large MCM package with memory channel length reduction
CN113410223B (en) Chip set and method for manufacturing the same
CN114902404A (en) Multi-chip stacked device
US20120049361A1 (en) Semiconductor integrated circuit
CN114823623A (en) Semiconductor package
KR102671078B1 (en) Stack package including fan out sub package
CN111753481B (en) Multi-die FPGA utilizing active silicon connection layer to balance delay
CN111753478B (en) Multi-die FPGA (field programmable gate array) for realizing built-in analog circuit by utilizing active silicon connection layer
CN111710661B (en) Multi-die FPGA designed based on signal delay balancing technology
CN111753479B (en) Multi-die FPGA for integrating multi-die network-on-chip using silicon connection layer
CN111755435B (en) Multi-die FPGA for integrating HBM memory dies by utilizing silicon connection layer
CN221201168U (en) Packaging structure
KR100851108B1 (en) Wafer level system in package and fabrication method thereof
CN218039195U (en) Semiconductor packaging structure
US20220208712A1 (en) Multi-level bridge interconnects
US20240014140A1 (en) Fan-out Wafer Level Package having Small Interposers
US20240120276A1 (en) Three-dimensional semiconductor integrated circuit device including inter-die interface
CN118215391A (en) Package structure and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant