CN114996201B - Routing system based on Die interconnection - Google Patents

Routing system based on Die interconnection Download PDF

Info

Publication number
CN114996201B
CN114996201B CN202210896835.4A CN202210896835A CN114996201B CN 114996201 B CN114996201 B CN 114996201B CN 202210896835 A CN202210896835 A CN 202210896835A CN 114996201 B CN114996201 B CN 114996201B
Authority
CN
China
Prior art keywords
die
destination
access request
routing information
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210896835.4A
Other languages
Chinese (zh)
Other versions
CN114996201A (en
Inventor
丛高建
其他发明人请求不公开姓名
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Muxi Technology Chengdu Co ltd
Original Assignee
Muxi Technology Chengdu Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Muxi Technology Chengdu Co ltd filed Critical Muxi Technology Chengdu Co ltd
Priority to CN202210896835.4A priority Critical patent/CN114996201B/en
Publication of CN114996201A publication Critical patent/CN114996201A/en
Application granted granted Critical
Publication of CN114996201B publication Critical patent/CN114996201B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306Intercommunication techniques
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/02Topology update or discovery

Abstract

The invention relates to the technical field of chips, in particular to a routing system based on Die interconnection, which comprises N dice forming an interconnection topological structure, wherein each Die comprises M interconnected IP and R external interconnection interfaces; a local map and a global map are stored on each Die internal bus; the method comprises the steps that an access request queries a global route according to a destination address to obtain an external interconnection interface of the Die, queries a local map according to the external interconnection interface to obtain an address and local routing information of the interconnection interface, sends the access request to the corresponding interconnection interface according to the local routing information, enables the access request to be input to the next Die, and updates local routing information carried by the access request according to the local map of the next Die, achieves the purpose of cross-Die routing, and solves the problem that cross-Die access cannot be achieved at present.

Description

Routing system based on Die interconnection
Technical Field
The invention relates to the technical field of chips, in particular to a routing system based on Die interconnection.
Background
SoC (System on Chip), generally referred to as a System-on-Chip, is an integrated circuit that integrates a processor and other electronic systems into a single Chip, and due to the current increasing degree of integration, designers divide the SoC into a plurality of smaller dies, and then package the dies into multi-Chip modules, where the dies are called Die.
One Die comprises a plurality of IPs, the IPs are interconnected based on a Network On Chip (NOC), the NOC has all routing information in the Die, if a certain IP inside the Die is accessed, the corresponding routing information can be obtained after the address of a target IP is obtained, but when the current Die is interconnected with the next Die and the IP in the current Die needs to access a certain IP in the next Die, the NOC cannot obtain the routing information outside the current Die, and cross-Die access cannot be carried out.
Disclosure of Invention
In order to solve the above technical problem, an object of the present invention is to provide a routing system based on Die interconnect, and an adopted technical solution is specifically as follows:
a routing system based on Die interconnection comprises N dice forming an interconnection topological structure, wherein each Die comprises M interconnected IP and R external interconnection interfaces;
the system comprises a plurality of Die internal buses, wherein each Die internal bus is stored with a local map and a global map, the local map comprises addresses of all IPs in the current Die, addresses of interconnection interfaces connected with external Dies and routing information for accessing the internal IPs or the interconnection interfaces, and the global map comprises addresses of N interconnection Dies, addresses of the IPs in each Die and routing information for accessing destination Dies;
when a source IP initiates an access request to a destination IP, the access request carries a destination IP address of the destination IP, a global map is inquired according to the destination IP address to obtain an address of a destination Die to which the destination IP address belongs and global routing information of the access destination Die, and the address of the destination Die and the global routing information are added to the head of the access request;
judging whether the current Die is the destination Die or not by the current Die according to the address of the destination Die carried by the access request, if so, inquiring a local map to obtain destination routing information of the destination IP, and sending the access request to the destination IP according to the destination routing information; otherwise, obtaining an interconnection interface connected with the next Die according to the global routing information, inquiring a local map of the current Die according to the interconnection interface to obtain an address of the interconnection interface and local routing information of the access interface, adding the local routing information to the head of the access request, sending the access request to the corresponding interconnection interface by the current Die according to the local routing information of the head of the access request, transmitting the access request to the next Die, and updating the local routing information in the access request according to the local map inside the next Die.
The invention has the following beneficial effects:
the embodiment of the invention provides a routing system based on Die interconnection, which comprises N dice forming an interconnection topological structure, wherein each Die comprises M interconnected IP and R external interconnection interfaces; a local map and a global map are stored on each Die internal bus; the method comprises the steps that an access request queries a global route according to a destination address to obtain an external interconnection interface of the Die, queries a local map according to the external interconnection interface to obtain an address and local routing information of the interconnection interface, sends the access request to the corresponding interconnection interface according to the local routing information, enables the access request to be input to the next Die, and updates local routing information carried by the access request according to the local map of the next Die, achieves the purpose of cross-Die routing, and solves the problem that cross-Die access cannot be achieved at present.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a block diagram of a Die-based interconnect topology provided by one embodiment of the present invention;
fig. 2 is a block diagram of an internal structure of Die according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description is given to a routing system based on Die interconnection, its specific implementation, structure, features and effects according to the present invention with reference to the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" refers to not necessarily the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
The following describes a specific scheme of a routing system based on Die interconnect according to the present invention in detail with reference to the accompanying drawings.
The embodiment of the invention provides a routing system based on Die interconnection, which comprises N dice forming an interconnection topological structure: { Die (1), Die (2), …, Die (i), …, Die (N) }, where Die (i) denotes the ith Die, i ranges from 1 to N, and N > 0; die (i) includes M interconnect IPs: { IP (i,1), IP (i,2), …, IP (i, M), …, IP (i, M) } and R external interconnection interfaces { P (i,1), P (i,2), …, P (i, R) }, wherein IP (i, M) denotes the mth IP in die (i), M ranges from 1 to M, and M > 0; p (i, R) denotes the R-th external interconnect interface of die (i).
The method comprises the steps that a local map and a global map are stored in registers of a Die (i) internal bus, wherein the local map comprises addresses of all IPs in a current Die, addresses of interconnection interfaces connected with external dice and routing information for accessing the internal IPs or the interconnection interfaces, and the global map comprises N interconnection Die addresses, IP addresses in each Die and routing information for accessing destination dice. Each Die in the interconnect topology is synchronized with a global map, both of which are stored in registers of the internal bus.
When IP (i, M) is used as a source IP and IP (j, k) is used as a destination IP, and when the IP (i, M) initiates an access request to the IP (j, k), a header of the access request carries a destination IP address of the IP (j, k), the IP (i, M) queries a global map according to the destination IP address carried by the header of the access request to obtain an address of a destination Die to which the destination IP address belongs and global routing information of the access destination Die, and adds the obtained global routing information to the header of the access request, wherein the IP (j, k) represents that the value range of the kth IP in the Die (j) is 1 to N, and the value range of k is 1 to M. At this time, the header of the access request carries the destination IP address of the IP (j, k), the address of the destination Die to which the destination IP belongs, and the routing information of the access destination Die.
After an access request is initiated, a Die to which an IP (i, m) belongs is a Die (i), namely a current Die, so that the Die (i) judges whether the current Die is a destination Die according to an address of the destination Die carried by a header of the access request, if so, a local map is inquired to obtain destination routing information of the IP (j, k), and the access request is sent to the IP (j, k) according to the destination routing information; otherwise, obtaining the interconnection interfaces of the current Die (i) and the next Die through the global routing information carried by the head of the access request, inquiring the local map of the current Die (i) according to the interconnection interfaces to obtain the address of the interconnection interface and the local routing information of the access interface, and adding the local routing information to the head of the access request. It should be noted that, the Die are interconnected according to a certain topology structure to form a cluster, where there is a one-to-one mapping relationship between the Die and the interconnection interface, and thus when a next Die is determined, it is equivalent to determining the output interconnection interface. In summary, when the Die is internal, the header of the access request carries the destination IP address of the IP (j, k), the address of the destination Die to which the destination IP belongs, the global routing information of the access destination Die, and the local routing information of the access interconnect interface. And the IP (i, m) sends the access request to a corresponding interconnection interface according to the local routing information of the head part of the access request, so that the access request is transmitted to the next Die, and when the internal part of the Die is accessed, the local routing information of the head part of the access request is updated according to the local map of the internal part of the Die. Since the local routing of the request header is out of date and no longer functional after the access request is output, the local routing information of the access request header is discarded when the access request is sent to the corresponding interconnect interface.
Specifically, the method for judging whether the current Die is the destination Die according to the address of the destination Die includes: comparing whether the address of the target Die is the same as the address of the current Die, if so, indicating that the current Die is the target Die and the target IP is in the current Die; if the two Die are not the same, it is indicated that the current Die is not the destination Die, and it is indicated that the current Die is an intermediate node, and the access request needs to be continuously sent to the next Die through the interconnection interface of the current Die and the next Die in the routing information.
Specifically, the specific method for querying the local map to obtain the destination routing information of the IP (j, k) includes: analyzing a data packet of the access request, storing a destination IP address of the IP (j, k) in the head of the data packet, and inquiring a local map of the current Die according to the destination IP address to obtain destination routing information of the access IP (j, k), wherein the local map is stored in an internal bus of the current Die; destination routing information is added to the header of the data packet of the access request.
It should be noted that, after the IP (i, m) queries the global map and the local map, the obtained global routing information and the local routing information are respectively added to the header of the access request, and when passing through the intermediate Die node, only the local routing information of the header of the access request needs to be updated according to the local map inside each Die, and the global routing information of the header of the access request does not need to be updated. Since the address of the destination Die is deterministic, the route is already determined and the corresponding route information is added to the header when the global map is queried for the first time, so that no further path updates are required. Although the access request carries routing information of the global Die, when the access request is forwarded through the intermediate Die, the routing information for accessing the interconnection interface connected with the next Die cannot be acquired inside the Die according to the global routing address, so that the routing information needs to be updated according to an actual local map inside the current Die, and the access request acquires the local routing information for accessing the interconnection interface to be output to the next Die.
The following describes a specific embodiment of the present invention in detail with reference to a practical example.
Specifically, taking 4 Die forming the interconnection topology as an example, please refer to fig. 1, which shows 4 Die forming the interconnection topology, wherein each Die includes 9 interconnected IPs and 3 interconnection interfaces. The Die set constituting the interconnection topology is as follows: { Die (1), Die (2), Die (3), Die (4) }, which includes 9 IP sets in the r-th Die (r): { IP (r,1), IP (r,2), …, IP (r,9) } and 3 sets of interconnect interfaces: { P (r,1), P (r,2), P (r,3) }, where r ranges from 1 to 4. Referring to fig. 2, fig. 2 shows the internal structure of die (r). Assuming that IP (1,2) is a source IP node, IP (3,2) is a destination IP node, and a global map and a local map are stored on an internal bus of Die (1) in IP (1,2), where the global map includes addresses of 4 Die, addresses of 4 × 9 IP in an interconnection topology and global routing information thereof, and the local map includes addresses of 9 IP in the current Die, addresses of 3 interconnection interfaces, and routing information for accessing the IP or the interconnection interfaces. IP (1,2) initiates an access request to IP (3,2), the header of the access request comprises the destination address of IP (3,2), IP (1,2) judges whether current Die is destination Die according to the destination address of the header of the access request, because IP (1,2) belongs to Die (1) and IP (3,2) belongs to Die (3), the current node is not a destination node, Die (1) inquires a global map according to the destination address to obtain global routing information of accessing Die (3), and adds the global routing information to the header of the access request. Assume that the next node in the global routing information is Die (2) and the interface interconnecting Die (2) is P (1, 2). The access request queries the local map according to the address of Die (2), obtains the address of the interconnection interface P (1,2) and the local routing information of access P (1,2), and adds the local routing information to the header of the access request, where the header of the access request includes the address of IP (3,2), the address of Die (3), the global routing information, and the local routing information. And sending the access request to P (1,2) according to the local routing information, repeating the process in the Die (1) when the access request accesses the Die (2) through P (1,2), and updating the local routing information of the head part of the access request according to the local map in the Die (2) until the access request is sent to IP (3, 2).
To sum up, the embodiment of the present invention provides a routing system based on Die interconnection, where the system includes N dies forming an interconnection topology, and each Die includes M interconnected IPs and R external interconnection interfaces; a local map and a global map are stored on each Die internal bus, the local map stores the addresses and routing information of a local IP and an external interconnection interface, and the global map stores the addresses of N interconnection dies, the IP address inside each Die and corresponding routing information; the access request queries the global route according to the destination address to obtain an external interconnection interface of the Die, queries a local map according to the external interconnection interface to obtain the address and the local routing information of the interconnection interface, sends the access request to the corresponding interconnection interface according to the local routing information, enables the access request to be input to the next Die, and updates the local routing information carried by the access request according to the local map of the next Die, thereby achieving the purpose of cross-Die routing.
Preferably, the routing system may further include a plurality of packages, each package including a number of Die, and the global map between the Die is invariant. For routing between Die and Die, there is no difference in routing due to the difference in electrical characteristics across the package and across the Die. On the level of the global map, the package can be regarded as a transparent shell, and addresses of all the Die, IP addresses inside each Die, and corresponding routing information can be directly acquired on the global map, and still the Die-specific routing is performed.
It should be noted that: the precedence order of the above embodiments of the present invention is only for description, and does not represent the merits of the embodiments. And specific embodiments thereof have been described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (6)

1. A routing system based on Die interconnection is characterized in that the routing system comprises N dice forming an interconnection topological structure, and each Die comprises M interconnected IP and R external interconnection interfaces;
the global map comprises addresses of N interconnected Dies, the address of an IP in each Die and routing information of an access destination Die;
when a source IP initiates an access request to a destination IP, the access request carries a destination IP address of the destination IP, a global map is inquired according to the destination IP address to obtain an address of a destination Die to which the destination IP address belongs and global routing information of the access destination Die, and the address of the destination Die and the global routing information are added to the head of the access request;
judging whether the current Die is the destination Die or not by the current Die according to the address of the destination Die carried by the access request, if so, inquiring a local map to obtain destination routing information of the destination IP, and sending the access request to the destination IP according to the destination routing information; otherwise, obtaining an interconnection interface connected with the next Die according to the global routing information, inquiring a local map of the current Die according to the interconnection interface to obtain an address of the interconnection interface and local routing information of the access interface, adding the local routing information to the head of the access request, sending the access request to the corresponding interconnection interface by the current Die according to the local routing information of the head of the access request, transmitting the access request to the next Die, and updating the local routing information in the access request according to the local map inside the next Die.
2. A Die interconnect-based routing system as recited in claim 1, wherein the step of determining whether the current Die is the destination Die comprises: comparing whether the address of the target Die is the same as the address of the current Die, and if so, taking the current Die as the target Die; otherwise, the current Die is not the destination Die.
3. A Die interconnect-based routing system as claimed in claim 1, wherein the step of querying the local map for destination routing information of the destination IP comprises: and inquiring a local map according to the destination IP address to obtain destination routing information for accessing the destination IP, and adding the destination routing information to the head of the access request.
4. A Die interconnect-based routing system as claimed in claim 1 wherein the global map and local map are stored in registers of a Die internal bus.
5. A Die interconnect-based routing system as claimed in claim 1, wherein said sending access request to corresponding interconnect interface further comprises the steps of: the local routing information of the access request header is discarded.
6. A Die interconnect-based routing system as recited in claim 1, wherein the routing system comprises a plurality of packages, each package comprising a number of dice.
CN202210896835.4A 2022-07-28 2022-07-28 Routing system based on Die interconnection Active CN114996201B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210896835.4A CN114996201B (en) 2022-07-28 2022-07-28 Routing system based on Die interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210896835.4A CN114996201B (en) 2022-07-28 2022-07-28 Routing system based on Die interconnection

Publications (2)

Publication Number Publication Date
CN114996201A CN114996201A (en) 2022-09-02
CN114996201B true CN114996201B (en) 2022-09-30

Family

ID=83021409

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210896835.4A Active CN114996201B (en) 2022-07-28 2022-07-28 Routing system based on Die interconnection

Country Status (1)

Country Link
CN (1) CN114996201B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117056157B (en) * 2023-10-11 2024-01-23 沐曦集成电路(上海)有限公司 Register hierarchy verification method, storage medium and electronic equipment

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2460331A (en) * 2008-05-30 2009-12-02 Intel Corp Protocol shim for IP core incorporation in a PC
CN104052663A (en) * 2013-03-14 2014-09-17 中国人民解放军信息工程大学 Large-scale on-chip chip interconnecting method and routing algorithm for realizing interconnecting structure
CN105630727A (en) * 2014-11-07 2016-06-01 华为技术有限公司 Access method, apparatus and system among multi-SoC nodes
CN108880840A (en) * 2017-05-10 2018-11-23 中兴通讯股份有限公司 The method and apparatus for obtaining access path
CN111104775A (en) * 2019-11-22 2020-05-05 核芯互联科技(青岛)有限公司 Network-on-chip topological structure and implementation method thereof
CN111710662A (en) * 2020-07-01 2020-09-25 无锡中微亿芯有限公司 Universal multi-die silicon stacking interconnection structure
CN112835848A (en) * 2021-02-05 2021-05-25 中国电子科技集团公司第五十八研究所 Inter-chip interconnection bypass system of interconnection bare chip and communication method thereof
CN113590508A (en) * 2021-09-30 2021-11-02 沐曦科技(北京)有限公司 Dynamic reconfigurable memory address mapping method and device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6874014B2 (en) * 2001-05-29 2005-03-29 Hewlett-Packard Development Company, L.P. Chip multiprocessor with multiple operating systems

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2460331A (en) * 2008-05-30 2009-12-02 Intel Corp Protocol shim for IP core incorporation in a PC
CN104052663A (en) * 2013-03-14 2014-09-17 中国人民解放军信息工程大学 Large-scale on-chip chip interconnecting method and routing algorithm for realizing interconnecting structure
CN105630727A (en) * 2014-11-07 2016-06-01 华为技术有限公司 Access method, apparatus and system among multi-SoC nodes
CN108880840A (en) * 2017-05-10 2018-11-23 中兴通讯股份有限公司 The method and apparatus for obtaining access path
CN111104775A (en) * 2019-11-22 2020-05-05 核芯互联科技(青岛)有限公司 Network-on-chip topological structure and implementation method thereof
CN111710662A (en) * 2020-07-01 2020-09-25 无锡中微亿芯有限公司 Universal multi-die silicon stacking interconnection structure
CN112835848A (en) * 2021-02-05 2021-05-25 中国电子科技集团公司第五十八研究所 Inter-chip interconnection bypass system of interconnection bare chip and communication method thereof
CN113590508A (en) * 2021-09-30 2021-11-02 沐曦科技(北京)有限公司 Dynamic reconfigurable memory address mapping method and device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
MPCC: Multi-path routing packet connect circuit for network-on-chip;Gaoming Du 等;《2015 IEEE 9th International Conference on Anti-counterfeiting, Security, and Identification (ASID)》;20160215;第99-104页 *
一种高速低功耗多端口寄存器堆的设计;丛高建 等;《半导体学报》;20070430;第614-618页 *
芯片叠层型系统级封装设计优化方法;陈靖;《电子产品世界》;20180404;第38-40、44页 *

Also Published As

Publication number Publication date
CN114996201A (en) 2022-09-02

Similar Documents

Publication Publication Date Title
US10044642B2 (en) Storage device in which forwarding-function-equipped memory nodes are mutually connected and data processing method
US7159017B2 (en) Routing mechanism for static load balancing in a partitioned computer system with a fully connected network
AU2004220640B2 (en) System and method for dymanic ordering in a network processor
CN114996201B (en) Routing system based on Die interconnection
US7774374B1 (en) Switching systems and methods using wildcard searching
KR20020026265A (en) Network processor processing complex and mrthods
CN114338594B (en) ARP (Address resolution protocol) response-substituting method, device, equipment and storage medium in Kubernetes environment
CN110413845B (en) Resource storage method and device based on Internet of things operating system
CN114844827B (en) Shared storage-based spanning tree routing hardware architecture and method for network-on-chip
US6631421B1 (en) Recursive partitioning of networks
CN112165505B (en) Decentralized data processing method, electronic device and storage medium
JP2003198356A (en) Semiconductor chip and integrated circuit
US20200192842A1 (en) Memory request chaining on bus
CN116471224A (en) Communication system, method and related device
CN109582242B (en) Address determination method and device for cascade memory array system and electronic equipment
US6408365B1 (en) Multiprocessor system having means for arbitrating between memory access request and coherency maintenance control
CN105786733B (en) Method and device for writing TCAM (ternary content addressable memory) entries
US11914540B2 (en) On-chip integrated circuit, data processing device, and data processing method
CN114024844B (en) Data scheduling method, data scheduling device and electronic equipment
CN116016448A (en) Service network access method, device, equipment and storage medium
CN111343107B (en) Information processing method, Ethernet switching chip and storage medium
CN112463680A (en) Data transfer method and device
CN115309693A (en) Integrated circuit, data processing apparatus and method
CN113411257B (en) Method, device, computing equipment and storage medium for transmitting message
CN112052074B (en) Processor modeling system and processor modeling method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant