CN111755435B - Multi-die FPGA for integrating HBM memory dies by utilizing silicon connection layer - Google Patents

Multi-die FPGA for integrating HBM memory dies by utilizing silicon connection layer Download PDF

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CN111755435B
CN111755435B CN202010620175.8A CN202010620175A CN111755435B CN 111755435 B CN111755435 B CN 111755435B CN 202010620175 A CN202010620175 A CN 202010620175A CN 111755435 B CN111755435 B CN 111755435B
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hbm
bare chip
fpga
silicon
node
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CN111755435A (en
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徐彦峰
范继聪
单悦尔
闫华
张艳飞
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

Abstract

The application discloses utilize silicon connecting layer integrated HBM storage bare chip's many bare chip FPGA, relate to FPGA technical field, this many bare chip FPGA internally designs active silicon connecting layer and integrates FPGA bare chip and HBM storage bare chip on it, silicon connecting layer internally lays silicon connecting layer interconnection frame, HBM storage bare chip inserts silicon connecting layer interconnection frame, form HBM node with a plurality of network interface and a plurality of router, the inside existing bare chip routing node of FPGA bare chip inserts silicon connecting layer interconnection frame and HBM node forms bigger on-chip network, HBM node can use a plurality of routers simultaneously with the inside a plurality of bare chip routing node transmission data of FPGA bare chip, this structure has realized the high-efficient communication interconnection of HBM storage bare chip and FPGA bare chip, have high memory bandwidth, high data input output.

Description

Multi-die FPGA for integrating HBM memory dies by utilizing silicon connection layer
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a multi-die FPGA for integrating HBM (high-performance memory) memory dies by utilizing a silicon connection layer.
Background
An FPGA (Field Programmable Gate Array) is a Programmable logic device, and is widely applied to the fields of mobile communication, data centers, navigation guidance, automatic driving, and the like. With the rapid development of application drivers and integrated circuit manufacturing processes, the scale of FPGAs is getting larger and larger, the demand of storage and operation of large data volume for high bandwidth storage is increasing continuously, and HBM (high bandwidth memory) is a novel memory chip, and has the advantages of large capacity and high bit width, and the FPGA supports HBM to become the current mainstream trend.
Disclosure of Invention
The present invention provides a multi-die FPGA for integrating HBM memory dies by using silicon connection layers, aiming at the above problems and technical requirements, and the technical solution of the present invention is as follows:
a multi-die FPGA for integrating HBM memory dies by utilizing a silicon connection layer comprises a substrate, the silicon connection layer arranged on the substrate in a stacking mode, the FPGA dies and the HBM memory dies arranged on the silicon connection layer in the stacking mode, wherein the silicon connection layer covers all the FPGA dies and all the HBM memory dies;
the FPGA bare chip comprises a bare chip NOC network, a silicon stacking connection module and a connection point leading-out terminal, wherein the silicon stacking connection module comprises a plurality of silicon stacking connection points, the bare chip NOC network comprises a plurality of bare chip routing nodes connected through routing channels, each bare chip routing node comprises a functional IP module and a router connected through a network interface, and adjacent bare chip routing nodes are connected through routing channels connected among the routers; a router in the bare chip routing node is connected with a silicon stacking connection point, and the silicon stacking connection point is connected with a corresponding connection point leading-out end through a top layer metal wire in a rewiring layer;
a silicon connection layer interconnection frame is arranged in the silicon connection layer, the silicon connection layer interconnection frame comprises routers, network interfaces and routing channels, adjacent routers are connected through the routing channels respectively, and each router is connected with one network interface;
the HBM interface of the HBM memory bare chip is simultaneously connected with N network interfaces in the silicon connection layer interconnection frame, N is more than or equal to 2, and the HBM memory bare chip and the N network interfaces and the N routers connected with the HBM memory bare chip form an HBM node; and the connection point leading-out end connected with the bare chip routing node on the FPGA bare chip is connected to a router in the silicon connection layer interconnection frame, and the HBM node is simultaneously in interconnection communication with the N bare chip routing nodes in the FPGA bare chip.
The further technical scheme is that FIFOs connected with network interfaces in a silicon connection layer interconnection frame are further arranged in the silicon connection layer, each FIFO, the network interfaces connected with the FIFO and a router form a transfer node, and each HBM node is simultaneously in interconnection communication with N bare chip routing nodes through N transfer nodes.
Dividing data to be transmitted into N groups of subdata by each HBM node, wherein the sum of bit widths of the N groups of subdata is the bit width of the data to be transmitted, the bit widths of the N groups of subdata are the same or different, and the HBM nodes transmit the N groups of subdata to N bare chip routing nodes in the FPGA bare chip through N routers connected with the HBM nodes respectively;
and/or the N bare chip routing nodes in the FPGA bare chip respectively transmit the N groups of sub-data to the HBM node through the N routers connected with the HBM node, and the HBM node combines the N groups of sub-data to form high-bit-width data.
Each router in the network on the silicon connection layer chip comprises 5 × 5 intercommunicating switch arrays and 5 groups of input and output ports connected with the intercommunicating switch arrays, wherein one group of input and output ports are connected with corresponding network interfaces, and the other 4 groups of input and output ports are respectively arranged in four different directions and are respectively used for being connected with routers adjacent to the four directions; the routers form a two-dimensional interconnect array.
The beneficial technical effects of the invention are as follows:
the multi-die FPGA internally designs an active silicon connection layer and integrates an FPGA die and an HBM storage die on the active silicon connection layer, a silicon connection layer interconnection frame is arranged inside the silicon connection layer, the HBM storage die is connected into the silicon connection layer interconnection frame and forms an HBM node with a plurality of network interfaces and a plurality of routers, an existing die routing node inside the FPGA die is connected into the silicon connection layer interconnection frame and forms a larger network on a chip with the HBM node, the HBM node can use the plurality of routers to transmit data with the plurality of die routing nodes inside the FPGA die at the same time, and the structure realizes efficient communication interconnection of the HBM storage die and the FPGA die and has high storage bandwidth and high data input and output.
Drawings
FIG. 1 is a cross-sectional view of the structure of a multi-die FPGA of the present application.
FIG. 2 is a schematic diagram of one internal connection of the multi-die FPGA of the present application.
Fig. 3 is a schematic diagram of a connection structure of a router and a network interface in a silicon connection layer interconnection framework.
FIG. 4 is another schematic diagram of the internal connections of the multi-die FPGA of the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses utilize many bare-dies FPGA of silicon connecting layer integrated HBM memory die, please refer to fig. 1, this many bare-dies FPGA includes base plate 1, silicon connecting layer 2 and the range upon range of FPGA bare-die and HBM memory die that set up on silicon connecting layer 2 of range upon range of setting in proper order from bottom to top, and in actual implementation, this FPGA still includes the encapsulation shell that is used for protecting each subassembly of encapsulation in base plate 1, silicon connecting layer 2 and FPGA bare-die outsidely to and still include the pin etc. that is used for the signal to draw forth that links to each other with the base plate, these conventional structures are not shown in detail in fig. 1.
The FPGA die in the application is different from a conventional FPGA die, logic resources inside the conventional FPGA die mainly comprise CLBs, PLBs, BRAMs, DSPs, PCs, IOBs and the like, each logic resource is provided with an interconnection resource module (INT) with the same structure and distributed around the logic resource, and horizontal or vertical connecting lines among all the logic resources are connected through the INT module. The FPGA bare chip in the application also comprises a specially designed silicon stacking connection module LNK, each silicon stacking connection module comprises a plurality of silicon stacking connection points 3, and the FPGA bare chip in the application replaces certain conventional logic resources in the conventional FPGA bare chip into the silicon stacking connection module. And conventional logic resources at any position can be replaced according to the signal interconnection requirement, for example, for the existing conventional Column-Based FPGA architecture, the silicon stacking connection module may be disposed in the row-Column structure where the CLB is located, or the silicon stacking connection module may be disposed in the row-Column structure where the BRAM is located to obtain the FPGA die in the present application.
Each silicon stacking connection module in the FPGA bare chip in the application also has an interconnection resource module distributed around the silicon stacking connection module, so that the winding structure of the FPGA bare chip in the application can be consistent with that of a conventional FPGA bare chip without changing. The silicon stacking connection module is connected with horizontal or vertical connecting lines between other logic resources through an INT module, and the silicon stacking connection module LNK is directly connected with an interconnection switch in the INT of the corresponding interconnection resource module and is a part of an interconnection line. The silicon stacking connection module LNK and the interconnection switch can be fully interconnected or partially interconnected according to the requirement of connectivity.
The FPGA bare chip further comprises a connection point leading-out terminal 4 corresponding to the internal silicon stacking connection point 3, the silicon stacking connection point 3 on the FPGA bare chip is connected with the corresponding connection point leading-out terminal 4 through a top layer metal wire 5 in a rewiring layer (RDL layer), and the silicon stacking connection point 3 and the connection point leading-out terminal 4 are located on different planes. The connection point terminals 4 are generally arranged in a row-column configuration along the first direction and the second direction according to the stack interconnection needs. In addition, in order to achieve higher communication bandwidth, multiple rows/multiple columns of connection point leading-out terminals 4 can be arranged, that is, multiple rows of connection point leading-out terminals 4 are arranged in each FPGA die along the first direction, and/or multiple columns of connection point leading-out terminals 4 are arranged along the second direction, so that efficient two-dimensional cascade of multiple rows and multiple columns is achieved. When the plurality of rows/columns of the connection point leading-out terminals 4 are arranged along each direction, they may be arranged at regular intervals or at random. Silicon through holes 6 are further formed in the silicon connection layer 2, and the IOB on the FPGA bare chip is connected to the substrate 1 through the silicon through holes 6 in the silicon connection layer 2 so as to finally lead out signals.
Each FPGA die has a die NOC network formed therein, and referring to fig. 2, the die NOC network includes a plurality of die routing nodes connected by routing channels, each die routing node includes functional IP modules and routers (R) connected by Network Interfaces (NI), and adjacent die routing nodes are connected by routing channels connected between the routers R, such as the routing channels in fig. 2, which are bidirectional interconnection lines between the routers inside the FPGA die. According to the actual interconnection needs, routers in the die routing nodes needing to be interconnected with the outside in the die NOC network are connected with the silicon stacking connection points 3, and the silicon stacking connection points 3 are connected with the corresponding connection point leading-out terminals 4 through top layer metal wires in the rewiring layer.
A silicon connection layer interconnection frame is disposed in the silicon connection layer 2, and referring to fig. 2, the internal structure of the FPGA die and the structure of the HBM memory die are shown by dotted lines, and the structure in the silicon connection layer 2 is shown by solid lines. The silicon connection layer interconnection framework comprises routers (R), Network Interfaces (NI) and routing channels, adjacent routers (R) are respectively connected through the routing channels, each router R is connected with one network interface NI, and connection lines between adjacent routers in the silicon connection layer 2 in the figure represent the routing channels. In the present application, please refer to fig. 3, each router R includes a 5 × 5 intercommunicating switch array (Cross bar in the figure) and five groups of input/output ports connected thereto, the intercommunicating switch array realizes interconnection under the control of a corresponding control module, and the specific form and control manner of the Cross bar structure are conventional technologies, and the present application does not expand in detail. One of the input/output ports is connected to the corresponding network interface NI, and the other four input/output ports are respectively arranged in four different directions, such as East, South, West, and North directions in the figure, and are respectively used for connecting with the adjacent routers in the four directions, and one input/output port in each direction may be connected to any one input/output port in the adjacent router. The input port of each group of input/output ports is provided with a buffer, and the output port is provided with a register. It should be noted that the shape of the interconnection frame of the silicon connection layer is not limited, and it is not necessary to arrange a square structure, and it is not necessary to arrange a router on each lattice in the silicon connection layer 2, and it is only necessary to connect adjacent routers by using routing channels, so that the lengths of the routing channels between adjacent routers in the interconnection frame of the silicon connection layer may be different as shown in fig. 2.
The HBM interface of the HBM memory die is simultaneously connected to N network interfaces in the silicon connection layer interconnection frame, where N is greater than or equal to 2, for example, fig. 2 illustrates that the HBM memory die is simultaneously connected to three network interfaces, so that the HBM memory die is connected to the silicon connection layer interconnection frame, and the N network interfaces and the N routers connected to the HBM memory die form an HBM node. At the same time, the connection point terminals 4 on the FPGA die that are connected to the die routing nodes are connected to routers in the silicon connection layer interconnect frame. With this structure, the bare chip NOC network, the HBM memory bare chips and the silicon connection layer interconnection framework together form a larger-scale network on chip inside the multi-bare chip FPGA, the network on chip comprises NOC nodes which are respectively interconnected in two directions through routing channels, and the NOC nodes comprise bare chip routing nodes and HBM nodes.
Based on the large-scale network on chip formed, each HBM node can simultaneously communicate with N die routing nodes by means of N routers inside it: when the HBM nodes send data, each HBM node divides the data to be transmitted into N groups of subdata, the sum of bit widths of the N groups of subdata is the bit width of the data to be transmitted, the bit widths of the N groups of subdata are the same or different, and the HBM nodes respectively transmit the N groups of subdata to N bare chip routing nodes in the FPGA bare chip through N routers connected with the HBM nodes. When the HBM node receives data, N bare chip routing nodes in the FPGA bare chip respectively transmit N groups of sub-data to the HBM node through N routers connected with the HBM node, and the HBM node combines the N groups of sub-data to form high-bit-width data. Through the process, high-bandwidth and high-data input and output between the HBM memory bare chip and the FPGA bare chip can be realized, and the memory bandwidth of the multi-bare chip FPGA can be improved. For example, the HBM node divides 256-bit wide data to be transmitted into 4 groups of 64-bit wide sub-data, and sends the 4 groups of 64-bit wide sub-data to the 4 die routing nodes of the FPGA die.
Further, referring to fig. 4, the multi-die FPGA of the present application is not a single FPGA die structure, but is a multi-die FPGA structure, that is, the multi-die FPGA includes a plurality of FPGA dies therein, the plurality of FPGA dies are all stacked on the same silicon connection layer 2, and the silicon connection layer 2 covers all FPGA dies. The plurality of FPGA dies may be arranged on the silicon connection layer 2 along a one-dimensional direction, or may be arranged on the silicon connection layer 2 in a two-dimensional stacking manner, that is, arranged on a horizontal plane along two directions, i.e., two directions, such as fig. 4, where four FPGA dies are arranged on the silicon connection layer 2 in a two-dimensional stacking manner. The plurality of FPGA bare chips can be reasonably arranged on the silicon connection layer 2, and the whole area of the whole FPGA is smaller due to the fact that the FPGA bare chips are compactly arranged on the silicon connection layer 2 according to the shapes and the areas of the FPGA bare chips. The structure of each FPGA bare chip is as described above, and when the multi-die FPGA includes a plurality of FPGA bare chips, the bare chip connection point terminals 4 on each FPGA bare chip connected to the bare chip routing node are connected to the router in the silicon connection layer interconnection frame, so that the HBM node can achieve interconnection communication with the plurality of FPGA bare chips.
Meanwhile, the multi-die FPGA may further include a plurality of HBM memory dies, for example, as shown in fig. 4, two HBM memory dies are included, each HBM memory die is connected to a silicon connection layer interconnection frame by using the above-mentioned architecture to form an HBM node, each HBM node may implement interconnection communication with the FPGA die in the above-mentioned process, and in addition, the HBM nodes may also implement interconnection communication.
FIFOs can be additionally arranged in the silicon connection layer 2, each FIFO is connected with one network interface in the interconnection frame of the silicon connection layer, and each FIFO, the network interface connected with the FIFO and the router form a transfer node. Each HBM node transmits N groups of sub data obtained by splitting and synthesizing data to be transmitted to the N transit nodes respectively, and then the N transit nodes are simultaneously transmitted to the N bare chip routing nodes in the FPGA bare chip.
The structure of the application is favorable for improving the storage bandwidth of the multi-die FPGA, the die NOC network inside the FPGA die can have multiple functions, but is particularly suitable for the situation when the AI module is built in the FPGA die, the AI module needs high-bandwidth data input/output during working, the die routing node inside the FPGA die is formed by a plurality of nodes, the functional IP module is an AI engine inside the AI module at the moment, the application is directly expressed by the AI engine as shown in FIG. 4, and the requirement can be well met by utilizing the structure.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (4)

1. A multi-die FPGA integrating HBM memory dies by utilizing a silicon connection layer is characterized by comprising a substrate, the silicon connection layer arranged on the substrate in a stacking mode, the FPGA dies and the HBM memory dies arranged on the silicon connection layer in the stacking mode, and the silicon connection layer covers all the FPGA dies and the HBM memory dies;
the FPGA bare chip comprises a bare chip NOC network, a silicon stacking connection module and a connection point leading-out terminal, wherein the silicon stacking connection module comprises a plurality of silicon stacking connection points, the bare chip NOC network comprises a plurality of bare chip routing nodes connected through routing channels, each bare chip routing node comprises a functional IP module and a router connected through a network interface, and adjacent bare chip routing nodes are connected through routing channels connected among the routers; a router in the bare chip routing node is connected with a silicon stacking connection point, and the silicon stacking connection point is connected with a corresponding connection point leading-out end through a top layer metal wire in a rewiring layer;
a silicon connection layer interconnection frame is arranged in the silicon connection layer, the silicon connection layer interconnection frame comprises routers, network interfaces and routing channels, adjacent routers are connected through the routing channels respectively, each router is connected with one network interface, and 4 groups of input/output ports of each router, which are arranged in four different directions, are connected with the routers adjacent to the four directions respectively;
the HBM interface of the HBM memory bare chip is simultaneously connected with N network interfaces in the silicon connection layer interconnection frame, N is more than or equal to 2, and the HBM memory bare chip and the N network interfaces and the N routers connected with the HBM memory bare chip form an HBM node; connection point outlets on the FPGA die connected to die routing nodes are connected to routers in the silicon connection layer interconnect frame, and the HBM node simultaneously communicates with N die routing nodes on the FPGA die using a plurality of routers.
2. The multi-die FPGA of claim 1, wherein FIFOs connected to the network interfaces in the interconnection framework of the silicon connection layer are further disposed in the silicon connection layer, each FIFO and the network interface and the router connected to the FIFO form a transit node, and each HBM node is in interconnection communication with N die routing nodes through N transit nodes.
3. The multi-die FPGA of claim 1 or 2,
each HBM node divides data to be transmitted into N groups of subdata, the sum of bit widths of the N groups of subdata is the bit width of the data to be transmitted, the bit widths of the N groups of subdata are the same or different, and the HBM node transmits the N groups of subdata to N bare chip routing nodes in the FPGA bare chip through N routers connected with the HBM node;
and/or the N bare chip routing nodes in the FPGA bare chip respectively transmit the N groups of sub-data to the HBM node through N routers connected with the HBM node, and the HBM node combines the N groups of sub-data to form high-bit-width data.
4. The multi-die FPGA of claim 1, wherein each router in the silicon-on-chip network comprises 5 × 5 intercommunicating switch arrays and 5 sets of input/output ports connected thereto, wherein one set of input/output ports is connected to a corresponding network interface, and the remaining 4 sets of input/output ports are respectively arranged in four different directions for connecting to routers adjacent to the four directions; the routers form a two-dimensional interconnect array.
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US20150109024A1 (en) * 2013-10-22 2015-04-23 Vaughn Timothy Betz Field Programmable Gate-Array with Embedded Network-on-Chip Hardware and Design Flow
US20180102776A1 (en) * 2016-10-07 2018-04-12 Altera Corporation Methods and apparatus for managing application-specific power gating on multichip packages
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