CN111753481B

CN111753481B - Multi-die FPGA utilizing active silicon connection layer to balance delay

Info

Publication number: CN111753481B
Application number: CN202010622789.XA
Authority: CN
Inventors: 单悦尔; 徐彦峰; 范继聪; 张艳飞; 闫华
Original assignee: Wuxi Zhongwei Yixin Co Ltd
Current assignee: Wuxi Zhongwei Yixin Co Ltd
Priority date: 2020-07-01
Filing date: 2020-07-01
Publication date: 2022-03-22
Anticipated expiration: 2040-07-01
Also published as: CN111753481A

Abstract

The application discloses a multi-die FPGA utilizing balance delay of an active silicon connection layer, and relates to the technical field of FPGAs (field programmable gate arrays). the multi-die FPGA comprises a substrate, a silicon connection layer on the substrate and a plurality of FPGA dies stacked on the silicon connection layer in a two-dimensional stacking mode, wherein silicon stacking connection points built in the FPGA dies are connected to connection point leading-out ends, and the connection point leading-out ends can be connected to other dies through cross-die connection lines in two directions in the active silicon connection layer so as to realize two-dimensional interconnection communication between the dies; active devices arranged inside the silicon connecting layer can flexibly adjust the time delay of the cross-chip signals, realize the time delay balance of the multi-bare-chip FPGA cross-chip signals and accelerate the time sequence convergence of the design.

Description

Multi-die FPGA utilizing active silicon connection layer to balance delay

Technical Field

The invention relates to the technical field of semiconductors, in particular to a multi-die FPGA utilizing an active silicon connection layer to balance delay.

Background

An FPGA (Field Programmable Gate Array) is a Programmable logic device of hardware, and is widely applied to prototype verification in integrated circuit design besides the fields of mobile communication, data center, etc., so as to effectively verify the correctness of circuit functions and accelerate the circuit design speed. The prototype verification needs to realize circuit design by using programmable logic resources inside the FPGA, the demand for the number of the programmable logic resources of the FPGA is continuously increased along with the continuous increase of the scale of the integrated circuit and the realization of complex functions, the number of the programmable resources of the FPGA becomes a larger bottleneck due to the continuous increase of the subsequent technical development and demand, and a larger challenge is provided for the development of the industry. The increase in the FPGA scale represents an increasing chip area, which leads to an increase in chip processing difficulty and a decrease in chip production yield.

Some patents have proposed a method for designing chip interconnects by using silicon-on-chip (SSI), for example, the patent with application number 2016800598883 proposes a stacked die interconnect without interposer, which uses a plurality of discrete interconnect dies to implement signal interconnects between two adjacent dies; another example is patent application No. 2017800501825, which proposes a separate interface for silicon stacked interconnect technology integration that uses an entire interposer as an interconnect carrier to achieve signal interconnection of two adjacent IC dies. However, the above two patents are limited by the defects of the chip itself and the structure design, and both can only interconnect two adjacent IC dies arranged side by side, and can only implement signal interconnection in a single direction, so that the structure limitation is large in practical application, and the signal delay of the device is difficult to design and adjust due to the structure limitation, and the complex circuit requirement of the large-scale integrated circuit is difficult to meet in practice.

Disclosure of Invention

The present invention provides a multi-die FPGA utilizing active silicon connection layer to balance delay, which solves the above problems and technical requirements, and the technical solution of the present invention is as follows:

a multi-die FPGA utilizing active silicon connection layer balance delay comprises a substrate, a silicon connection layer arranged on the substrate in a stacking mode and a plurality of FPGA dies arranged on the silicon connection layer in a stacking mode, wherein the FPGA dies are arranged on the silicon connection layer in a two-dimensional stacking mode, and the silicon connection layer covers all the FPGA dies;

each FPGA bare chip comprises a plurality of configurable function modules, interconnection resource modules distributed around each configurable function module and a connection point leading-out end, each configurable function module in the FPGA bare chip at least comprises a programmable logic unit, a silicon stacking connection module and an input/output port, each silicon stacking connection module comprises a plurality of silicon stacking connection points, the programmable logic units in the FPGA bare chip are respectively connected with the silicon stacking connection points and the input/output ports through the interconnection resource modules, and the silicon stacking connection points in the FPGA bare chip are connected with the corresponding connection point leading-out ends through top layer metal wires in a rewiring layer;

the connection point leading-out end in each FPGA bare chip is connected with the corresponding connection point leading-out end in other FPGA bare chips through a cross bare chip connection wire in the silicon connection layer, and an active device is distributed in the silicon connection layer and used for adjusting signal delay on a signal transmission path between the two FPGA bare chips; each FPGA bare chip can be connected with any other FPGA bare chip through a cross-bare-chip connecting line in the silicon connecting layer, the cross-bare-chip connecting line which is communicated with each FPGA bare chip is arranged in the silicon connecting layer along a first direction and a second direction in a crossed mode, and the first direction and the second direction are vertical to each other in the horizontal direction; and the input/output port in the FPGA bare chip is connected to the substrate through the silicon through hole on the silicon connecting layer.

The further technical scheme is that the active devices distributed in the silicon connection layer comprise buffers, each buffer comprises an even number of inverters which are sequentially connected in series, and a cross-die connection line between connection point leading-out ends of two FPGA dies penetrates through the buffers.

The further technical scheme is that at least two buffers with different time delay sizes are distributed in the silicon connecting layer, and the buffers with different time delay sizes adjust signal transmission paths to have different signal delays.

The method comprises the following steps that each buffer comprises a plurality of buffer paths connected in parallel through switches, when the switches are closed, the buffer paths are connected into the circuits, when the number of the connected buffer paths is different, the buffers have different time delay sizes, the signal transmission paths are adjusted to have different signal delays, the larger the number of the connected buffer paths is, the smaller the time delay of the buffers is, and the switching of the opening and closing states of the switches in the buffer paths is realized by a metal selection technology.

The further technical scheme is that the buffer comprises 4 paths of buffer paths connected in parallel through a switch, and when the number of the buffer paths controlled to be accessed through the metal selection technology is respectively 1-4 paths, the buffer correspondingly and sequentially has BUF1X time delay, BUF2X time delay, BUF3X time delay and BUF4X time delay.

The buffer also comprises a Schmitt trigger circuit which is connected in series with the output ends of the even number of inverters.

The active device arranged in the silicon connection layer also comprises a first type trigger, the first type trigger adopts a synchronous design mode, a cross-bare chip connecting line between leading-out ends of connection points of the two FPGA bare chips is respectively connected with an input end and an output end of the first type trigger through a change-over switch, when the state of the change-over switch is switched, the first type trigger is connected or not connected into a signal transmission path between the two FPGA bare chips, the switching of the on-off state of the change-over switch is realized by a metal selection technology, and the clock frequency of the first type trigger is a multiple of the system clock frequency.

The multi-die FPGA further comprises a second type of trigger which adopts an asynchronous design mode and is used for clock domain crossing communication between two FPGA dies.

The technical scheme is that a second type of trigger is arranged in the silicon connecting layer and comprises a first D trigger and a second D trigger, the D end of the first D trigger is connected with one FPGA bare chip to acquire an enabling signal, the Q end of the first D trigger is connected with the D end of the second D trigger, the Q end of the second D trigger is connected with an active device output enabling signal in the silicon connecting layer to control the on-off of the active device output enabling signal, and the clock ends of the first D trigger and the second D trigger are connected with the other FPGA bare chip to acquire a clock signal.

The technical scheme is that the second type of trigger is respectively arranged inside the two FPGA bare chips, and the two FPGA bare chips carry out handshake signals interaction through the second type of trigger.

A first top layer metal wire between a first silicon stacking connection point in any first FPGA bare chip and a corresponding first connection point leading-out end, a cross-bare chip connection wire between the first connection point leading-out end and a second connection point leading-out end on any second FPGA bare chip, and a second top layer metal wire between a second connection point leading-out end on the second FPGA bare chip and a corresponding second silicon stacking connection point form a signal transmission path; the signal delay of the signal transmission path corresponds to the total wiring distance of the signal transmission path, the total wiring distance is the sum of the winding distance of the first top-layer metal wire, the winding distance of the cross-bare-chip connecting wire and the winding distance of the second top-layer metal wire, the longer the total wiring distance is, the higher the signal delay of the signal transmission path is, and when the total wiring distance of the two signal transmission paths is adjusted to be equal, the signal delays of the two signal transmission paths are equal; the routing distances of the top layer metal lines and the cross-bare chip connecting lines are adjusted through different routing structures.

The further technical scheme is that the silicon stacking connection point is directly connected with an interconnection switch in the interconnection resource module, and the silicon stacking connection point and the interconnection switch are fully or partially interconnected.

The further technical scheme is that the cross-die connecting lines which are communicated with the FPGA dies are arranged in a silicon connecting layer in a layered mode.

The further technical scheme is that each silicon stacking connection module comprises N rows and M columns of silicon stacking connection points, each silicon stacking connection module comprises a high-delay silicon stacking connection point, a middle-delay silicon stacking connection point and a low-delay silicon stacking connection point, and in a rewiring layer, the winding distance of a top layer metal wire connected with the high-delay silicon stacking connection point, the winding distance of a top layer metal wire connected with the middle-delay silicon stacking connection point and the winding distance of a top layer metal wire connected with the low-delay silicon stacking connection point are sequentially reduced.

The FPGA chip further comprises other function modules, wherein the other function modules comprise a DSP module and/or a BRAM module, the other function modules are respectively connected with the silicon stacking connection point and the input/output port through the interconnection resource module, the programmable logic units, the silicon stacking connection module and the other function modules are arranged to form a two-dimensional array, and the silicon stacking connection module is arranged in a row-column structure where the programmable logic units are located and in a row-column structure where the other function modules are located.

The further technical scheme is that the size of the silicon stacking connection module is smaller than that of other functional modules, a row and column structure where the other functional modules are located forms a vacant area at the silicon stacking connection module, and at least one of a capacitor, a test circuit, a noise reduction circuit and a monitoring circuit is arranged at the vacant area.

The further technical scheme is that the connection point leading-out ends in each FPGA bare chip are distributed according to a row-column structure along a first direction and a second direction, and a plurality of rows of connection point leading-out ends are distributed in each FPGA bare chip along the first direction and/or a plurality of columns of connection point leading-out ends are distributed along the second direction.

The technical scheme is that a plurality of rows of connection point leading-out ends are uniformly distributed in each FPGA bare chip along a first direction at the same intervals; or, a plurality of rows of connection point terminals are randomly distributed in each FPGA bare chip along the first direction.

The further technical scheme is that the plurality of FPGA bare chips are arranged on the silicon connecting layer according to the shape and the area of each FPGA bare chip.

The beneficial technical effects of the invention are as follows:

1. a plurality of FPGA bare chips in the multi-bare-chip FPGA can realize two-dimensional interconnection communication through the cross bare chip connecting line arranged along two directions in the silicon connecting layer, and the multi-bare-chip FPGA can flexibly adjust the cross-chip signal delay by adding an active device in the silicon connecting layer, so that the multi-bare-chip FPGA can realize the cross-chip signal delay balance, and the designed time sequence convergence is accelerated. Active devices in the silicon connecting layer include but are not limited to BUF, triggers and other active devices, the BUF size can flexibly select device driving capability through Metal Option, different time delays are realized, and multi-die FPGA cross-chip signal time delay is balanced; when the BUF is realized, the Schmitt trigger characteristic can be increased, noise interference is reduced, and the quality of a cross-chip signal is improved; and the increase of the trigger can improve the cross-chip application frequency and reduce the frequency limit of the cross-chip signal delay.

2. The multi-die FPGA can also realize cross-die signal delay balance by adjusting the top layer metal wire winding distance in an efficient manner, and design timing sequence convergence is accelerated. The cascade structure of the multiple FPGA bare chips supports the realization of large-scale and large-area FPGA chips by cascading the multiple small-scale and small-area FPGA bare chips, not only can reduce the processing difficulty, improve the production yield of the chips and accelerate the design speed, but also can improve the flexibility of resource layout in application and accelerate the time sequence convergence of the design by the cross-bare chip signal delay balancing technology.

3. The cross-bare-chip connecting line in the silicon connecting layer also has a preset winding structure, and when the winding distances are different, the signal transmission delays are different, so after the FPGA bare chips are designed, the signal delay among the FPGA bare chips can be further adjusted through the winding distances of the cross-bare-chip connecting line in the silicon connecting layer, and the cross-bare-chip signal delay is simple, feasible and low in cost.

4. Besides the conventional configurable functional module, each FPGA bare chip also comprises a newly added configurable functional module special for bare chip signal extraction, namely a silicon stacking connection point, and the FPGA bare chips carry out signal extraction and interconnection through the special silicon stacking connection point, so that the FPGA bare chip has the advantages of higher bandwidth, lower delay, lower power consumption and the like.

5 various circuit structures can be arranged in the vacant areas at the silicon stacking connection points inside each FPGA bare chip, so that the FPGA bare chips have better performance and stronger function.

6. The multi-bare-chip FPGA can also be provided with other bare chips of various types on the silicon connecting layer, and the other bare chips can also realize two-dimensional interconnection communication with the FPGA bare chips through the cross bare chip connecting line arranged in the silicon connecting layer along two directions, so that various types of bare chips can be flexibly integrated, FPGA chips with rich varieties and powerful functions facing different applications can be quickly realized, and the market is occupied.

Drawings

FIG. 1 is a schematic cross-sectional view of a multi-die FPGA of the present application.

Fig. 2 is an enlarged view of a portion of the structure in fig. 1.

FIG. 3 is a top down two-dimensional schematic of one configuration of the FPGA of the present application.

Fig. 4 is a schematic diagram of an internal structure of a conventional FPGA.

FIG. 5 is a schematic diagram of an internal structure of a conventional FPGA adopting a Column-Based architecture.

FIG. 6 is a block diagram of a conventional FPGA adopting the Column-Based architecture.

Fig. 7 is a schematic block diagram of an FPGA die in the present application when the block structure shown in fig. 6 is adopted.

Fig. 8 is a schematic diagram of connections between a silicon stacked connection module and an interconnection resource module inside an FPGA die in the present application.

Fig. 9 is a schematic diagram of a connection point terminal on an FPGA die in the present application.

Fig. 10 is a two-dimensional schematic diagram of an interconnect structure formed between FPGA dies through connection point leadouts in the present application.

FIG. 11 is a schematic diagram of the connection of active devices in a silicon connection layer between two FPGA dies.

FIG. 12 is a circuit diagram of an active device when selecting whether the device is plugged using Metal Option.

FIG. 13 is a layout when a buffer size is selected using Metal Option.

Fig. 14 is a block diagram of an implementation manner of a second type of flip-flop in the FPGA of the present application.

Fig. 15 is a structural diagram of an implementation manner of a handshake protocol of a second type of flip-flop in the FPGA of the present application.

Fig. 16 is a schematic diagram of the routing structure of the top metal lines within the RDL layer of the FPGA die and the routing structure of the cross-die wires in the silicon connection layer in the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application provides a multi-die FPGA utilizing active silicon connection layers to balance delay, wherein FIG. 1 is a cross-sectional schematic view of a packaging structure of the FPGA, FIG. 2 is an enlarged view of a part of the structure in FIG. 1, and FIG. 3 is a corresponding top view schematic view of FIG. 1. The FPGA comprises a substrate 1, a silicon connection layer 2 and a plurality of FPGA dies, which are stacked in sequence from bottom to top, for example, the structure shown in fig. 1 to 3 includes 6 FPGA dies, which are respectively represented by dies 1 to 6. In practical implementation, the FPGA further comprises a package housing for protecting the various components, packaged outside the substrate 1, the silicon connection layer 2 and the FPGA die, and further comprises pins for signal extraction, etc. connected to the substrate, which conventional structures are not shown in detail in fig. 1 and 2.

The FPGA of the application does not adopt a single FPGA bare chip structure, but comprises a plurality of FPGA bare chips, the plurality of FPGA bare chips are all stacked and arranged on the same silicon connection layer 2, and the plurality of FPGA bare chips are arranged on the silicon connection layer 2 in a two-dimensional stacking mode, namely are arranged along the horizontal direction and the vertical direction on the horizontal plane, as shown in FIG. 3. The plurality of FPGA bare chips can be reasonably arranged on the silicon connection layer 2, and are compactly arranged on the silicon connection layer 2 according to the shape and the area of each FPGA bare chip, so that the whole area of the whole FPGA is smaller, and the interconnection performance between the bare chips is better.

The internal structure of the FPGA bare chip and the connection mode of the FPGA bare chip and the silicon connection layer 2 are adjusted and designed elaborately. Next, the present application introduces specific connection structures and implementations between the FPGA die and the silicon connection layer 2:

the FPGA bare chip in the present application is different from a conventional FPGA bare chip, and first, the structure of the conventional FPGA bare chip is described as follows, please refer to the schematic structure shown in fig. 4, where the conventional FPGA bare chip is composed of configurable functional modules with multiple functions, and a common configurable functional module mainly includes a programmable logic unit (CLB or PLBs) and an input/output port (IOB), and sometimes includes some other functional modules, such as BRAM, DSP, PC, and the like. Each configurable functional module has an interconnection resource module (INT) with the same structure distributed around the configurable functional module, and horizontal or vertical connecting lines among the configurable functional modules are connected through the INT module. On the basis of the conventional structure, the FPGA bare chip in the application also comprises a silicon stacking connection module which is specially designed in the bare chip according to the signal interconnection requirement between bare chips, besides the conventional configurable function modules comprising the CLB, the IOB and other function modules, each silicon stacking connection module comprises a plurality of silicon stacking connection points, the silicon stacking connection module is a newly-added configurable function module which is specially used for leading out bare chip signals, and the FPGA bare chip in the application replaces some conventional configurable function modules in the conventional FPGA bare chip into the silicon stacking connection module. And the conventional configurable function module at any position can be replaced according to the signal interconnection requirement, for example, the conventional Column-Based FPGA architecture shown in fig. 5 is taken as an example, where each Column is the same module, for example, a CLB Column is a chip Column filled with CLB modules arranged from top to bottom. The height of each module is aligned with INT, the height of the CLB is equal to the INT height, the heights of other functional modules can be equal to a plurality of INT heights, the structure enables the whole FPGA to look like a two-dimensional array formed by INT, the heights of the modules in the array are consistent, the width of the same column is the same, but the widths of different columns can be different. Based on the two-dimensional array architecture, the silicon stacking connection module can be arranged in a row-column structure where the programmable logic unit is located, and can also be arranged in a row-column structure where other functional modules are located to obtain the FPGA bare chip in the application. The module size of the silicon stacking connection module is small, the height of the module is equal to the height of the CLB and INT, the width of the module is slightly smaller than the CLB, and the height and the width of other functional modules such as the DSP and the BRAM are larger than the CLB, so that an empty area is formed when the silicon stacking connection module is placed at the other functional modules (the DSP and the BRAM) with larger size, and at least one conventional circuit structure of a capacitor, a test circuit, a noise reduction circuit and a monitoring circuit can be arranged at the empty area to improve the circuit performance and enrich the functions.

The following examples are given: a schematic diagram of a conventional FPGA module using the architecture of fig. 5 is shown in fig. 6, which includes two other functional modules, namely, a DSP and a BRAM, in addition to a CLB, where the height of the CLB is equal to the height of INT, the height of the DSP is equal to 2 INT heights, and the height of the BRAM is equal to 4 INT heights. Based on the module structure shown in fig. 6, the CLB, the DSP, and the BRAM at any position may be replaced and set as the silicon stacking connection module to obtain the FPGA bare chip in the present application, for example, in fig. 7, the CLB column and the DSP column are both provided with the silicon stacking connection module LNK, and the CLB and one of the DSPs at the four corners are replaced and set as the silicon stacking connection module LNK. As can be seen from fig. 7, since the height of the DSP is equal to 2 INT heights, two silicon stack connection modules LNK are disposed in the height direction in the area where the DSP is originally arranged, and since the width of the DSP is greater than the width of the CLB, other conventional circuits, such as the TEST circuit TEST shown in fig. 7, may also be disposed in the vacant area in the width direction. Actual FPGA dies are also not necessarily limited to the Column-Based architecture illustrated in the present application, and there is no fixed location for the silicon stack connection modules inside the FPGA dies.

Each silicon stacking connection module in the FPGA bare chip in the application also has an interconnection resource module distributed around the silicon stacking connection module, so that the winding structure of the FPGA bare chip in the application can be consistent with that of a conventional FPGA bare chip without changing. The horizontal or vertical connection lines between the silicon stacking connection module and each other configurable functional module are all connected via the INT module, and the silicon stacking connection module LNK is directly connected to the interconnection switch in the INT module corresponding to the silicon stacking connection module, and is a part of the interconnection line, please refer to fig. 8. The silicon stacking connection module LNK and the interconnection switch can be fully interconnected or partially interconnected according to the requirement of connectivity. The FPGA die in the present application further includes a connection point terminal 4 corresponding to the internal silicon stack connection point 3, the silicon stack connection point 3 in the FPGA die is connected to the corresponding connection point terminal 4 through a top layer metal wire 5 in a redistribution layer (RDL layer), it should be noted that fig. 8 shows the silicon stack connection point 3 and the connection point terminal 4 on the same plane for illustrating the connection relationship between the two, but please refer to fig. 3, where the silicon stack connection point 3 and the connection point terminal 4 are actually on different planes. The connection point terminals 4 are generally arranged in a row-column structure along the first direction and the second direction according to the requirement of stacking interconnection, and the structure diagram can be referred to as fig. 9. With this structure, the die signals of the FPGA die have been connected by the silicon stack connection points 3 to connection point terminals 4. The connection point leading-out terminal 4 can be connected to the corresponding connection point leading-out terminal 4 in other FPGA bare chips through a cross bare chip connection wire 6 in the silicon connection layer 2, so that the FPGA bare chips are interconnected. Since the FPGA die is provided with the connection point terminals 4 along both the first direction and the second direction, the FPGA die can be connected to other FPGA dies in a two-dimensional direction by using the connection point terminals 4 in the two directions and combining the cross-die connection lines 6 in the two directions, please refer to the schematic diagram shown in fig. 10. In addition, in order to achieve higher communication bandwidth, multiple rows/multiple columns of connection point leading-out terminals 4 can be arranged, that is, multiple rows of connection point leading-out terminals 4 are arranged in each FPGA die along the first direction, and/or multiple columns of connection point leading-out terminals 4 are arranged along the second direction, so that efficient two-dimensional cascade of multiple rows and multiple columns is achieved. When the plurality of rows/columns of the connection point leading-out terminals 4 are arranged along each direction, they may be arranged at regular intervals or at random. The connection mode of the connection point terminal 4 and the silicon connection layer 2 may specifically be: the micro-convex ball grows on the FPGA bare chip, the connection point leading-out end 4 is connected with the silicon connection layer 2 through the micro-convex ball and is connected to other FPGA bare chips through the cross bare chip connection line inside the silicon connection layer 2, the micro-convex ball structure at the bottom of the FPGA bare chip can be seen in figure 2, and the micro-convex ball structure is not marked in detail any more.

The silicon connection layer 2 is internally provided with the cross-die connecting wire 6, the cross-die connecting wire 6 is distributed in the whole area or partial area of the silicon connection layer 2, and meanwhile, the silicon connection layer 2 covers all the FPGA dies, so each FPGA die can be connected to any other FPGA die through the cross-die connecting wire 6 according to the circuit requirement, the circuit interconnection between the dies is almost not limited in space, and the flexibility is far better than the structures of the two patents mentioned in the background technology. The inter-die connection lines 6 arranged inside the silicon connection layer 2 are arranged crosswise along a first direction and a second direction, the first direction and the second direction are mutually vertical in the horizontal direction, namely, the first direction and the second direction are two directions of the horizontal direction and the vertical direction matched with the die arrangement structure. Therefore, each FPGA die can be simultaneously connected with other FPGA dies in the first direction and the second direction through the cross-die connection 6 in the two directions, so that a two-dimensional interconnection structure is formed among the plurality of FPGA dies, as shown in fig. 3, the die 1 can be interconnected with the die 2 through the cross-die connection 6 in the first direction, and can also be interconnected with the die 4 through the cross-die connection 6 in the second direction, and the same is true for the rest of the dies. In each direction, each FPGA die can be interconnected not only with other adjacent FPGA dies by the cross-die connection 6, but also with other spaced FPGA dies by the cross-die connection 6, for example, as shown in fig. 1 to 3, the die 1 can be interconnected not only with the adjacent die 2 by the cross-die connection 6, but also with the die 3 by the cross-die connection 6, or even with other spaced dies. In addition, the FPGA die can be connected to different rows of FPGA dies simultaneously through the cross-die connection 6 in two directions, for example, in fig. 3, the die 1 can be connected to the die 6 through the cross-die connection 6. It should be noted that fig. 3 shows the cross-die connections between the spaced FPGA dies as crossing the surface of the intermediate FPGA dies, such as the cross-die connections between die 1 and die 3 crossing the surface of die 2, but this is merely for convenience of illustration of the connections, and practically all of the cross-die connections 6 are within the silicon connection layer 2, as shown in fig. 1 and 2. The cross-die connecting lines 6 are arranged in the silicon connecting layer 2 in a layered and crossed mode, and the cross-die connecting lines 6 in the same direction and the cross-die connecting lines 6 in different directions can be arranged in a layered and crossed mode, so that the cross-die connecting lines 6 are not influenced with each other. It should be noted that although the present application claims such a two-dimensional stacking scheme, the technical solution is also applicable to a one-dimensional stacking scheme, but only there is a die-crossing wire 6 in only one direction (lateral or longitudinal) inside the silicon connection layer 2.

The manufacturing process of the silicon connection layer 2 can be different from that of the FPGA bare chips, the silicon connection layer 2 in the application is an active silicon connection layer, a multi-layer cross-bare-chip connecting wire 6 is arranged in the active silicon connection layer, an active device is further arranged in the active silicon connection layer, and the active device is used for adjusting signal delay on a signal transmission path between the two FPGA bare chips, wherein:

referring to fig. 11, the active devices disposed in the silicon interconnect layer include buffers, each buffer includes an even number of inverters sequentially connected in series, for example, in fig. 11, each buffer includes two inverters, and the cross-die connection line 6 between the connection point terminals 4 of two FPGA dies passes through the Buffer (BUF). The inverters forming the buffer may be symmetrically arranged on the cross-die connection line 6 between the connection point terminals 4 of the two FPGA dies, for example, two inverters are taken as an example, and it is common practice to arrange one inverter at the input end of the signal transmission path and the other inverter at the output end of the signal transmission path; it is also possible to arrange one inverter at the 1/4 proximal input end of the signal transmission path and the other inverter at the 1/4 proximal output end of the signal transmission path.

The size (W/L) of the BUF controls the signal delay on the signal transmission path between the two FPGA dies, and each BUF can be designed to have multiple different sizes to realize different delay choices, that is, at least two BUFs with different delay sizes are arranged in the silicon connection layer 2, as shown in fig. 11, two BUFs with different sizes are arranged. The size of the BUF can be selected by closing the switch, that is, each buffer includes a plurality of buffer paths connected in parallel through the switch, wherein one buffer path is directly connected to the signal transmission path, and the other buffer paths are connected in parallel with the signal transmission path, and the paths are respectively provided with the switches, as shown in fig. 12, when the switch is closed, the buffer path where the switch is located is connected to the circuit, and when the number of the buffer paths connected to the whole buffer is different, the buffer has different time delay sizes, and the adjustment signal transmission path has different signal delays. The larger the number of buffer paths to be accessed, the stronger the driving capability of the buffer, and the lower the signal delay, and the switching of the on/off states of the switches in the respective buffer paths is realized by Metal selection technology (Metal operation). For example, in practical application, as shown in fig. 12, generally, a buffer is configured to include 4 buffer paths connected in parallel through switches, the 4 buffer paths are connected in parallel, and switches are disposed in 3 buffer paths, a part of the switches may be selected to be closed through Metal Option, and when the number of closed switches is respectively 1 to 4, the buffer correspondingly has a BUF1X delay, a BUF2X delay, a BUF3X delay, and a BUF4X delay, and the delays are sequentially reduced. A layout illustration of the Metal Option select buffer size is shown at 13. In addition, when the BUF is realized, the Schmitt trigger characteristic can be added, namely, a Schmitt trigger circuit is connected in series with the output end of the buffer, so that the noise interference can be reduced, and the quality of the cross-chip signal can be improved.

The active devices arranged in the silicon connection layer further include a first type flip-flop, the first type flip-flop is designed in a synchronous manner, the clock frequency of the first type flip-flop is a multiple of the system clock frequency, and a cross-die connection line 6 between connection point terminals 4 of the two FPGA dies also passes through the first type flip-flop, as shown in fig. 11. The design of the first type of trigger can improve the cross-chip application frequency and reduce the limitation of the cross-chip signal delay on the frequency, similar to the BUF, the first type of trigger can be connected to a cross-bare chip connecting line between the connection point leading-out ends of two FPGA bare chips through a change-over switch during the design, as shown in fig. 12, an implementation mode is shown, when a single-pole double-throw switch selects a cross-bare chip connecting line 6 channel, the first type of trigger is not connected to a signal transmission path between the two FPGA bare chips, when the single-pole double-throw switch selects a first type of trigger channel, the first type of trigger is connected to the signal transmission path between the two FPGA bare chips, and the Metal Option can be used for controlling the on-off state switching of the change-over switch so as to select whether the first type of trigger is inserted into the path.

In addition, the multi-die FPGA further comprises a second type of trigger, the second type of trigger is designed in an asynchronous mode and is used for clock domain crossing communication between two FPGA dies, the second type of trigger is added and is used for clock domain crossing communication between different FPGA dies in the FPGA to reduce metastable state, and the application introduces two implementation modes of the second type of trigger designed in an asynchronous mode:

1. the second type of flip-flop is arranged in the silicon connection layer 2, as shown in fig. 14, the second type of flip-flop includes a first D flip-flop D1 and a second D flip-flop D2, a D terminal of the first D flip-flop D1 is connected to one of the FPGA dies (die 1 in the figure) to obtain an enable signal EN, a Q terminal is connected to a D terminal of the second D flip-flop D2, and a Q terminal of the second D flip-flop D2 is connected to an active device in the silicon connection layer 2 so as to output the enable signal EN to control on/off of the active device, as shown in fig. 14, the Q terminal of the second D flip-flop D2 is connected to a buffer. The clock terminal CLK of the first D flip-flop D1 and the second D flip-flop D2 are connected to another FPGA die (in the figure, die 2) and acquire a clock signal.

2. The second type of trigger is respectively arranged inside the two FPGA bare chips, and the two FPGA bare chips carry out handshake signals interaction through the second type of trigger, as shown in fig. 15, when handshake signals are adopted, the same handshake signal can control the transmission of a plurality of BUFs, and the transmission quality of the cross-bare-chip bus is improved.

Except that the multi-bare-chip signal time delay can be balanced by the active silicon connection layer, the cross-bare-chip signal time delay can be balanced by the winding structure, and the method mainly comprises the following two aspects:

1. cross-die signal delay is balanced by the routing structure of the top layer metal lines 5 between the silicon stack connection points 3 and the connection point terminals 4 within the FPGA die. Referring to fig. 16, in the present application, the top metal line 5 in the RDL layer in the FPGA die may have a predetermined routing structure and the routing distance corresponds to the signal delay on the signal transmission path, and the longer the routing distance of the top metal line 5, the greater the time delay between the silicon stack connection point 3 and the connection point terminal 4, so that the cross-die signal delay can be balanced by adjusting the routing distance of the top metal line 5. At least two top metal lines 5 with different winding distances exist in the RDL layer, and the method comprises the following steps: each silicon stacking connection module LNK includes N rows and M columns of silicon stacking connection points 3 therein, as shown in fig. 16, each silicon stacking connection module LNK includes three types, i.e., a high delay silicon stacking connection point, a middle delay silicon stacking connection point, and a low delay silicon stacking connection point, respectively, and in the redistribution layer, the routing distance of the top layer metal line 5 connected to the high delay silicon stacking connection point, the routing distance of the top layer metal line 5 connected to the middle delay silicon stacking connection point, and the routing distance of the top layer metal line 5 connected to the low delay silicon stacking connection point are sequentially decreased, as shown in fig. 16, the high delay silicon stacking connection point forms a high delay area a, and the routing distance of the top layer metal line 5 connected thereto is the longest; the middle delay silicon stacking connection point forms a middle delay area B, and the routing distance of the top layer metal wire 5 connected with the middle delay silicon stacking connection point is the second order; the low-delay silicon stack connection point forms a low-delay region C, which connects the shortest routing distance of the top metal lines 5.

2. The cross-die signal delay is balanced by the routing structure of the cross-die connection line 6 in the silicon connection layer 2, and similarly, fig. 3, fig. 8 and fig. 10 all only show the connection relationship between the connection point terminals 4 of two FPGA dies implemented by the cross-die connection line 6, but do not show the routing manner of the cross-die connection line 6, as shown in fig. 16, in this application, the cross-die connection line 6 may also have a predetermined routing structure and the routing distance corresponds to the signal delay on the signal transmission path. The longer the distance of the windings of the cross-die wire 6, the greater the signal delay between the connection point outlets 4 of the two FPGA dies, so the cross-die signal delay can be balanced by adjusting the distance of the windings of the cross-die wire 6. As shown in fig. 16, taking the cross-die wires 6 with three different routing distances as an example, the routing distances of the cross-die wires 6 of the three routing structures from left to right in fig. 16 become shorter and the signal delays become smaller.

Therefore, in the present application, a signal transmission path is formed by a first top layer metal wire between a first silicon stacked connection point in any first FPGA die and a corresponding first connection point lead-out, a cross-die connection wire between the first connection point lead-out and a second connection point lead-out on any second FPGA die, and a second top layer metal wire between a second connection point lead-out on the second FPGA die and a corresponding second silicon stacked connection point. The signal delay of the signal transmission path corresponds to the total wiring distance of the signal transmission path, the total wiring distance is the sum of the winding distance of the first top-layer metal wire, the winding distance of the cross-die connecting wire and the winding distance of the second top-layer metal wire, and the longer the total wiring distance is, the higher the signal delay of the signal transmission path is. The Delay of the signal transmission path is T1a + T2a + T3a, where T1a is the signal Delay on the first top-level metal line, T2a is the signal Delay on the die-crossing line, and T3a is the signal Delay on the second top-level metal line, so to adjust the Delay of the signal transmission path, Delay _ path can be implemented by adjusting one or more of T1a, T2a, and T3a, and each signal Delay corresponds to a respective routing distance, so that the signal Delay can be adjusted by adjusting the routing distances of the first top-level metal line, the die-crossing line, and the second top-level metal line. By adjusting the total wiring distances of the two signal transmission paths to be equal, the signal delays of the two signal transmission paths can be made equal.

It should be noted that the multi-die FPGA of the present application employs the FPGA die with the built-in dedicated silicon stack connection point, and signal extraction and die interconnection are performed through the independent silicon stack connection point. But the multi-die FPGA is also compatible with a conventional FPGA die, and die signals of the conventional FPGA die are directly connected to the cross-die connecting line 6 in the silicon connecting layer 2 via the IOB to achieve die interconnection, but compared with a structure directly adopting IOB interconnection, the structure adopting silicon stacking connection point interconnection has the advantages of higher bandwidth, lower delay, lower power consumption and the like.

Referring to fig. 1 and 2, a silicon connection layer 2 is stacked on a substrate 1, specifically, micro-bumps are grown on a side of the silicon connection layer 2 away from the FPGA die, and the silicon connection layer 2 is connected to the substrate 1 through the micro-bumps. Silicon through holes 7 are further formed in the silicon connecting layer 2, and IOBs in the FPGA bare chip are connected to the substrate 1 through the silicon through holes 7 in the silicon connecting layer 2 so as to finally lead out signals.

The multi-die FPGA realizes the interconnection communication among the multiple FPGA dies, so that when a large-scale FGPA needs to be designed, the multi-die FPGA can be formed by cascading multiple smaller-scale FPGA dies, and the processing difficulty is greatly reduced. In addition, the multi-die FPGA can be further expanded according to usage requirements, that is, other dies are stacked on the silicon connection layer 2 in addition to the plurality of FPGA dies, and the arrangement of the other dies and the connection with the silicon connection layer are similar to the FPGA, which is not described in detail herein. The connection point leading-out end in the FPGA bare chip is connected with the corresponding connection point leading-out end in other bare chips through a cross bare chip connecting wire in the silicon connecting layer, so that the FPGA with more varieties and powerful functions can be realized, and the FPGA has the advantages of high speed, low power consumption and more connection channels. Wherein:

the at least one other die is a Processor chip including at least one of a Processor chip such as an ARM chip or a RISC-V chip;

and/or at least one other bare chip is a DSP chip;

and/or, at least one other die is an AI chip;

and/or, the at least one other bare chip is a memory chip, and the memory chip comprises at least one of SRAM, DRAM, ROM, FLASH, MRAM and RRAM;

and/or at least one other bare chip is a data conversion chip, and the data conversion chip comprises at least one of an analog-to-digital conversion chip and a digital-to-analog conversion chip;

and/or, at least one other die is a radio frequency chip;

and/or, at least one other die comprises an HBM, RAMBUS or NOC interface;

and/or, at least one other die includes a PCIE, Ethernet MAC, XUAI, SONET/SDH, or INTERLAKEN interface.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims

1. A multi-die FPGA utilizing an active silicon connection layer to balance delay is characterized in that the multi-die FPGA comprises a substrate, a silicon connection layer arranged on the substrate in a stacking mode and a plurality of FPGA dies arranged on the silicon connection layer in a stacking mode, wherein the FPGA dies are arranged on the silicon connection layer in a two-dimensional stacking mode, and the silicon connection layer covers all the FPGA dies;

each FPGA bare chip comprises a plurality of configurable function modules, interconnection resource modules distributed around each configurable function module and a connection point leading-out end, each configurable function module in the FPGA bare chip at least comprises a programmable logic unit, a silicon stacking connection module and an input/output port, each silicon stacking connection module comprises a plurality of silicon stacking connection points, each programmable logic unit in the FPGA bare chip is connected with the corresponding connection point leading-out end through the interconnection resource module and the corresponding silicon stacking connection point through a top layer metal wire in a rewiring layer;

the connection point leading-out terminal in each FPGA bare chip is connected with the corresponding connection point leading-out terminal in other FPGA bare chips through a cross bare chip connection line in the silicon connection layer, and an active device is distributed in the silicon connection layer and used for adjusting signal delay on a signal transmission path between the two FPGA bare chips; each FPGA die can be connected with any other FPGA die through a cross-die connecting line in the silicon connecting layer, the cross-die connecting line communicated with each FPGA die is arranged in the silicon connecting layer along a first direction and a second direction in a crossing mode, and the first direction and the second direction are perpendicular to each other in the horizontal direction; an input/output port in the FPGA bare chip is connected to the substrate through a silicon through hole on the silicon connecting layer;

active devices distributed in the silicon connection layer comprise buffers, each buffer comprises an even number of inverters which are sequentially connected in series, and a cross-die connecting line between connection point leading-out ends of the two FPGA dies penetrates through the buffers.

2. The multi-die FPGA of claim 1 wherein at least two buffers with different delay sizes are disposed in the silicon connection layer, the buffers with different delay sizes adjusting signal transmission paths to have different signal delays.

3. The multi-die FPGA as claimed in claim 1, wherein each buffer comprises a plurality of buffer paths connected in parallel through a switch, when the switch is closed, the buffer paths are connected to the circuit, when the number of the buffer paths is different, the buffers have different time delay sizes, the signal transmission paths are adjusted to have different signal delays, the switching of the on/off states of the switches in the respective buffer paths is realized by a metal selection technique when the number of the buffer paths is larger and the time delay of the buffers is smaller.

4. The multi-die FPGA of claim 3, wherein the buffer comprises 4 buffer paths connected in parallel through a switch, and when the number of the buffer paths controlled to be accessed through the metal selection technology is respectively 1-4, the buffer has BUF1X delay, BUF2X delay, BUF3X delay and BUF4X delay.

5. The multi-die FPGA of claim 1 wherein said buffer further comprises schmitt trigger circuits connected in series at outputs of an even number of inverters.

6. The multi-die FPGA of any one of claims 1-5, wherein the active devices disposed in the silicon connection layer further comprise a first type of flip-flop, the first type of flip-flop is designed in a synchronous manner, a cross-die connection line between connection point terminals of two FPGA dies is respectively connected to an input terminal and an output terminal of the first type of flip-flop through a switch, when the state of the switch is switched, the first type of flip-flop is connected or not connected to a signal transmission path between the two FPGA dies, the switching of the on-off state of the switch is realized by a metal selection technology, and the clock frequency of the first type of flip-flop is a multiple of the system clock frequency.

7. The multi-die FPGA of claim 1 further comprising a second type of flip-flop, said second type of flip-flop being of an asynchronous design and used for clock domain cross communication between two FPGA dies.

8. The multi-die FPGA of claim 7, wherein the second type of flip-flop is disposed in the silicon connection layer, the second type of flip-flop includes a first D flip-flop and a second D flip-flop, a D terminal of the first D flip-flop is connected to one of the FPGA dies to obtain an enable signal, a Q terminal of the first D flip-flop is connected to a D terminal of the second D flip-flop, a Q terminal of the second D flip-flop is connected to an active device output enable signal in the silicon connection layer to control on and off of the second D flip-flop, and clock terminals of the first D flip-flop and the second D flip-flop are both connected to another FPGA die and obtain a clock signal.

9. The multi-die FPGA of claim 7, wherein the second type of flip-flop is disposed inside two FPGA dies respectively, and then the two FPGA dies perform handshake signal interaction through the second type of flip-flop.

10. The multi-die FPGA of claim 1 wherein a first top level metal line between a first silicon stack connection point on any first FPGA die and a corresponding first connection point lead-out, a cross-die connection line between the first connection point lead-out and a second connection point lead-out on any second FPGA die, and a second top level metal line between a second connection point lead-out on the second FPGA die and a corresponding second silicon stack connection point form a signal transmission path; the signal delay of the signal transmission path corresponds to a total wiring distance of the signal transmission path, the total wiring distance is the sum of the winding distance of the first top-layer metal wire, the winding distance of the cross-die connecting wire and the winding distance of the second top-layer metal wire, the longer the total wiring distance is, the higher the signal delay of the signal transmission path is, and when the total wiring distances of the two signal transmission paths are adjusted to be equal, the signal delays of the two signal transmission paths are equal; the routing distances of the top layer metal lines and the cross-bare chip connecting lines are adjusted through different routing structures.

11. The multi-die FPGA of claim 1 wherein said silicon stack connection points are directly connected to interconnect switches in said interconnect resource module, and wherein said silicon stack connection points are fully or partially interconnected to said interconnect switches.

12. The multi-die FPGA of claim 1 wherein cross-die wires that communicate between individual FPGA dies are arranged hierarchically within said silicon connectivity layer.