CN111710663B - Multi-die silicon stacking interconnection structure FPGA - Google Patents

Abstract

The application discloses a multi-die silicon stacking interconnection structure FPGA, which relates to the technical field of FPGA and comprises a substrate, a silicon connection layer on the substrate and a plurality of FPGA dies which are stacked on the silicon connection layer in a two-dimensional stacking mode, wherein the dies are internally provided with special silicon stacking connection points for leading out signals and connected to connection point leading-out ends through RDL layers, the die signals are led out to the connection point leading-out ends through the silicon stacking connection points, and the connection point leading-out ends can be connected to other dies through cross-die connection lines in two directions in the silicon connection layer to realize two-dimensional interconnection communication between the dies; the cascade structure supports the realization of large-scale and large-area FPGA products by cascading a plurality of small-scale and small-area bare chips, reduces the processing difficulty, improves the production yield of chips and accelerates the design speed; meanwhile, various types of bare chips are flexibly integrated, so that FPGA products oriented to different applications can be quickly realized.

Description

Multi-die silicon stacking interconnection structure FPGA

Technical Field

The invention relates to the technical field of FPGA (field programmable gate array), in particular to a multi-die silicon stack interconnection structure FPGA.

Background

An FPGA (Field Programmable Gate Array) is a Programmable logic device of hardware, and is widely applied to prototype verification in integrated circuit design besides the fields of mobile communication, data center, etc., so as to effectively verify the correctness of circuit functions and accelerate the circuit design speed. The prototype verification needs to realize circuit design by using programmable logic resources inside the FPGA, the demand for the number of the programmable logic resources of the FPGA is continuously increased along with the continuous increase of the scale of the integrated circuit and the realization of complex functions, the number of the programmable resources of the FPGA becomes a larger bottleneck due to the continuous increase of the subsequent technical development and demand, and a larger challenge is provided for the development of the industry. The increase in the FPGA scale represents an increasing chip area, which leads to an increase in chip processing difficulty and a decrease in chip production yield.

Some patents have proposed a method for designing chip interconnects by using silicon-on-chip (SSI), for example, the patent with application number 2016800598883 proposes a stacked die interconnect without interposer, which uses a plurality of discrete interconnect dies to implement signal interconnects between two adjacent dies; another example is patent application No. 2017800501825, which proposes a separate interface for silicon stacked interconnect technology integration that uses an entire interposer as an interconnect carrier to achieve signal interconnection of two adjacent IC dies. However, the above two patents are limited by the defects of the chip itself and the structure design, and both can only interconnect two adjacent IC dies arranged side by side, and can only implement signal interconnection in a single direction, so that the structure is very limited in practical application, and the complex circuit requirements of the large-scale integrated circuit are difficult to meet.

Disclosure of Invention

The present invention provides a multi-die silicon stacked interconnect FPGA for solving the above problems and technical requirements, and the technical solution of the present invention is as follows:

a multi-die silicon stack interconnection structure FPGA comprises a substrate, a silicon connection layer arranged on the substrate in a stacking mode and a plurality of FPGA dies arranged on the silicon connection layer in a stacking mode, wherein the FPGA dies are arranged on the silicon connection layer in a two-dimensional stacking mode, and the silicon connection layer covers all the FPGA dies;

each FPGA bare chip comprises a plurality of configurable function modules, interconnection resource modules distributed around each configurable function module and a connection point leading-out end, each configurable function module in the FPGA bare chip at least comprises a programmable logic unit, a silicon stacking connection module and an input/output port, each silicon stacking connection module comprises a plurality of silicon stacking connection points, the programmable logic units in the FPGA bare chip are respectively connected with the silicon stacking connection points and the input/output ports through the interconnection resource modules, and the silicon stacking connection points in the FPGA bare chip are connected with the corresponding connection point leading-out ends through connection lines in a rewiring layer; the connection point leading-out end in each FPGA bare chip is connected with the corresponding connection point leading-out end in other FPGA bare chips through a cross bare chip connection wire in the silicon connection layer, and each FPGA bare chip is connected with any other FPGA bare chip through the cross bare chip connection wire in the silicon connection layer; the cross-die connecting lines which are communicated with the FPGA dies are arranged in the silicon connecting layer along a first direction and a second direction in a crossed mode, and the first direction and the second direction are vertical to each other in the horizontal direction; and the input/output port in the FPGA bare chip is connected to the substrate through the silicon through hole on the silicon connecting layer.

The further technical scheme is that the silicon stacking connection module is directly connected with an interconnection switch in the interconnection resource module, and the silicon stacking connection module and the interconnection switch are fully or partially interconnected.

The FPGA chip further comprises other function modules, wherein the other function modules comprise a DSP module and/or a BRAM module, the other function modules are respectively connected with the silicon stacking connection point and the input/output port through the interconnection resource module, the programmable logic units, the silicon stacking connection module and the other function modules are arranged to form a two-dimensional array, and the silicon stacking connection module is arranged in a row-column structure where the programmable logic units are located and in a row-column structure where the other function modules are located.

The further technical scheme is that the size of the silicon stacking connection module is smaller than that of other functional modules, a row and column structure where the other functional modules are located forms a vacant area at the silicon stacking connection module, and at least one of a capacitor, a test circuit, a noise reduction circuit and a monitoring circuit is arranged at the vacant area.

The further technical scheme is that the connection point leading-out ends in each FPGA bare chip are distributed according to a row-column structure along a first direction and a second direction, and a plurality of rows of connection point leading-out ends are distributed in each FPGA bare chip along the first direction and/or a plurality of columns of connection point leading-out ends are distributed along the second direction.

Its further technical scheme does, has laid a plurality of rows of tie point terminals along first direction in every FPGA bare chip, includes: a plurality of rows of connection point leading-out ends are uniformly distributed in each FPGA bare chip along the first direction at the same intervals; or, a plurality of rows of connection point terminals are randomly distributed in each FPGA bare chip along the first direction.

The further technical scheme is that the cross-die connecting lines which are communicated with the FPGA dies are arranged in a silicon connecting layer in a layered mode.

The input/output port in the FPGA bare chip is connected with the corresponding connection point leading-out terminal through a connection line in the rewiring layer.

The further technical scheme is that the plurality of FPGA bare chips are arranged on the silicon connecting layer according to the shape and the area of each FPGA bare chip.

The multi-die silicon stacked interconnection structure FPGA further comprises other dies, the other dies are stacked on the silicon connection layer, and connection point leading-out ends in the FPGA dies are connected with corresponding connection point leading-out ends in the other dies through cross-die connection lines in the silicon connection layer; wherein:

the at least one other die is a Processor chip including at least one of a Processor chip such as an ARM chip or a RISC-V chip;

and/or at least one other bare chip is a DSP chip;

and/or, at least one other die is an AI chip;

and/or, the at least one other bare chip is a memory chip, and the memory chip comprises at least one of SRAM, DRAM, ROM, FLASH, MRAM and RRAM;

and/or at least one other bare chip is a data conversion chip, and the data conversion chip comprises at least one of an analog-to-digital conversion chip and a digital-to-analog conversion chip;

and/or, at least one other die is a radio frequency chip;

and/or, at least one other die comprises an HBM, RAMBUS or NOC interface;

and/or, at least one other die includes a PCIE, Ethernet MAC, XUAI, SONET/SDH, or INTERLAKEN interface.

The beneficial technical effects of the invention are as follows:

1. the multi-die silicon stacked interconnection structure FPGA comprises a substrate, a silicon connection layer and a plurality of FPGA dies, wherein the silicon connection layer covers all the FPGA dies, multilayer cross-die connecting lines in two directions are arranged in the whole or partial area of the silicon connection layer according to circuit requirements, and therefore each FPGA die can be connected with any other FPGA die through the cross-die connecting line of the silicon connection layer, two-dimensional interconnection communication of the FPGA dies is achieved through the cross-die connecting lines arranged in the silicon connection layer along the two directions. The cascade structure supports the realization of large-scale and large-area FPGA chips by cascading a plurality of small-scale and small-area FPGA bare chips, reduces the processing difficulty, improves the production yield of the chips and accelerates the design speed.

2. Besides a conventional configurable function module, each FPGA bare chip also comprises a newly added configurable function module which is specially used for leading out signals of the bare chip, namely a silicon stacking connection module, a plurality of silicon stacking connection points are included in the silicon stacking connection module, and the FPGA bare chips carry out signal leading out and interconnection through the special silicon stacking connection points, so that the FPGA bare chip has the advantages of higher bandwidth, lower delay, lower power consumption and the like.

3. Various circuit structures can be arranged in a vacant area at the silicon stacking connection module inside each FPGA bare chip, so that the FPGA bare chip has better performance and stronger function.

4. The multi-die silicon stacked interconnection structure FPGA can also be provided with other dies of various types on a silicon connection layer, and the other dies can also realize two-dimensional interconnection communication with the FPGA dies through a cross-die connecting line arranged along two directions in the silicon connection layer, so that various dies of various types can be flexibly integrated, FPGA chips with rich varieties and powerful functions facing different applications can be quickly realized, and the market is occupied.

Drawings

FIG. 1 is a schematic cross-sectional view of a multi-die silicon stacked interconnect structure FPGA of the present application.

Fig. 2 is an enlarged view of a portion of the structure in fig. 1.

FIG. 3 is a top down two-dimensional schematic view of a multi-die silicon stacked interconnect structure FPGA of the present application.

Fig. 4 is a schematic diagram of an internal structure of a conventional FPGA.

FIG. 5 is a schematic diagram of an internal structure of a conventional FPGA adopting a Column-Based architecture.

FIG. 6 is a block diagram of a conventional FPGA adopting the Column-Based architecture.

Fig. 7 is a schematic block diagram of an FPGA die in the present application when the block structure shown in fig. 6 is adopted.

Fig. 8 is a schematic diagram of connections between a silicon stacked connection module and an interconnection resource module inside an FPGA die in the present application.

Fig. 9 is a schematic diagram of a connection point terminal on an FPGA die in the present application.

Fig. 10 is a two-dimensional schematic diagram of an interconnect structure formed between FPGA dies through connection point leadouts in the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application provides a multi-die silicon stack interconnection structure FPGA which is different from an existing FPGA, wherein FIG. 1 is a schematic cross-sectional view of a packaging structure of the FPGA, FIG. 2 is an enlarged view of a part of the structure in FIG. 1, and FIG. 3 is a corresponding schematic top view of FIG. 1. The FPGA comprises a substrate 1, a silicon connection layer 2 and a plurality of FPGA dies, which are stacked in sequence from bottom to top, for example, the structure shown in fig. 1 to 3 includes 6 FPGA dies, which are respectively represented by dies 1 to 6. In practical implementation, the FPGA further comprises a package housing for protecting the various components, packaged outside the substrate 1, the silicon connection layer 2 and the FPGA die, and further comprises pins for signal extraction, etc. connected to the substrate, which conventional structures are not shown in detail in fig. 1 and 2.

The FPGA of the application does not adopt a single FPGA bare chip structure, but comprises a plurality of FPGA bare chips, the plurality of FPGA bare chips are all stacked and arranged on the same silicon connection layer 2, and the plurality of FPGA bare chips are arranged on the silicon connection layer 2 in a two-dimensional stacking mode, namely are arranged along the horizontal direction and the vertical direction on the horizontal plane, as shown in FIG. 3. The plurality of FPGA bare chips can be reasonably arranged on the silicon connection layer 2, and are compactly arranged on the silicon connection layer 2 according to the shape and the area of each FPGA bare chip, so that the whole area of the whole FPGA is smaller, and the interconnection performance between the bare chips is better.

The silicon connection layer 2 is internally provided with cross-die connecting wires 3, the cross-die connecting wires 3 are distributed in the whole area or partial area of the silicon connection layer 2, and meanwhile, the silicon connection layer 2 covers all the FPGA dies, so each FPGA die can be connected to any other FPGA die through the cross-die connecting wires 3 according to circuit requirements, the circuit interconnection between the dies is almost not limited in space, and the flexibility is far better than the structures of the two patents mentioned in the background art. The inter-die connection lines 3 arranged inside the silicon connection layer 2 are arranged crosswise along a first direction and a second direction, and the first direction and the second direction are mutually vertical in the horizontal direction, namely, the first direction and the second direction are two directions of the horizontal direction and the vertical direction matched with the die arrangement structure. Therefore, each FPGA die can be simultaneously connected with other FPGA dies in the first direction and the second direction through the cross-die connection 3 in the two directions, so that a two-dimensional interconnection structure is formed among the plurality of FPGA dies, as shown in fig. 3, the die 1 can be interconnected with the die 2 through the cross-die connection 3 in the first direction, and can also be interconnected with the die 4 through the cross-die connection 3 in the second direction, and the same is true for the rest of the dies. In each direction, each FPGA die can be interconnected not only with other adjacent FPGA dies by the cross-die connection 3, but also with other spaced FPGA dies by the cross-die connection 3, for example, as shown in fig. 1 to 3, the die 1 can be interconnected not only with the adjacent die 2 by the cross-die connection 3, but also with the die 3 by the cross-die connection 3, or even with other spaced dies. In addition, the FPGA die can be connected to different rows of FPGA dies simultaneously through the cross-die connection 3 in two directions, for example, in fig. 3, the die 1 can be connected to the die 6 through the cross-die connection 3. It should be noted that fig. 3 shows the cross-die connection between the spaced FPGA dies as crossing the surface of the intermediate FPGA die, such as the cross-die connection between the die 1 and the die 3 crossing the surface of the die 2, but this is merely for convenience of illustration of the connection relationship, and practically all of the cross-die connection 3 is inside the silicon connection layer 2, as shown in fig. 1 and 2. The cross-die connecting lines 3 are arranged in the silicon connecting layer 2 in a layered and crossed mode, and the cross-die connecting lines 3 in the same direction and the cross-die connecting lines 3 in different directions can be arranged in a layered and crossed mode, so that the cross-die connecting lines 3 are not influenced with each other. It should be noted that although the present application claims such a two-dimensional stacking scheme, the technical solution is also applicable to a one-dimensional stacking scheme, but only there is a die-crossing wire 3 in one direction (lateral or longitudinal) inside the silicon connection layer 2. The manufacturing process of the silicon connection layer 2 can be different from that of an FPGA (field programmable gate array) die, and only the cross-die connection line 3 consisting of a plurality of layers of metal lines is arranged inside the silicon connection layer 2 without active devices, so that the manufacturing is easy and the cost is low.

The application can realize the arbitrary two-dimensional interconnection communication structure with higher flexibility, and besides the arrangement of the two-dimensional multilayer cross-bare chip connecting wire 3 in the silicon connecting layer 2, the application also adjusts and elaborately designs the internal structure of the FPGA bare chip and the connection mode of the FPGA bare chip and the silicon connecting layer 2. Next, the present application introduces specific connection structures and implementations between the FPGA die and the silicon connection layer 2:

the FPGA bare chip in the present application is different from a conventional FPGA bare chip, and first, the structure of the conventional FPGA bare chip is described as follows, please refer to the schematic structure shown in fig. 4, where the conventional FPGA bare chip is composed of configurable functional modules with multiple functions, and a common configurable functional module mainly includes a programmable logic unit (CLB or PLBs) and an input/output port (IOB), and sometimes includes some other functional modules, such as BRAM, DSP, PC, and the like. Each configurable functional module has an interconnection resource module (INT) with the same structure distributed around the configurable functional module, and horizontal or vertical connecting lines among the configurable functional modules are connected through the INT module. On the basis of the conventional structure, the FPGA bare chip in the present application includes, in addition to conventional configurable functional modules including CLBs, IOBs and other functional modules, a silicon stack connection module specially designed inside the bare chip according to the signal interconnection requirement between the bare chips, where the silicon stack connection module is an additional configurable functional module specially designed for leading out signals of the bare chip, and the silicon stack connection module includes a plurality of silicon stack connection points 4. The FPGA die in the application is formed by replacing some conventional configurable functional modules in the conventional FPGA die into a silicon stacking connection module. And the conventional configurable function module at any position can be replaced according to the signal interconnection requirement, for example, the conventional Column-Based FPGA architecture shown in fig. 5 is taken as an example, where each Column is the same module, for example, a CLB Column is a chip Column filled with CLB modules arranged from top to bottom. The height of each module is aligned with INT, the height of the CLB is equal to the INT height, the heights of other functional modules can be equal to a plurality of INT heights, the structure enables the whole FPGA to look like a two-dimensional array formed by INT, the heights of the modules in the array are consistent, the width of the same column is the same, but the widths of different columns can be different. Based on the two-dimensional array architecture, the silicon stacking connection module can be arranged in a row-column structure where the programmable logic unit is located, and can also be arranged in a row-column structure where other functional modules are located to obtain the FPGA bare chip in the application. The silicon stacking connection module is small in size, the height of the silicon stacking connection module is equal to that of the CLB and the INT, the width of the silicon stacking connection module is slightly smaller than that of the CLB, and the height and the width of other functional modules such as the DSP and the BRAM are larger than those of the CLB, so that a vacant area is formed when the silicon stacking connection module is placed at the other functional modules (the DSP and the BRAM) with the large size, and at least one conventional circuit structure of a capacitor, a test circuit, a noise reduction circuit and a monitoring circuit can be arranged at the vacant area to improve the circuit performance and enrich the functions.

The following examples are given: a schematic diagram of a conventional FPGA module using the architecture of fig. 5 is shown in fig. 6, which includes two other functional modules, namely, a DSP and a BRAM, in addition to a CLB, where the height of the CLB is equal to the height of INT, the height of the DSP is equal to 2 INT heights, and the height of the BRAM is equal to 4 INT heights. Based on the module structure shown in fig. 6, the CLB, the DSP, and the BRAM at any position may be replaced and set as the silicon stacking connection module to obtain the FPGA bare chip in the present application, for example, in fig. 7, the CLB column and the DSP column are both provided with the silicon stacking connection module LNK, and the CLB and one of the DSPs at the four corners are replaced and set as the silicon stacking connection module LNK. As can be seen from fig. 7, since the height of the DSP is equal to 2 INT heights, two silicon stack connection modules LNK are disposed in the height direction in the area where the DSP is originally arranged, and since the width of the DSP is greater than the width of the CLB, other conventional circuits, such as the TEST circuit TEST shown in fig. 7, may also be disposed in the vacant area in the width direction. Actual FPGA dies are also not necessarily limited to the Column-Based architecture illustrated in this application, and there is no fixed location for the silicon stack connection modules inside the FPGA dies.

Each silicon stacking connection module in the FPGA bare chip in the application also has an interconnection resource module distributed around the silicon stacking connection module, so that the winding structure of the FPGA bare chip in the application can be consistent with that of a conventional FPGA bare chip without changing. The horizontal or vertical connection lines between the silicon stacking connection module and each other configurable functional module are all connected via the INT module, and the silicon stacking connection module LNK is directly connected to the interconnection switch in the INT module corresponding to the silicon stacking connection module, and is a part of the interconnection line, please refer to fig. 8. The silicon stacking connection module LNK and the interconnection switch can be fully interconnected or partially interconnected according to the requirement of connectivity.

The FPGA die of the present application further includes connection point terminals 5 corresponding to the internal silicon stack connection points 4, the connection point terminals being generally arranged in a row-column configuration along a first direction and a second direction according to the stack interconnection requirements, and the schematic diagram can be seen with reference to fig. 9. The silicon stack connection points 4 within the FPGA die are connected to the corresponding connection point terminals by connection lines within the redistribution layer (RDL layer) as shown in figure 2. With this structure, the die signals of the FPGA die have been connected by the silicon stack connection points 4 to connection point terminals 5. The connection point leading-out end 5 can be connected to corresponding connection point leading-out ends in other FPGA bare chips through a cross bare chip connection wire 3 in the silicon connection layer 2, interconnection between the FPGA bare chips is achieved, specifically, a micro convex ball grows on the FPGA bare chips, the connection point leading-out end 5 is connected with the silicon connection layer 2 through the micro convex ball and is connected to other FPGA bare chips through a cross bare chip connection wire inside the silicon connection layer 2, the structure of the micro convex ball at the bottom of the FPGA bare chips can be seen in figure 2, and detailed marking is omitted in the application. Since the FPGA die is provided with the connection point terminals 5 along both the first direction and the second direction, the FPGA die can be connected to other FPGA dies in a two-dimensional direction by using the connection point terminals 5 in the two directions and combining the cross-die connection lines 3 in the two directions, please refer to the schematic diagram shown in fig. 10.

In addition, in order to achieve higher communication bandwidth, multiple rows/multiple columns of connection point leading-out terminals 5 can be arranged, that is, multiple rows of connection point leading-out terminals 5 are arranged in each FPGA die along the first direction, and/or multiple columns of connection point leading-out terminals 5 are arranged along the second direction, so that efficient two-dimensional cascade of multiple rows and multiple columns is achieved. When the plurality of rows/columns of the connection point leading-out terminals 5 are arranged along each direction, they may be arranged at regular intervals or at random.

It should be noted that the multi-die silicon stack interconnection structure FPGA of the present application employs the FPGA die with the built-in dedicated silicon stack connection point, and performs signal extraction and die interconnection through the independent silicon stack connection point. However, the multi-die silicon stacked interconnect structure FPGA is also compatible with a conventional FPGA die, and a die signal of the conventional FPGA die is directly connected to the inter-die connection line 3 in the silicon connection layer 2 via the IOB to achieve die interconnection, but the structure adopting silicon stacked connection point interconnection has advantages of higher bandwidth, lower delay, lower power consumption and the like compared with the structure directly adopting IOB interconnection.

Referring to fig. 1 and 2, a silicon connection layer 2 is stacked on a substrate 1, specifically, micro-bumps are grown on a side of the silicon connection layer 2 away from the FPGA die, and the silicon connection layer 2 is connected to the substrate 1 through the micro-bumps. Silicon through holes 6 are further formed in the silicon connecting layer 2, and IOBs in the FPGA bare chip are connected to the substrate 1 through the silicon through holes 6 in the silicon connecting layer 2 so as to finally lead out signals.

The multi-die silicon stacked interconnection structure FPGA realizes interconnection communication among multiple FPGA dies, so that when a large-scale FGPA needs to be designed, multiple smaller-scale FPGA dies can be cascaded to form the multi-die silicon stacked interconnection structure FPGA, and the processing difficulty is greatly reduced. In addition, the multi-die silicon stacked interconnect structure FPGA can be further expanded according to use requirements, that is, other dies are stacked on the silicon connection layer 2 in addition to the plurality of FPGA dies, and the arrangement mode of the other dies and the connection mode with the silicon connection layer are similar to the FPGA, which is not described in detail herein. The connection point leading-out end in the FPGA bare chip is connected with the corresponding connection point leading-out end in other bare chips through a cross bare chip connecting wire in the silicon connecting layer, so that the FPGA with more varieties and powerful functions can be realized, and the FPGA has the advantages of high speed, low power consumption and more connection channels. Wherein:

the at least one other die is a Processor chip including at least one of a Processor chip such as an ARM chip or a RISC-V chip;

and/or at least one other bare chip is a DSP chip;

and/or, at least one other die is an AI chip;

and/or, the at least one other bare chip is a memory chip, and the memory chip comprises at least one of SRAM, DRAM, ROM, FLASH, MRAM and RRAM;

and/or at least one other bare chip is a data conversion chip, and the data conversion chip comprises at least one of an analog-to-digital conversion chip and a digital-to-analog conversion chip;

and/or, at least one other die is a radio frequency chip;

and/or, at least one other die comprises an HBM, RAMBUS or NOC interface;

and/or, at least one other die includes a PCIE, Ethernet MAC, XUAI, SONET/SDH, or INTERLAKEN interface.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (10)

1. The multi-die silicon stack interconnection structure FPGA is characterized by comprising a substrate, a silicon connection layer stacked on the substrate and a plurality of FPGA dies stacked on the silicon connection layer, wherein the FPGA dies are arranged on the silicon connection layer in a two-dimensional stacking mode, and the silicon connection layer covers all the FPGA dies;

each FPGA bare chip comprises a plurality of configurable function modules, interconnection resource modules distributed around each configurable function module and a connection point leading-out end, each configurable function module in the FPGA bare chip at least comprises a programmable logic unit, a silicon stacking connection module and an input/output port, each silicon stacking connection module comprises a plurality of silicon stacking connection points, each programmable logic unit in the FPGA bare chip is respectively connected with the silicon stacking connection point and the input/output port through the interconnection resource modules, and the silicon stacking connection points in the FPGA bare chip are connected with the corresponding connection point leading-out ends through connection lines in a rewiring layer; the connection point leading-out terminal in each FPGA bare chip is connected with the corresponding connection point leading-out terminal in other FPGA bare chips through a cross bare chip connection wire in the silicon connection layer, and each FPGA bare chip is connected with any other FPGA bare chip through the cross bare chip connection wire in the silicon connection layer; cross-die connections connecting the FPGA dies are arranged crosswise along a first direction and a second direction in the silicon connection layer, and the first direction and the second direction are vertical to each other in the horizontal direction; and the input/output port in the FPGA bare chip is connected to the substrate through the silicon through hole on the silicon connecting layer.

2. The multi-die silicon stacked interconnect structure FPGA of claim 1, wherein the silicon stacked connection module is directly connected to the interconnect switch in the interconnect resource module, and the silicon stacked connection module is fully or partially interconnected with the interconnect switch.

3. The multi-die silicon stacked interconnect structure FPGA of claim 1, wherein the configurable functional modules in the FPGA die further include other functional modules, the other functional modules include DSP modules and/or BRAM modules, the other functional modules are respectively connected to the silicon stacked connection points and the input/output ports through the interconnect resource modules, the programmable logic units, the silicon stacked connection modules and the other functional modules are arranged to form a two-dimensional array, and the silicon stacked connection modules are disposed in a row-column structure where the programmable logic units are located and in a row-column structure where the other functional modules are located.

4. The multi-die silicon stacked interconnect structure FPGA of claim 3, wherein the size of the silicon stacked interconnect module is smaller than the size of the other functional modules, and the row-column structure of the other functional modules forms a vacant area at the silicon stacked interconnect module, and the vacant area is provided with at least one of a capacitor, a test circuit, a noise reduction circuit and a monitoring circuit.

5. The multi-die silicon stacked interconnect structure FPGA of any one of claims 1-4, wherein the contact pads terminals in each FPGA die are arranged in a row-column configuration along the first direction and the second direction, and wherein rows of contact pads terminals are arranged along the first direction and/or columns of contact pads terminals are arranged along the second direction in each FPGA die.

6. The multi-die silicon stacked interconnect structure FPGA of claim 5, wherein each FPGA die has rows of connection point terminals routed along the first direction, comprising:

a plurality of rows of connection point leading-out ends are uniformly distributed in each FPGA bare chip along the first direction at the same intervals; or, a plurality of rows of connection point terminals are randomly distributed in each FPGA bare chip along the first direction.

7. The multi-die silicon stacked interconnect structure FPGA of any one of claims 1-4, wherein cross-die wires connecting individual FPGA dies are arranged hierarchically within the silicon connection layer.

8. The multi-die silicon stacked interconnect structure FPGA of any of claims 1-4, wherein the input/output ports in the FPGA die are further connected to corresponding connection point terminals via connection lines in the rewiring layer.

9. The multi-die silicon stacked interconnect structure FPGA of any one of claims 1-4, wherein a plurality of FPGA dies are arranged on the silicon connection layer according to the shape and area of each FPGA die.

10. The multi-die silicon stacked interconnect structure FPGA of any one of claims 1-4, wherein the multi-die silicon stacked interconnect structure FPGA further comprises other dies stacked on the silicon connection layer, and connection point terminals in the FPGA die are connected to corresponding connection point terminals in the other dies by cross-die wires in the silicon connection layer; wherein:

at least one other die is a Processor chip including a Processor chip, the Processor chip being an ARM chip or a RISC-V chip;

and/or at least one other bare chip is a DSP chip;

and/or, at least one other die is an AI chip;

and/or, at least one other die is a memory chip comprising at least one of SRAM, DRAM, ROM, FLASH, MRAM, and RRAM;

and/or at least one other bare chip is a data conversion chip, and the data conversion chip comprises at least one of an analog-to-digital conversion chip and a digital-to-analog conversion chip;

and/or, at least one other die is a radio frequency chip;

and/or, at least one other die comprises an HBM, RAMBUS or NOC interface;

and/or, at least one other die includes a PCIE, Ethernet MAC, XUAI, SONET/SDH, or INTERLAKEN interface.

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