CN118215391A

CN118215391A - Package structure and method for manufacturing the same

Info

Publication number: CN118215391A
Application number: CN202410636337.5A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Bi Ren Technology Co ltd
Current assignee: Shanghai Bi Ren Technology Co ltd
Priority date: 2024-05-22
Filing date: 2024-05-22
Publication date: 2024-06-18

Abstract

The embodiment of the disclosure provides a packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: packaging a substrate; an interposer electrically connected to the package substrate and having a first side and a second side opposite to each other, wherein the package substrate is disposed on the second side of the interposer; and a main chip module and at least one passive device matrix disposed side by side on a first side of the interposer and electrically connected through the interposer, wherein each passive device matrix has a plurality of chip regions and dicing reserved regions, and includes a plurality of passive device chips disposed respectively in the plurality of chip regions, the plurality of passive device chips being disposed side by side in a direction parallel to a main surface of the package substrate and being spaced apart from each other by the dicing reserved regions, wherein the passive device matrix has a substrate continuously extending in the plurality of chip regions and the dicing reserved regions. The embodiment of the disclosure can reduce or avoid the warpage of the packaging structure, can improve the device performance of the packaging structure, and can be beneficial to reducing the overall size of the packaging structure.

Description

Package structure and method for manufacturing the same

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor packaging, and more particularly, to a packaging structure and a method of manufacturing the same.

Background

Chip-on-substrate (Chip on Wafer on Substrate, coWoS) packaging is an advanced semiconductor packaging technology that can achieve high-density wiring connection of multiple chips and high-rate transmission of data. In CoWoS packages, warpage problems may exist. How to reduce the warpage of the package structure is an important research topic in the packaging technology field.

Disclosure of Invention

There is provided, in accordance with at least one embodiment of the present disclosure, a package structure including: packaging a substrate; an interposer electrically connected to the package substrate and having a first side and a second side opposite to each other, wherein the package substrate is disposed on the second side of the interposer; and a main chip module and at least one passive device matrix disposed side by side on the first side of the interposer in a direction parallel to a main surface of the package substrate and electrically connected through the interposer, wherein each of the passive device matrices has a plurality of chip regions and dicing reserved regions, and includes a plurality of passive device chips respectively disposed on the plurality of chip regions, the plurality of passive device chips being disposed side by side in a direction parallel to the main surface of the package substrate and being spaced apart from each other by the dicing reserved regions, wherein the passive device matrix has a substrate continuously extending between the plurality of chip regions and the dicing reserved regions.

In a package structure provided according to at least one embodiment of the present disclosure, the passive device matrix includes: the substrate comprises a first substrate part positioned in the plurality of chip areas and a second substrate part positioned in the cutting reserved area; and a dielectric structure disposed on one side of the substrate, extending continuously between the plurality of chip regions and the dicing reserved region, and including a first dielectric portion in the plurality of chip regions and a second dielectric portion in the dicing reserved region; wherein each passive device chip includes one or more passive devices disposed in or on at least one of the first substrate portion and the first dielectric portion.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the dicing reserved area includes at least the second substrate portion and the second dielectric portion, and an orthographic projection of the one or more passive devices on the package substrate does not overlap with an orthographic projection of the dicing reserved area on the package substrate.

In the package structure provided according to at least one embodiment of the present disclosure, the dicing reserved area further includes an alignment mark disposed in or on at least one of the second substrate portion and the second dielectric portion.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the passive device matrix is a capacitor matrix, and each passive device chip includes one or more capacitors.

In a package structure provided in accordance with at least one embodiment of the present disclosure, each passive device chip includes a silicon capacitor.

In the package structure provided according to at least one embodiment of the present disclosure, a plurality of capacitors of the plurality of passive device chips are connected in parallel to each other through the interposer.

In the package structure provided according to at least one embodiment of the present disclosure, further includes: and the encapsulation layer is arranged on the first side of the medium layer, surrounds and encapsulates the main chip module and the passive device matrix, covers the side walls of the main chip module and the passive device matrix, and fills a gap between the main chip module and the passive device matrix.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the plurality of passive device chips includes an edge passive device chip adjacent to or near an edge of the encapsulation layer, the edge passive device chip having a first chip side and a second chip side opposite or adjacent to each other; the first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is encapsulated by the encapsulation layer, and the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix and is adjacent to the dicing reserved area and separated from the encapsulation layer.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the main chip module includes a first chip and a second chip, and the first chip and the second chip and the plurality of passive device chips in the passive device matrix are electrically connected to each other through the interposer.

In a package structure provided according to at least one embodiment of the present disclosure, the first chip includes a logic chip, and the second chip includes a memory chip.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the logic chip includes a system chip, and the memory chip includes a high bandwidth memory chip.

In accordance with at least one embodiment of the present disclosure, there is provided a package structure wherein the passive device matrix and the main chip module have sidewalls aligned in a direction parallel to a main surface of the package substrate from a plan view.

In the package structure provided according to at least one embodiment of the present disclosure, the at least one passive device matrix includes a plurality of passive device matrices, and the plurality of passive device matrices are disposed on the same side or different sides of the main chip module in a direction parallel to the main surface of the package substrate.

At least one embodiment of the present disclosure provides a method for manufacturing a package structure, including: providing a main chip module and a passive device matrix; providing an interposer, arranging the main chip module and the passive device matrix side by side on a first side of the interposer and electrically connecting with the interposer; the interposer is electrically connected to a package substrate, and the package substrate is disposed on a second side of the interposer, the second side being opposite to the first side, wherein the passive device matrix has a plurality of chip regions and dicing reserved regions, and includes a plurality of passive device chips respectively disposed in the plurality of chip regions, the plurality of passive device chips are disposed side by side in a direction parallel to a main surface of the package substrate and are spaced apart from each other by the dicing reserved regions, and the passive device matrix has a substrate continuously extending in the plurality of chip regions and the dicing reserved regions.

In a method for manufacturing a package structure provided according to at least one embodiment of the present disclosure, providing the passive device matrix includes: providing a passive device wafer having a plurality of die regions and a dicing region, each die region having one passive device die disposed therein, the dicing region being located between adjacent die regions and spacing adjacent passive device dies, wherein the passive device wafer comprises a matrix region comprising an initial passive device matrix located therein, the initial passive device matrix comprising a plurality of passive device dies arranged in an n x m array and a first dicing region located between the plurality of passive device dies, the dicing region further comprising a second dicing region located around the matrix region; and performing a wafer dicing process on the passive device wafer along a dicing path extending at least partially along the second dicing area to separate the initial passive device matrix from other passive device chips in the passive device wafer and form the passive device matrix, wherein the first dicing area remains in the passive device matrix and forms at least part of the dicing remains.

In a method for manufacturing a package structure according to at least one embodiment of the present disclosure, disposing the main chip module and the passive device matrix side by side on the first side of the interposer and electrically connecting with the interposer includes: a main chip bonding region bonding the main chip module to a chip bonding region of the interposer; calculating the spare area of the chip bonding area except the main chip bonding area; calculating the matrix area of the required passive device matrix according to the spare area, so that the matrix area is smaller than or equal to the spare area; calculating values of n and m of the n×m array based on the matrix area, and determining a position of the matrix area in the passive device wafer; performing the wafer dicing process and matching the size of the formed passive device matrix to the size of the spare area; and bonding the matrix of passive devices to the free area of the interposer.

In the manufacturing method of the packaging structure provided by at least one embodiment of the present disclosure, n is greater than or equal to 1, m is greater than or equal to 1, and n+m is greater than 2.

According to the package structure and the manufacturing method thereof provided by at least one embodiment of the present disclosure, warpage of the package structure may be reduced or avoided, device performance of the package structure may be improved, and an overall size of the package structure may be advantageously reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1 illustrates a schematic plan view of a package structure according to some embodiments of the present disclosure.

Fig. 2 illustrates a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

Fig. 3 illustrates a schematic plan view of a passive device matrix in a package structure according to some embodiments of the present disclosure.

Fig. 4 illustrates a schematic cross-sectional view of a passive device matrix in a package structure according to some embodiments of the present disclosure.

Fig. 5 illustrates a schematic plan view of a passive device wafer, according to some embodiments of the present disclosure.

Fig. 6 shows a schematic process flow diagram in a method of manufacturing a package structure according to some embodiments of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Generally, coWoS packages include chips, interposers, and package substrates. The interposer is located between the plurality of chips and the package substrate, provides interconnection between the plurality of chips, and connects the plurality of chips to the package substrate. CoWoS packages can be divided into three types based on the type of interposer: coWoS-S packages using a silicon substrate as an interposer, coWoS-R packages using an interposer including a rerouting structure, coWoS-L packages using a combination of bridge chips and a rerouting structure as an interposer.

In CoWoS-R or CoWoS-L packages, the interposer includes an organic dielectric layer and a rerouting structure embedded in the organic dielectric layer for making electrical connections between the plurality of chips and the package substrate; coWoS-L package also includes a bridge chip embedded in the organic dielectric layer, and the bridge chip is also used to provide electrical connections between the plurality of chips. In such CoWoS packages, because the interposer has an organic dielectric layer, such an interposer (i.e., including an organic dielectric layer and a rerouting structure) is also referred to as an organic interposer.

In CoWoS packages, the dimensions of the multiple chips on the interposer may not be perfectly matched, for example, there may be some free areas in the chip bonding area of the interposer that are detrimental to stress balancing, and thus may lead to warpage of the package structure. The dummy chip may be disposed in the free areas, and may serve to reduce package warpage, but the dummy chip has substantially no other electrical function except for filling the free areas.

In CoWoS packages, passive devices are also typically included that are electrically connected to the chip on the interposer to provide corresponding electrical performance. For example, the passive device may be or include a capacitor and may be used to reduce power supply noise of the package structure. In CoWoS-S packages, the interposer using the silicon substrate may have passive devices embedded therein, but the space for embedded passive devices is limited, for example, when the passive devices are capacitors, the capacity of the capacitors embedded in the silicon substrate interposer may be limited, so that its ability to reduce power supply noise is also limited. In CoWoS-R packages or CoWoS-L packages, in general, passive devices such as capacitors may not be embedded in an interposer, or passive devices such as capacitors may be embedded in an interposer of such a package, which is difficult and costly to implement.

The passive device may be mounted on the package substrate, for example, on a side of the package substrate near the interposer, or on a side of the package substrate remote from the interposer and provided with conductive terminals. The passive device installed on the packaging substrate needs to be electrically connected to the chip positioned on the interposer through the packaging substrate and the interposer, and the connection path between the passive device and the chip is far, so that the passive device can not provide corresponding electrical performance better; for example, when the passive device is a filter capacitor, a far connecting path may make the filtering effect of the capacitor limited, and thus the power noise cannot be reduced well. In addition, the passive device is mounted on the package substrate (for example, on a side thereof close to the interposer) to occupy an additional area of the package substrate, resulting in a larger overall size of the package structure; if the passive device is mounted on the side of the package substrate remote from the interposer, then a portion of the conductive terminal area is sacrificed to provide the passive device, which may have an adverse effect on the larger power chip.

In view of the warpage of the package structure and the above-described problems, embodiments of the present disclosure provide a package structure and a method of manufacturing the same, which can reduce or avoid the warpage of the package structure, can improve the device performance of the package structure, and can be advantageous to reduce the overall size of the package structure.

For example, embodiments of the present disclosure provide a package structure including a package substrate, an interposer, a main chip module, and at least one passive device matrix, and a method of manufacturing the same; the interposer is electrically connected with the packaging substrate and is provided with a first side and a second side which are opposite to each other, wherein the packaging substrate is arranged on the second side of the interposer; the main chip module and at least one passive device matrix are arranged side by side on a first side of the interposer and are electrically connected through the interposer, wherein each passive device matrix has a plurality of chip regions and dicing reserved regions, and comprises a plurality of passive device chips respectively arranged on the plurality of chip regions, the plurality of passive device chips are arranged side by side in a direction parallel to a main surface of the package substrate and are spaced apart from each other by the dicing reserved regions, wherein the passive device matrix has a substrate continuously extending between the plurality of chip regions and the dicing reserved regions.

In the embodiments of the present disclosure, by disposing the main chip module and the passive device matrix side-by-side on the first side of the interposer, it may be advantageous to balance the stress of the package structure, thereby reducing or avoiding warpage of the package structure. Compared with a passive device arranged on a packaging substrate, the passive device matrix and the main chip module are closer in distance, and the connecting path between the passive device matrix and the main chip module is shortened, so that the passive device matrix can better provide corresponding electrical performance; in addition, compared with the passive device chips which are independent of each other and are respectively and independently arranged on the intermediate layer, the passive device chips of the passive device matrix of the embodiment of the disclosure are arranged on the intermediate layer in a matrix form, so that the space occupied by the passive device chips can be reduced, the integration level of the passive device chips is improved, the warping of the packaging structure can be reduced more advantageously, and the manufacturing process can be simplified. On the other hand, the passive device matrix is arranged on the interposer without occupying the area of the package substrate additionally, which is beneficial to reducing the overall size of the package structure, and without sacrificing the area of the package substrate, which is far away from the interposer, for arranging the conductive terminals, so that the side of the package substrate, which is far away from the interposer, can be used for arranging a sufficient number of conductive terminals to provide electrical connection between the package structure and an external component (such as a power supply terminal).

In addition, compared with the mode of arranging the dummy chip on the intermediate layer to reduce warpage, the warpage can be reduced or avoided by arranging the passive device matrix, and the passive device matrix can also provide corresponding electrical performance; that is, the function of reducing warpage of the dummy chip and the function of the passive device are integrated together, which can be advantageous in reducing the package size and the package cost.

Fig. 1 illustrates a schematic plan view of a package structure according to some embodiments of the present disclosure, and fig. 2 illustrates a schematic cross-sectional view of the package structure taken along line I-I' of fig. 1 according to some embodiments of the present disclosure.

Referring to fig. 1 and 2, in some embodiments, a package structure 500 includes a main chip module 110, at least one passive device matrix 120, an interposer 210, and a package substrate 300. The main chip module 110 and the at least one passive device matrix 120 are disposed side by side on the first side S1 of the interposer 210 and electrically connected to the interposer 210. The package substrate 300 is disposed on the second side S2 of the interposer 210 and electrically connected to the interposer 210; the first side S1 and the second side S2 of the interposer 210 are opposite to each other, for example, in a direction perpendicular to the main surface of the package substrate 300. Herein, the plurality of members being disposed "side by side" means that the plurality of members are disposed side by side in a direction parallel to the main surface of the package substrate (e.g., a horizontal direction of fig. 2), that is, the plurality of members overlap in a direction parallel to the main surface of the package substrate, and may include a case where the plurality of members are aligned or not aligned in a direction parallel to the main surface of the package substrate. The main surface of the package substrate 300 is, for example, a surface on a side thereof close to or away from the interposer.

The main chip module 110 and the passive device matrix 120 are electrically connected through the interposer 210, including the case where one or more chips in the main chip module 110 and one or more passive device matrices 120 are electrically connected to each other only through the interposer 210 and corresponding conductive connectors, and also including the case where one or more chips in the main chip module 110 and one or more passive device matrices 120 are electrically connected to each other through the interposer 210 and the package substrate 300 and corresponding conductive connectors.

Referring to fig. 2, in some embodiments, each of the passive device matrices 120 has a plurality of chip regions 101 and a dicing reserved region 102, and includes a plurality of passive device chips 120a respectively disposed at the plurality of chip regions 101, the plurality of passive device chips 120a are spaced apart from each other by the dicing reserved region 102, and the passive device matrix 120 has a substrate continuously extending at the plurality of chip regions 101 and the dicing reserved region 102.

Fig. 3 illustrates a schematic enlarged plan view of a passive device matrix 120 and a schematic enlarged view of a passive device chip in the passive device matrix, according to some embodiments of the present disclosure; fig. 4 illustrates a schematic cross-sectional view taken along line A-A of fig. 3, according to some embodiments of the present disclosure.

Referring to fig. 1-4, in some embodiments, the plurality of chip regions 101 of the passive device matrix 120 may be disposed side-by-side in a direction parallel to the major surface of the package substrate, e.g., may be arranged in an array comprising one or more rows and/or one or more columns along the first direction D1, the second direction D2; a dicing reserved area 102 is located around each chip area 101 and separates adjacent chip areas 101. Each chip region 101 corresponds to one passive device chip 120a, i.e., the passive device matrix 120 includes a plurality of passive device chips 120a, the plurality of passive device chips 120a being disposed side by side (e.g., arranged in an array) and spaced apart from each other by dicing the reserved areas 102.

For example, the plurality of passive device chips 120a may have substantially the same size; the plurality of passive device chips 120a located in the same row may be substantially aligned with each other in the first direction D1, for example, have sidewalls aligned with each other in the first direction D1; the plurality of passive device chips 120a located in the same column may be substantially aligned with each other in the second direction D2, for example, having sidewalls aligned with each other in the second direction D2.

For example, the cut-and-hold region 102 may be in a grid shape; for example, the cut-and-hold region 102 may have a first sub-region 102a extending in the first direction D1 and a second sub-region 102b extending in the second direction D2. For example, the plurality of first sub-regions 102a extend in the first direction D1 in parallel with each other and are arranged in the second direction D2; the plurality of second sub-areas 102b extend in the second direction D2 in parallel with each other and are arranged in the first direction D1; the plurality of first sub-regions 102a and the plurality of second sub-regions 102b intersect each other and define a plurality of chip regions 101. Each chip region 101 may be surrounded by a dicing reserved region 102.

Referring to fig. 3 and 4, in some embodiments, the passive device matrix 120 includes a substrate 100, a dielectric structure 105 disposed on one side of the substrate 100, and a plurality of passive devices 106. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, and the substrate may alternatively or additionally include other suitable semiconductor materials, such as germanium and the like. For example, the material of the dielectric structure 105 may include a silicon-containing material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, combinations thereof, or the like, and may be a single-layer structure or a multi-layer structure, such as a multi-layer structure including a plurality of dielectric layers. A plurality of passive devices 106 are disposed in the chip region 101, and at least a portion of the passive devices 106 may be embedded in at least one of the substrate 100 and the dielectric structure 105.

For example, the substrate 100 extends continuously in the plurality of chip regions 101 and the dicing reserved region 102, and includes a first substrate portion 100a located in the plurality of chip regions 101 and a second substrate portion 100b located in the dicing reserved region 102. The plurality of first substrate portions 100a and the second substrate portions 100b are in contact with and continuous with each other and have the same material. That is, the substrate 100 including the plurality of first and second substrate portions 100a and 100b is a continuous substrate integrally formed, and no other material layer may be interposed between the first and second substrate portions without an interface (interface) therebetween. It should be understood that the boundaries between the chip regions and the dicing reserved regions are shown in dashed lines for ease of illustration only and do not represent interfaces between the chip regions and the dicing reserved regions.

For example, the dielectric structure 105 extends continuously in the plurality of chip regions 101 and the dicing reserved region 102, and includes a first dielectric portion 105a located in the plurality of chip regions 101 and a second dielectric portion 105b located in the dicing reserved region 102. The plurality of first dielectric portions 105a and the second dielectric portion 105b are in contact with each other and continuous, and have the same material. It is understood that the continuous extension of the dielectric structure 105 in the chip region and the dicing reserved region means that one or more dielectric layers in the dielectric structure 105 each extend continuously in these regions, and that portions of the plurality of first dielectric portions and second dielectric portions located in the respective dielectric layers are in contact with each other and continuous without an interface therebetween.

That is, the plurality of passive device chips 120a located in the plurality of chip regions 101 and the dicing reserved area 102 share the same substrate 100, and share the same dielectric structure 105. In some embodiments. Each passive device chip 120a includes one or more passive devices 106 disposed in or on at least one of the first substrate portion 100a and the first dielectric portion 105a of the respective chip region 101. It should be understood that the number, location, structure, etc. of passive devices of each chip region 101 shown in the figures are illustrative, and the disclosure is not limited thereto.

In some embodiments, the dicing reserved area 102 includes at least a second substrate portion 100b and a second dielectric portion 105b. One or more passive devices 106 of the plurality of passive device chips 120a may not extend into the dicing reserved area 102. The orthographic projection of one or more passive devices 106 of passive device chip 120a onto a reference plane extending in a direction parallel to the major surface of the substrate is offset from the orthographic projection of dicing retention 102 onto the reference plane, such as the major surface of package substrate 300 shown in fig. 2. In this context, staggering of the orthographic projections of a plurality of members on the same reference plane means that the orthographic projections of the plurality of members do not overlap, and includes the case where the orthographic projections of the plurality of members are spaced apart from one another but do not overlap, as well as the case where the orthographic projections of the plurality of members are adjacent to one another but do not overlap.

In some embodiments, the dicing reserved area 102 is also provided with an alignment mark (ALIGN MARK), which may be provided in or on at least one of the second substrate portion 100b and the second dielectric portion 105 b. For example, the dicing reserved area 102 has an alignment mark 103 provided on the second dielectric portion 105 b. It should be understood that the number, shape, and position of the alignment marks 103 are merely illustrative, and the disclosure is not limited thereto, and the alignment marks can be designed according to actual product requirements.

In some embodiments, the passive device matrix 120 is an integrated passive device matrix, and the passive device chips therein include capacitors therein, or may also include other types of passive devices. For example, the passive device matrix 120 is a capacitive matrix and each passive device chip includes one or more capacitances, which may be or include, for example, silicon capacitances. For example, the passive device 106 is a capacitor, such as any suitable type of capacitor, such as a metal-insulator-metal (MIM) capacitor, a deep trench capacitor (DEEP TRENCH capacitor, DTC), or the like. Fig. 4 schematically illustrates an electrode plate embedded in a dielectric structure of a capacitor, but the capacitor structure of the embodiment of the disclosure is not limited thereto.

Referring to fig. 2 to 4, the passive device matrix 120 further includes a plurality of second conductive bumps 108 disposed on the plurality of chip regions 101; the second conductive bumps 108 are electrically connected to the passive devices 106 of the passive device chip 120a and serve as external connection points for the passive device chip 120a, for example for electrical connection between the passive device chip 120a and an interposer. For example, a plurality of second conductive bumps 108 electrically connected to respective electrode plates of one or more capacitors may be provided in each passive device chip 120 a. The second conductive bump 108 may be a single-layer or multi-layer structure, and may include a metallic material such as titanium, copper, nickel, tin, silver, or an alloy thereof, or a combination thereof. For example, in some examples, the second conductive bump 108 may be a multi-layer structure and include a first metal layer, a second metal layer, and a solder layer stacked in sequence over the substrate; for example, the first metal layer may be or include a titanium copper (TiCu) layer, the second metal layer may be or include a nickel layer, and the solder layer may include tin silver (SnAg), but the disclosure is not limited thereto. The type, size (e.g., width, area, spacing) and the like of the plurality of second conductive bumps 108 may be set and adjusted according to product requirements.

In some embodiments, where the passive device matrix 120 is a capacitive matrix, the plurality of capacitances of the plurality of passive device chips 120a in the passive device matrix 120 may be parallel to each other, e.g., may be parallel to each other through an interposer; in the case where the same passive device chip 120a includes a plurality of capacitances, the plurality of capacitances may also be connected in parallel with each other. When a plurality of passive device matrices 120 are provided in the package structure, a plurality of capacitors of the plurality of passive device matrices 120 may also be connected in parallel with each other. The capacitors are connected in parallel, so that the overall capacitance of the passive device matrix can be increased, capacitance resistance and impedance in a circuit of the packaging structure can be reduced, and power supply noise of the packaging structure can be reduced.

Referring back to fig. 1 and 2, in some embodiments, the package structure 500 further includes an encapsulation layer 180 disposed on the first side S1 of the interposer 210, i.e., the side of the interposer 210 away from the package substrate 300, and surrounding the encapsulated host chip module 110 and the passive device matrix 120. For example, the encapsulation layer 180 covers and contacts the sidewalls of the main chip module 110, the sidewalls of the passive device matrix 120, and fills the gap between the main chip module 110 and the passive device matrix 120. In some embodiments, the encapsulation layer 180 may also cover the surfaces of the main chip module 110 and the passive device matrix 120 on the side away from the interposer 210, wherein the surfaces of the main chip module 110 and the passive device matrix 120 on the side away from the interposer 210 (i.e., the upper surface shown in fig. 2) may be substantially flush in a direction parallel to the major surfaces of the package substrate. In alternative embodiments, the surface of the encapsulation layer 180 on the side away from the interposer 210, the surface of the main chip module 110 on the side away from the interposer 210, and the surface of the passive device matrix 120 on the side away from the interposer 210 may be substantially flush in a direction parallel to the major surface of the package substrate; that is, the surfaces of the main chip module 110 and the passive device matrix 120 on the side away from the interposer 210 may be exposed without being covered by the encapsulation layer 180.

Referring to fig. 1-3, in some embodiments, an edge passive device chip may be included in the plurality of passive device chips 120a of the passive device matrix 120, which is located at an edge of the passive device matrix 120, such as may be adjacent to the main chip module 110 or near an edge of the encapsulation layer 180. For example, the passive device matrix 120 is arranged in an array of n×m (i.e., n rows and m columns, where n≡1, m≡1, and m+n > 2), and the passive device chips 120a located in the 1 st row, n-th row, 1 st column, and m-th column are edge passive device chips. That is, the edge passive device chip is an outermost passive device chip among the plurality of passive device chips of the passive device matrix; the edges of the matrix of passive devices include the sidewalls of the matrix of passive devices and a partial region adjacent to the sidewalls thereof.

For example, one side of the edge passive device chip may be adjacent to (e.g., facing) the main chip module or near the edge of the encapsulation layer 180 and encapsulated by the encapsulation layer 180, and the other side of the edge passive device chip is adjacent to the other passive device chips, adjacent to the dicing reserved area 102, and separated from the encapsulation layer 180.

For example, an edge passive device chip has a first chip side and a second chip side opposite or adjacent to each other; the first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is encapsulated by the encapsulation layer; the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix and is adjacent to the dicing reserved area and separated from the encapsulation layer.

For example, in the example of the passive device matrix 120 shown in fig. 3 arranged in a 5×8 (i.e., 5 rows and 8 columns) array, the passive device chips 120a located in the 1 st row, 5 th row, 1 st column, and 8 th column are edge passive device chips, in conjunction with fig. 1 and 3. For example, at least one side of the edge passive device chip is facing the main chip module or near the encapsulation layer edge, and at least another side of the edge passive device chip is facing the other passive device chips and abuts the dicing retention 102.

For example, the edge passive device chip may have a first chip side a1 and a second chip side a2 adjacent to or opposite to each other in a direction parallel to the major surface of the package substrate (e.g., the first direction D1 or the second direction D2), the first chip side a1 of the edge passive device chip facing the main chip module or an edge near the encapsulation layer and being encapsulated by the encapsulation layer; while the second chip side a2 of the edge passive device chip faces the other passive device chips and is adjacent to the dicing reserved area 102 and separated from the encapsulation layer. The dicing reserved area 102 located at the edge passive device chip second chip side a2 is located between the edge passive device chip and the adjacent passive device chip and is separated from the encapsulation layer.

In some embodiments, the first chip side a1 of the edge passive device chip may also be provided with a dicing reserved area 102, or the first chip side a1 of the edge passive device chip may be directly exposed at the side wall of the passive device matrix, while the side may not be provided with a dicing reserved area. The encapsulation of the first chip side a1 of the edge passive device chip by the encapsulation layer may include that a surface of a portion of the edge cut-and-remain region located at the first chip side a1 of the edge passive device chip is covered by and in contact with the encapsulation layer, or that a side surface of the first chip side a1 of the edge passive device chip is covered by and in contact with the encapsulation layer.

With continued reference to fig. 1 and 2, in some embodiments, the main chip module 110 includes one or more chips, which may each be a system on chip (SoC), a Digital Signal Processor (DSP) chip, a graphics processor (graphic processing unit, GPU), an Application SPECIFIC INTEGRATED Circuit (ASIC) chip, a memory chip, or the like. For example, the main chip module 110 includes a plurality of chips, and the plurality of chips may include the same type or different types of chips therein. The plurality of chips are disposed side by side on the interposer and may be electrically connected to each other through the interposer or through the interposer and the package substrate.

For example, the main chip module 110 includes one or more first chips 110a and one or more second chips 110b, 110c, 110d, 110e; the one or more first chips and the one or more second chips are electrically connected to each other through the interposer 210 or through the interposer 210 and the package substrate 300. For example, the one or more first chips 110a may include logic chips, which may include, for example, a system chip; one or more of the second chips 110b-110e may comprise a memory chip, which may comprise, for example, a high bandwidth memory (high bandwidth memory, HBM) chip.

For example, each chip in the main chip module may include a substrate, a device layer, and conductive bumps; the substrate may be or include a semiconductor substrate such as a silicon substrate; the device layer is disposed on one side of the substrate and may include active devices (e.g., transistors), passive devices (e.g., capacitors, inductors, etc.), or combinations thereof, and an interconnect structure through which the devices may be connected; the conductive bump is positioned on one side of the device layer away from the substrate and can be electrically connected to various devices on the substrate through the interconnection structure; the conductive bumps may serve as external connection points for the chip. The side of the chip with the conductive bumps or near the device layer may be referred to as the front or active side of the chip and the side of the chip where the substrate is located (i.e., the side opposite the front side) may be referred to as the back side. For example, each chip in the main chip module may be flip-chip mounted on the interposer 210 such that its front side faces the interposer, and may be electrically connected to the interposer 210 through conductive connections such as conductive bumps.

Referring to fig. 1, in some embodiments, interposer 210 has a die bonding region BR for bonding host chip module 110 and passive device matrix 120. For example, the die bonding region BR may be centrally disposed in the interposer 210, i.e., the center of the die bonding region BR may coincide with the center of the interposer 210 in plan view, the die bonding region BR may be of a symmetrical structure about a center line extending through the center, and the interposer 210 may be of a symmetrical structure about the same center line.

The die bonding region BR has a first bonding region R1 and a second bonding region R2, the first bonding region R1 is used for bonding one or more dies in the main die module 110, and may be also referred to as a main die bonding region; the second bonding region R2 is used to bond the matrix of passive devices 120 and may also be referred to as a passive device bonding region. In the die bonding region BR, there may be one or more second bonding regions R2; in the case of having a plurality of second bonding regions R2, the plurality of second bonding regions R2 may be located on the same side or different sides of the first bonding region R1 in a direction parallel to the main surface of the package substrate. For example, all chips in the main chip module 110 are disposed in the first bonding region R1, and each of the second bonding regions R2 may be correspondingly provided with one passive device matrix 120; that is, the passive device matrix 120 may be disposed in one-to-one correspondence with the second bonding regions R2. In the case of having a plurality of passive device matrices 120, the plurality of passive device matrices 120 may be disposed on the same side or different sides of the main chip module 110 in a direction parallel to the main surface of the package substrate.

In some embodiments, the plurality of chips in the main chip module 110 may be substantially uniformly distributed in the first bonding region R1. In some examples, the plurality of chips in the main chip module 110 may have different shapes or sizes, etc., such that the first bonding region R1 may have an irregular shape. The second bonding region R2 is a free region except the first bonding region R1 in the die bonding region BR, and the passive device matrix 120 is disposed in the second bonding region R2 to fill the free region of the die bonding region BR; for example, the die bonding region BR, which is formed by the second bonding region R2 and the first bonding region R1 together, may have a substantially regular-shaped profile and may, for example, be substantially symmetrical in shape.

For example, in the example shown in fig. 1, the plurality of second bonding regions R2 are respectively located at corners of the first bonding regions R1, near edges of the interposer, the first chip and the plurality of second chips of the main chip module 110 are bonded to the first bonding regions R1 of the interposer 210, and the plurality of passive device matrices 120 are respectively bonded to the plurality of second bonding regions R2 of the interposer 210. The plurality of passive device matrices 120 are disposed at corners of the main chip module 110, near edges of the interposer.

In some embodiments, as shown in fig. 1, the first chip 110a may be centrally disposed with respect to the interposer 210 in a plan view, and the first chip 110a may have an axisymmetric structure; for example, the symmetry axis of the first chip 110a may coincide with an orthographic projection of a center line of the interposer 210 on the package substrate, the center line of the interposer 210 may extend along the first direction D1 or along the second direction D2, and may also be the symmetry axis of the interposer 210. In some embodiments, the plurality of second chips have substantially the same shape, size, and may be symmetrically disposed with respect to a centerline of the interposer 210 extending in the first direction or the second direction. For example, the first chip 110a has a first side and a second side opposite to each other in the first direction D1, the second chips 110b and 110c are disposed at the first side of the first chip 110a, and the second chips 110D and 110e are disposed at the second side of the first chip 110 a; the second chip 110b and the second chip 110D may be symmetrically disposed about a symmetry axis of the first chip 110a extending in the second direction D2 or a center line of the interposer 210; similarly, the second chip 110c and the second chip 110e may be symmetrically disposed about a symmetry axis of the first chip 110a extending in the second direction D2 or a center line of the interposer 210. The second chips 110b and 110c may be symmetrically disposed about a symmetry axis of the first chip extending in the first direction D1 or a center line of the interposer; the second chips 110D and 110e may be symmetrically disposed about a symmetry axis of the first chip extending in the first direction D1 or a center line of the interposer.

The passive device matrix 120 may overlap one or more chips in the main chip module in at least one of the first direction D1 and the second direction D2. Herein, overlapping of a plurality of members in a certain direction means that the orthographic projections of the plurality of members overlap on a reference plane perpendicular to the direction; that is, the orthographic projection of the passive device matrix 120 on a reference plane (e.g., an extension plane of a sidewall of the package substrate or interposer) perpendicular to the first direction D1 or the second direction D2 overlaps with the orthographic projection of one or more chips in the main chip module on the reference plane.

For example, the passive device matrix 120 may be disposed at one side of the first chip 110a in the first direction D1 and at one side of the second chip in the second direction D2. In the case where a plurality of passive device matrices 120 are provided in a package structure, shapes, sizes, and the like of the plurality of passive device matrices 120 may be the same as or different from each other. In some examples, the passive device matrix 120 may have substantially the same shape and size, and may be disposed substantially symmetrically to each other. For example, in the example shown in fig. 1, two passive device matrices located in the upper left and right corners of the die bonding region or two passive device matrices located in the lower left and right corners of the die bonding region may be symmetrically disposed about the axis of symmetry of the first chip or the center line of the interposer extending in the second direction D2; the two passive device matrices located at the upper left and lower left corners of the die bonding region or the two passive device matrices located at the upper right and lower right corners of the die bonding region may be symmetrically disposed about a center line of the interposer or an axis of symmetry of the first chip extending in the first direction D1.

In some embodiments, the passive device matrix 120 and the main chip module 110 may have sidewalls (or sides) that are substantially aligned in a direction parallel to the major surfaces of the package substrate from a plan view. For example, a sidewall of the passive device matrix 120 may be aligned with a sidewall of the first chip 110a extending in the first direction D1; for example, a sidewall of the passive device matrix 120 may be aligned with a sidewall of the second chip extending in the second direction D2.

It should be understood that the shapes, sizes, numbers, arrangements, etc. of the chips of the main chip module 110 and the passive device matrix 120 shown in fig. 1 are merely illustrative, and the disclosure is not limited thereto. The size, number, arrangement, etc. of the chips of the main chip module 110 and the passive device matrix 120 can be set and adjusted according to the actual product design and requirements, and the warpage of the package structure can be reduced by matching the main chip module 110 with the passive device matrix 120.

With continued reference to fig. 1 and 2, in some embodiments, the passive device matrix 120 is a capacitive matrix, and the passive device chips 120a therein may each be or include silicon capacitors. The provision of the passive device matrix 120 may be advantageous for improving power performance and reliability of the package structure, in addition to reducing warpage of the package structure. For example, compared with the traditional ceramic capacitor mounted on the packaging substrate, the silicon capacitor has higher resonant frequency, can effectively reduce high-frequency noise, has lower parasitic resistance and/or lower parasitic inductance, is more beneficial to reducing the impedance of a power supply network, can greatly reduce the power supply noise, and has higher stability even at high temperature, so that the power supply performance and reliability of the packaging structure can be improved. On the other hand, compared with the ceramic capacitor, the silicon capacitor has smaller size (such as width, thickness and the like), and more silicon capacitors can be arranged in unit volume, so that the overall capacitance of the capacitor matrix is increased, and the power supply noise is reduced.

In particular, under ideal conditions, a capacitor may be considered as a pure capacitor having only capacitive properties, but in practice the capacitor may also have resistive and inductive properties coupled to it, i.e. may also have parasitic resistance, referred to as Equivalent series resistance (Equivalent SERIES RESISTANCE, ESR), and/or parasitic inductance, referred to as Equivalent series inductance (Equivalent Series Inductance, ESL). That is, not only the capacitance C but also a resistance component (i.e., ESR) and an inductance component (i.e., ESL) exist in the capacitor, and thus the impedance characteristic curve of the capacitor exhibits a "V" shape, and exhibits a capacitive characteristic before the resonance frequency, and as the frequency increases, the impedance decreases, and the impedance of the resonance frequency depends on the ESR; after passing the resonance frequency, the impedance characteristic becomes inductive, and the impedance rises with increasing frequency. The inductive impedance characteristics depend on the ESL. The smaller the ESR, the lower the impedance of the resonant frequency. The smaller the ESL, the lower the impedance of the inductive area, so the smaller the ESR and ESL are, the more favorable for removing high-frequency noise, and the smaller the ESR and/or ESL of the silicon capacitor is, so that the impedance of a power network can be better improved, and the power noise is further reduced.

For example, taking a silicon capacitor and a ceramic capacitor of the same capacitance value (e.g., 180 nf) as examples, the resonance frequency point of the ceramic capacitor may be located near 20MHz, the resonance frequency point of the silicon capacitor may be located near 100MHz, and the ESL of the silicon capacitor may be about 1/10 of the ceramic capacitor. That is, the silicon capacitor has a good suppression effect on high-frequency noise on the package structure, and its ESL is only 1/10 of that of the ceramic capacitor, thus having a better decoupling (i.e., removing noise on the power pins of the chip) effect.

When a plurality of passive device matrixes are provided, the sizes of the plurality of passive device matrixes and the number of passive device chips contained in the plurality of passive device matrixes can be the same or different; in the case where the plurality of passive device matrices are a plurality of capacitance matrices, capacitance values of the plurality of capacitance matrices may be the same or different. For example, a plurality of capacitance matrices having different capacitance values may be used, so that noise at different frequency points may be reduced.

For example, in the example shown in fig. 1 and 3,4 capacitance matrices may use the same capacitance type; for example, the capacitance value of a single capacitor in each capacitor matrix is 1 μf, and the capacitance value of each 5×8 capacitor matrix is 5×8×1 μf=40 μf; the total capacitance of the 4 capacitance matrices is 40 μf×4=160 μf. In other examples, power filtering may also be performed using combinations of capacitive matrices having different capacitance values, e.g., multiple capacitive matrices each having a capacitance value of 1uf, 500nf, 180nf, 140nf, etc., may be employed, each disposed in a different free area.

With continued reference to fig. 2, in some embodiments, each chip in the master chip module 110 is electrically connected to the interposer 210 through a first conductive bump 107, and each passive device chip 120a in the passive device matrix 120 is electrically connected to the interposer 210 through a second conductive bump 108. The interposer 210 is electrically connected to the package substrate 300 through the conductive connection 220, and a plurality of conductive terminals 310 may be disposed on a side of the package substrate 300 away from the interposer 210. For example, the first conductive bump 107 and the second conductive bump 108 may each be or include a conductive bump such as a micro-bump (micro-bump). The conductive connection 220 may be or include conductive bumps, such as solder balls, for example, controlled collapse chip connection (Controlled collapsed chip connection, C4) bumps. The conductive terminals 310 may be or include solder balls (solder balls), such as ball grid arrays (ball GRID ARRAY, BGA). However, the disclosure is not limited thereto. For example, the package structure may be further connected to other external components, such as a printed circuit board (printed circuit board, PCB), through the conductive terminals 310.

In some embodiments, the package structure 500 further includes a first underfill layer 160 filling the space between each chip of the main chip module 110 and the interposer 210 and the space between each passive device matrix 120 and the interposer 210 and surrounding the plurality of first conductive bumps 107 and the second conductive bumps 108 in a direction parallel to the main surface of the package substrate.

In some embodiments, the package structure 500 further includes a second underfill layer 230 that fills the space between the interposer 210 and the package substrate 300 and surrounds the plurality of conductive connectors 220 in a direction parallel to the major surface of the package substrate.

In some embodiments, the interposer 210 may be an organic interposer and may include a dielectric structure 200 and a rerouting (redistribution layer, RDL) structure 205. Dielectric structure 200 may comprise an organic dielectric material, such as an epoxy, polyimide, or other suitable polymeric material, and may comprise one or more dielectric layers; the re-wiring structure 205 is embedded in the dielectric structure 200 and may include one or more re-wiring layers, each of which may include conductive lines 201 and/or conductive vias 202. The redistribution structure 205 comprises a suitable conductive material, including, for example, a metallic material such as titanium, copper, and the like. The rewiring structure 205 acts as a conductive member of the interposer 210, providing electrical connections between the components in the package structure. In this example, the interposer 210 is an organic interposer that does not include a semiconductor substrate such as a silicon substrate, i.e., the package structure 500 is a CoWoS-R package, but the disclosure is not limited thereto.

In an alternative embodiment, the package structure 500 may also be CoWoS-S package, and the interposer 210 is a silicon substrate and includes a silicon substrate, substrate vias disposed in the silicon substrate, and interconnect structures disposed on the silicon substrate. In other embodiments, the package structure 500 may also be CoWoS-L package, and the interposer 210 includes bridge chips and rerouting structures embedded in a dielectric structure. The present disclosure is not limited in terms of the type of interposer 210, so long as the interposer 210 can provide electrical connection between related components in the package structure.

With continued reference to fig. 2, in some embodiments, the package structure 500 may further include a stiffener ring 302, the stiffener ring 302 being mounted on the package substrate 300 and may be disposed along an edge of the package substrate 300. For example, the stiffener ring 302 and interposer 210 are disposed on the same side of the package substrate 300. The stiffener ring 302 may comprise a rigid material and may be used to control, improve (e.g., reduce) warpage of the overall package structure.

In some embodiments, when the passive device matrix 120 is a capacitive matrix, providing the passive device matrix 120 facilitates improving the warpage of the package structure, improving the power performance of the package structure, reducing the overall size of the packaged device, and improving the reliability of the package structure. For example, in some package structures without the capacitor matrix, a capacitor such as a ceramic capacitor needs to be disposed on the package substrate 300 to reduce power noise; the ceramic capacitor may be disposed on at least one of a side of the package substrate closer to the interposer and a side thereof farther from the interposer, and electrically connected to the chip in the main chip module through the package substrate and the interposer. In these package structures, although the capacitor is disposed on the package substrate to reduce power noise, the capacitor is disposed at a distance from the main chip, so that the connection paths of the capacitor and the main chip are far, for example, when the capacitor is a filter capacitor, the filter path is far. If the capacitor is arranged on one side of the packaging substrate far away from the intermediate layer, the distance between the capacitor and the chip is further, and the filtering effect of the capacitor is limited; moreover, the capacitor is disposed on the same side of the package substrate as the conductive terminals, so that a region of a portion of the conductive terminals needs to be sacrificed to dispose the capacitor, which may have an adverse effect on a chip having a large power consumption. On the other hand, these capacitors generally use ceramic capacitors, but the Equivalent Series Resistance (ESR) and equivalent series inductance (ESL) of the ceramic capacitors are high, and high-frequency noise cannot be improved. In addition, the ceramic capacitor has a relatively large size and a large occupied area, resulting in an increase in the overall size of the package structure.

In the embodiment of the disclosure, the capacitor matrix is disposed on the interposer 210, and the capacitor matrix is connected to the interposer and connected to the chip in the main chip module through the interposer, so that the capacitor matrix and the main chip module can be shortened without being connected to the interposer through the package substrate, for example, the filtering effect of the filter capacitor can be improved, and the power noise can be reduced. In addition, a plurality of capacitor chips are arranged in the capacitor matrix, and the capacitor matrix has increased capacitance, so that the impedance in the circuit of the packaging structure is reduced more favorably, and the power supply noise is reduced more favorably. The size, capacitance and the like of the passive device matrix of the embodiment of the disclosure can be set and adjusted according to the product requirements.

Moreover, since the capacitor matrix is arranged, the capacitor such as ceramic capacitor is not required to be arranged on the packaging substrate or the number of the capacitors arranged on the packaging substrate can be reduced, so that the additional occupation of the area on the packaging substrate by the capacitor can be avoided or the area on the packaging substrate occupied by the capacitors can be reduced, and the overall size of the packaging structure can be reduced. For example, in some embodiments, the ceramic capacitor 301 may be optionally disposed on a side of the package substrate 300 remote from the conductive terminal 310. In other embodiments, the passive device matrix 120 is a capacitor matrix, and the ceramic capacitors 301 may be omitted, which may be advantageous to reduce the overall size of the package structure. Ceramic capacitor 301 is shown in phantom, indicating that the ceramic capacitor may be selectively disposed on the package substrate and may be omitted in some examples. Moreover, in the embodiments of the present disclosure, since the capacitor matrix is provided, power noise can be effectively reduced, and thus, it is unnecessary to provide a capacitor on a side of the package substrate 300 away from the interposer, and thus, it is unnecessary to occupy an area of the conductive terminal 310, and thus, a sufficient number of conductive connectors can be provided to provide electrical connection of the package structure with an external member (e.g., a power terminal).

The embodiment of the disclosure provides a manufacturing method of a packaging structure, which comprises the following steps: providing a main chip module and a passive device matrix; providing an interposer, arranging a main chip module and a passive device matrix on a first side of the interposer side by side and electrically connecting the main chip module and the passive device matrix with the interposer; the interposer is electrically connected to the package substrate, and the package substrate is disposed on a second side of the interposer, the second side being opposite to the first side, wherein the passive device matrix has a plurality of chip regions and dicing reserved regions, and includes a plurality of passive device chips disposed on the plurality of chip regions, respectively, the plurality of passive device chips being disposed side by side in a direction parallel to a main surface of the package substrate and being spaced apart from each other by the dicing reserved regions, and the passive device matrix has a substrate continuously extending between the plurality of chip regions and the dicing reserved regions.

In some embodiments, forming the matrix of passive devices includes: providing a passive device wafer having a plurality of die areas and a dicing area, each die area having one passive device die disposed therein, the dicing area being located between adjacent die areas and spacing adjacent passive device dies, wherein the passive device wafer comprises a matrix area comprising an initial passive device matrix located therein, the initial passive device matrix comprising a plurality of passive device dies arranged in an n x m array and a first dicing area located between the plurality of passive device dies, the dicing area further comprising a second dicing area located around the matrix area; a wafer dicing process is performed on the passive device wafer along dicing paths that extend at least partially along the second dicing regions to separate the initial passive device matrix from other passive device chips in the passive device wafer and form a passive device matrix, wherein the first dicing regions remain in the passive device matrix and form at least a portion of the dicing remain.

In some embodiments, disposing the master chip module and the passive device matrix side-by-side on a first side of the interposer and electrically connecting with the interposer includes: a main chip bonding region bonding the main chip module to the chip bonding region of the interposer; calculating the spare area of the chip bonding area except the main chip bonding area; calculating the matrix area of the required passive device matrix according to the spare area, so that the matrix area is smaller than or equal to the spare area; calculating n and m values of an n multiplied by m array based on the matrix area, and determining the position of a matrix area in the passive device wafer; performing a wafer cutting process, and enabling the size of the formed passive device matrix to be matched with the size of the spare area; and bonding the matrix of passive devices to the free area of the interposer. For example, in a matrix of an n.times.m array, n.gtoreq.1, m.gtoreq.1, and n+m > 2.

Fig. 5 illustrates a plan view of a passive device wafer according to some embodiments of the present disclosure. For example, the passive device matrix 120 in the package structure is cut from the passive device wafer.

Referring to fig. 5, in some embodiments, the passive device wafer 10 is provided with a plurality of die areas 101 and dicing areas 12, one passive device die 120a being provided in each die area 101; the plurality of passive device chips 120a are spaced apart from each other by the dicing regions 12. The plurality of passive device chips 120a may be arranged in an array, for example, may be arranged in an array including a plurality of rows and a plurality of columns along the first direction D1 and the second direction D2. The dicing area 12 is located between adjacent passive device chips 120a to space adjacent passive device chips 120a apart. One or more alignment marks, such as alignment during a manufacturing process for passive device chips, a wafer dicing process, etc., may be provided in the dicing area 12.

For example, a matrix region MR is located in the passive device wafer, the matrix region MR including a plurality of passive device chips 120a and a first dicing region 12a located between the plurality of passive device chips 120 a; the matrix region MR is the region in the wafer where the subsequently formed passive device matrix 120 is located prior to the wafer dicing process. The first cutting region 12a is a portion of the cutting region 12 located in the matrix region MR, and the cutting region 12 further includes a second cutting region 12b located around the matrix region MR.

The passive device wafer 10 is subjected to a dicing process by which the portion of the wafer located in the matrix region MR is diced from the wafer and the passive device matrix 120 is formed, i.e., the passive device matrix located in the matrix region MR is separated from other passive device chips in the wafer by the wafer dicing process. For example, the passive device wafer 10 is subjected to a wafer dicing process along dicing paths that extend at least partially along the second dicing regions 12b to separate the passive device matrix from other passive device chips that are located outside the matrix region MR and form a passive device matrix 120 as shown in fig. 3. In some embodiments, the matrix of passive devices that may be located in the matrix area of the wafer prior to the wafer dicing process may also be referred to as an initial matrix of passive devices; that is, the wafer dicing process cuts the initial passive device matrix from the wafer to form the passive device matrix.

For example, fig. 5 schematically illustrates a first dicing path CL1, a second dicing path CL2, a third dicing path CL3, and a fourth dicing path CL4 of the wafer dicing process, each of which extends at least partially along the second dicing area 12b around the matrix area. For example, the first and second dicing paths CL1 and CL2 may extend in the first direction D1, and the third and fourth dicing paths CL3 and CL4 may extend in the second direction D2, the dicing paths intersecting each other and defining the boundaries of the passive device matrix. The dicing path of the wafer dicing process does not pass through the first dicing area 12a between the plurality of passive device chips located within the matrix area. The wafer dicing process may be or include a mechanical sawing (MECHANICAL SAW) process, a laser drilling (LASER DRILLING) process, a laser dicing process, or a combination thereof.

After the wafer dicing process, the passive device matrix 120 located in the matrix region MR is separated from other passive device chips of the wafer located outside the matrix region MR; the plurality of passive device chips 120a located in the matrix region MR remain in the formed passive device matrix 120, i.e. at least part of the dicing remain region 102 shown in fig. 3, because the dicing regions between the passive device chips 120a are not subjected to dicing process, and the plurality of passive device chips 120a in the passive device matrix still continue to each other, share the same substrate, and are not independent of each other. In some embodiments, the second dicing area 12b outside the outer sidewall of the edge passive device chip of the passive device matrix 120 may be partially removed in the dicing process, while partially remaining in the passive device matrix 120 and being part of the dicing reserved area 102; in other embodiments, the second scribe areas 12b of the edge passive device matrix 120 other than the outer sidewalls of the edge passive device chips may be completely removed in the wafer dicing process and such that the sidewalls of the edge passive devices may be exposed at the sidewalls of the passive device matrix.

Fig. 6 shows a schematic flow chart of a part of a process of a method of manufacturing a package structure according to some embodiments of the present disclosure.

Referring to fig. 1-3 and 5, 6, in some embodiments, the following steps are included in a method of manufacturing a package structure 500;

In a first step S01, one or more chips in the main chip module 110 are bonded to a first bonding region R1 of the interposer 210, which first bonding region R1 may also be referred to as a main chip bonding region.

In a second step S02, the free area of the free region (i.e., the second bonding region R2) of the die bonding region BR of the interposer 210 other than the first bonding region R1 is calculated. It should be appreciated that there may be one or more free areas, and when there are multiple free areas, the free areas of the multiple free areas are calculated separately. Each empty region corresponds to a matrix of passive devices.

In a third step S03, setting a matrix area of the required passive device matrix based on the spare area; for example, the matrix area may be less than or approximately equal to the free area.

In a fourth step S04, determining the position of the matrix region in the passive device wafer based on the matrix area obtained in the third step S03; for example, the number and arrangement modes of the passive device chips in the passive device matrix are calculated according to the matrix area; for example, a passive device matrix includes a plurality of passive device chips arranged in an n×m array, and this step calculates the values of n and m. For example, a matrix form meeting the matrix area can be calculated according to the size of a single passive device chip in the passive device wafer, the size of a cutting area and the like, namely, values of n and m are obtained; the locations of the satisfactory matrix areas are then determined in the wafer.

In a fifth step S05, the wafer dicing process is performed to dice the passive device matrix located in the matrix area from the passive device wafer, that is, the desired passive device matrix arranged in an n×m array is diced from the passive device wafer, and the size of the formed passive device matrix is made to match the size of the spare area.

It should be understood that, when there are a plurality of free areas, after the free areas of the plurality of free areas are calculated in the second step S02, respectively, one or more subsequent third to fifth steps S03 to S05 may be performed, thereby obtaining a passive device matrix matched with each free area. Multiple passive device matrices for different spare areas may be cut from the same passive device wafer or different passive device wafers, and the size of the multiple passive device matrices, etc. may be the same or different. The capacitance values of the multiple passive device matrices may be the same or different.

In a sixth step S06, the passive device matrix 120 is bonded to the vacant areas of the interposer 210, i.e., the second bonding regions R2.

Thereafter, an interposer provided with a main chip module and a passive device matrix is bonded to the package substrate.

It should be understood that the steps shown in fig. 6 are merely illustrative of some steps included in the method of manufacturing the package structure, and are not intended to limit the order of the steps, and in the method of manufacturing the package structure, the steps may be performed sequentially, but may not be performed sequentially, for example, some steps may be performed alternately, or one or more steps may be performed simultaneously; or the method of manufacturing the package structure may further comprise other process steps than the above.

The manufacturing method of the package structure of the embodiment of the disclosure has the same technical effects as described above for the package structure, and the passive device matrix can simplify the process, for example, the wafer dicing process and the bonding process of a plurality of passive device chips of the passive device matrix and the interposer, so that the process efficiency can be improved, the chip failure risk can be reduced, the yield can be improved, and the process cost can be reduced.

The following points need to be described:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.

(2) Features of the same and different embodiments of the disclosure may be combined with each other without conflict.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A package structure, comprising:

packaging a substrate;

An interposer electrically connected to the package substrate and having a first side and a second side opposite to each other, wherein the package substrate is disposed on the second side of the interposer; and

A main chip module and at least one passive device matrix disposed side by side on the first side of the interposer in a direction parallel to a major surface of the package substrate and electrically connected through the interposer,

Wherein each of the passive device matrices has a plurality of chip regions and a dicing reserved region, and includes a plurality of passive device chips respectively disposed in the plurality of chip regions, the plurality of passive device chips being disposed side by side in a direction parallel to a main surface of the package substrate and being spaced apart from each other by the dicing reserved region, wherein the passive device matrix has a substrate continuously extending between the plurality of chip regions and the dicing reserved region.

2. The package structure of claim 1, wherein the passive device matrix comprises:

The substrate comprises a first substrate part positioned in the plurality of chip areas and a second substrate part positioned in the cutting reserved area; and

A dielectric structure disposed on one side of the substrate, extending continuously between the plurality of chip regions and the dicing reserved region, and including a first dielectric portion in the plurality of chip regions and a second dielectric portion in the dicing reserved region;

wherein each passive device chip includes one or more passive devices disposed in or on at least one of the first substrate portion and the first dielectric portion.

3. The package structure of claim 2, wherein the cut-and-hold region comprises at least the second substrate portion and the second dielectric portion, and an orthographic projection of the one or more passive devices on the package substrate does not overlap with an orthographic projection of the cut-and-hold region on the package substrate.

4. The package structure of claim 3, wherein the dicing reserved area further comprises an alignment mark disposed in or on at least one of the second substrate portion and the second dielectric portion.

5. The package structure of any one of claims 1-4, wherein the passive device matrix is a capacitive matrix and each passive device chip includes one or more capacitors.

6. The package structure of claim 5, wherein each passive device chip comprises a silicon capacitor.

7. The package structure of claim 5, wherein a plurality of capacitances of the plurality of passive device chips are connected in parallel with each other through the interposer.

8. The package structure according to any one of claims 1 to 4, further comprising:

And the encapsulation layer is arranged on the first side of the medium layer, surrounds and encapsulates the main chip module and the passive device matrix, covers the side walls of the main chip module and the passive device matrix, and fills a gap between the main chip module and the passive device matrix.

9. The package structure of claim 8, wherein the plurality of passive device chips comprises an edge passive device chip adjacent to or near an edge of the encapsulation layer adjacent to the main chip module, the edge passive device chip having a first chip side and a second chip side opposite or adjacent to each other;

The first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is encapsulated by the encapsulation layer, and the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix and is adjacent to the dicing reserved area and separated from the encapsulation layer.

10. The package structure of any one of claims 1 to 4, wherein the main chip module includes first and second chips, the first and second chips and a plurality of passive device chips in the passive device matrix being electrically connected to each other through the interposer.

11. The package structure of claim 10, wherein the first chip comprises a logic chip and the second chip comprises a memory chip.

12. The package structure of claim 11, wherein the logic chip comprises a system chip, the memory chip comprising a high bandwidth memory chip.

13. The package structure of claim 1, wherein the passive device matrix and the main chip module have sidewalls aligned in a direction parallel to a main surface of the package substrate as viewed in a plan view.

14. The package structure of claim 1, wherein the at least one passive device matrix comprises a plurality of passive device matrices, and the plurality of passive device matrices are disposed on the same side or different sides of the main chip module in a direction parallel to a major surface of the package substrate.

15. A method of manufacturing a package structure, comprising:

Providing a main chip module and a passive device matrix;

providing an interposer, arranging the main chip module and the passive device matrix side by side on a first side of the interposer and electrically connecting with the interposer;

Electrically connecting the interposer to a package substrate disposed on a second side of the interposer opposite the first side,

The passive device matrix is provided with a plurality of chip areas and cutting reserved areas, and comprises a plurality of passive device chips which are respectively arranged on the plurality of chip areas, the plurality of passive device chips are arranged side by side in a direction parallel to the main surface of the packaging substrate and are mutually spaced through the cutting reserved areas, and the passive device matrix is provided with a substrate which continuously extends between the plurality of chip areas and the cutting reserved areas.

16. The method of manufacturing a package structure of claim 15, wherein providing the matrix of passive devices comprises:

Providing a passive device wafer having a plurality of die regions and a dicing region, each die region having one passive device die disposed therein, the dicing region being located between adjacent die regions and spacing adjacent passive device dies, wherein the passive device wafer comprises a matrix region comprising an initial passive device matrix located therein, the initial passive device matrix comprising a plurality of passive device dies arranged in an n x m array and a first dicing region located between the plurality of passive device dies, the dicing region further comprising a second dicing region located around the matrix region;

And performing a wafer dicing process on the passive device wafer along a dicing path extending at least partially along the second dicing area to separate the initial passive device matrix from other passive device chips in the passive device wafer and form the passive device matrix, wherein the first dicing area remains in the passive device matrix and forms at least part of the dicing remains.

17. The method of manufacturing a package structure of claim 16, wherein disposing the host chip module and the passive device matrix side-by-side on the first side of the interposer and electrically connecting with the interposer comprises:

a main chip bonding region bonding the main chip module to a chip bonding region of the interposer;

Calculating the spare area of the chip bonding area except the main chip bonding area;

calculating the matrix area of the required passive device matrix according to the spare area, so that the matrix area is smaller than or equal to the spare area;

calculating values of n and m of the n×m array based on the matrix area, and determining a position of the matrix area in the passive device wafer;

performing the wafer dicing process and matching the size of the formed passive device matrix to the size of the spare area; and

Bonding the matrix of passive devices to the free area of the interposer.

18. The method of claim 16 or 17, wherein n is 1 or more, m is 1 or more, and n+m > 2.