CN111696024B - Infrared image mirroring method and device based on FPGA - Google Patents
Infrared image mirroring method and device based on FPGA Download PDFInfo
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Abstract
The invention provides a mirror image method and a mirror image device for an infrared image based on an FPGA, which are characterized in that an A/D conversion unit, the FPGA, an external memory and a CPU are configured, and original infrared image data after A/D conversion is subjected to line buffering, line processing and AXI bus address writing operation, so that the infrared image is rapidly and timely mirror image processed and stored, the CPU is not required to be occupied for mirror image processing, a large amount of resources and system expenditure can be saved, the real-time processing speed of the image is improved, and a good real-time processing effect can be maintained even facing a large-size infrared image.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to an infrared image mirroring method and device based on an FPGA.
Background
The infrared image is an image formed by acquiring the intensity of infrared light of an object, and the difference of outward radiation energy of a target and a background is felt and reflected, so that the infrared image belongs to passive imaging. The infrared radiation can penetrate through fog, haze and atmosphere and has stronger anti-interference capability than visible light intensity, so that the object can be detected by overcoming part of visual barriers. The types of mirroring operations for images typically include original images, horizontal mirroring, vertical mirroring, and diagonal mirroring; in the existing infrared image mirroring method, images are stored in an external memory such as DDR (double data rate) and processed pixel by a CPU (central processing unit). With the continuous development of infrared detectors, the resolution of the infrared images output by the infrared detectors is larger and larger, the maximum resolution of the infrared detectors at present reaches 1280 multiplied by 1024, the processing speed of a CPU is limited, the CPU directly carries out mirror image processing on pixels can not meet the requirement on real-time infrared image processing with high resolution, and especially in an embedded system with limited resources, the instantaneity is influenced by the size of the resolution of the images and the capability of the system, so that the actual processing time of image mirror image is longer, the time delay is longer, and the requirement on real-time processing of the images can not be met.
Disclosure of Invention
In view of the above, the invention provides a method and a device for mirroring an infrared image based on an FPGA, which are used for carrying out image line processing in the FPGA, completing the mirroring processing of the image in the image storage process and realizing high instantaneity of image processing.
In one aspect, the invention provides a mirroring method of an infrared image based on an FPGA, which comprises an A/D conversion unit, the FPGA, an external memory and a CPU, wherein the A/D conversion unit performs A/D conversion on an acquired original infrared image; after mirror image processing is carried out on the original infrared image data after the A/D conversion in the FPGA, the original infrared image data after mirror image processing is sent to an external memory for storage through a data bus of the FPGA; the CPU interacts with the FPGA to determine the operation type of the FPGA for mirroring the original infrared image data;
the method for mirroring the image by the FPGA comprises the following steps of;
s1: the method comprises the steps that collected original infrared image data are sequentially sent to an input port of an FPGA from top to bottom according to the sequence of image rows after being processed by an A/D conversion unit in a digital format;
s2: a first intra-chip cache unit BlockRAM0, a second intra-chip cache unit BlockRAM1, a read-write address control unit and an AXI bus control unit are configured in a chip of the FPGA, the first intra-chip cache unit BlockRAM0 and the second intra-chip cache unit BlockRAM1 can perform read-write operation at the same time, and the first intra-chip cache unit BlockRAM0 and the second intra-chip cache unit BlockRAM1 are used for constructing ping-pong cache; the bit width pixw of the first intra-chip buffer memory unit BlockRAM0 and the second intra-chip buffer memory unit BlockRAM1 are the same as the pixel width of the original infrared image data, and the depth w of the first intra-chip buffer memory unit BlockRAM0 and the second intra-chip buffer memory unit BlockRAM1 are the same as the line pixel number of the original infrared image; the read-write address control unit distributes addresses in the table tennis buffer and performs read-write operation; the read-write address control unit is also connected with the AXI bus control unit in a signal way, and the data read by the read-write address control unit are sent to an external memory for storage through the AXI bus control unit;
s3: the read-write address control unit of the FPGA writes the received original infrared image data of the first row into the first in-chip buffer memory unit BlockRAM0 from left to right, and the address written into the first in-chip buffer memory unit BlockRAM0 is increased from 0 to w-1 until the original infrared image data of the first row is completely written; then the read-write address control unit writes the received original infrared image data of the second line into a second on-chip buffer memory unit BlockRAM1 according to the left-to-right sequence, and the address written into the second on-chip buffer memory unit BlockRAM1 is increased according to 0 to w-1 until the original infrared image data of the second line is written; then the read-write address control unit writes the received original infrared image data of the third row into the first in-chip buffer memory unit Block RAM0 according to the left-to-right sequence, and so on, alternately writes the data of the original infrared image data of each row into the ping-pong buffer memory until the data of all rows of the original infrared image data are written into the ping-pong buffer memory;
s4: after each time the ping-pong buffer writes a line of complete original infrared image data, a read-write address control unit of the FPGA processes the line of the complete original infrared image data which is written in the ping-pong buffer last time and reads the address of the ping-pong buffer; according to different mirror image operation types, decomposing the complete infrared image data of each line into a plurality of Burst data, wherein the read-write address control unit reads the ping-pong cache addresses in different modes;
s5: the read-write address control unit of the FPGA executes mirror image write address operation on the whole row of infrared image data after the row processing is finished in the previous step through the AXI bus control unit, and writes each Burst data into an external memory for storage through the AXI bus control unit until the data of all rows of the infrared image are written, so that infrared image data after mirror image processing is obtained; the way in which the entire line of infrared image data is written into the external memory differs according to the type of mirror operation.
On the basis of the above technical solution, preferably, when the mirror image operation type is the original image, the FPGA performs row processing on the original infrared image data, that is, the read-write address control unit reads the data in each address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1 according to the ascending order of the addresses 0 to w-1 until the reading of the whole row of original infrared image data is completed; blockraddr=i, i= {0,1,2, … w-2,w-1}, blockRaddr is a read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is a sequential count of the read original infrared image data.
Further preferably, when the type of the mirroring operation is an original image, the mirroring write address operation is performed by sequentially writing each Burst data of each line of complete infrared image data into the external memory from top to bottom according to the ascending order of the read address; the write address offset starts from 0, the base address of the external memory locates BaseAddr, the AXI bus control unit writes the bus address DDRWaddr=BaseAddr of the first Burst data, and the number of bytes written by one Burst data is Burst; the bus address of the AXI bus control unit for writing adjacent Burst data is increased by Burst byte, namely the writing address of the current AXI bus control unit is BaseAddr+burst byte; and the like until all the Burst data of each complete line of infrared image data are written into the external memory.
Still preferably, when the mirroring operation type is horizontal mirroring, the FPGA performs row processing on the original infrared image data, that is, the read-write address control unit reads the data in each address of the first intra-chip cache unit BlockRAM0 or the second intra-chip cache unit BlockRAM1 according to the descending order of the addresses w-1 to 0 until the reading of the whole row of original infrared image data is completed; blockraddr=w-1-i, i= {0,1,2, … w-2,w-1}, blockRaddr is a read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is a sequential count of the read original infrared image data.
Still further preferably, when the mirroring operation type is horizontal mirroring, the mirroring write address operation is performed by sequentially writing each Burst data of each line of complete infrared image data into the external memory from top to bottom according to a descending order of the read address; the write address offset starts from 0, the base address of the external memory is defined as BaseAddr, the bus address DDRWaddr=BaseAddr of the first Burst data written by the AXI bus control unit, and the byte number written by one Burst data is Burst byte; the bus address of the AXI bus control unit for writing adjacent Burst data is increased by Burst byte, namely the current bus writing address is BaseAddr+burst byte; and the like until all the Burst data of each complete line of infrared image data are written into the external memory.
Further preferably, when the mirroring operation type is vertical mirroring, the FPGA performs row processing on the original infrared image data, that is, uses the first Burst data at the tail end of the row of original infrared image data as initial read data of the read-write address control unit, reads the Burst data in the direction of the lower address according to the last address of the Burst data, and reads one Burst data adjacent to the row of original infrared image data after the current Burst data is read; until the reading of the whole line of original infrared image data is completed;
blockraddr=w-1- ((i &0xffc 0) | (63- (i &0x3 f))), i= {0,1,2, … w-2,w-1}, where BlockRaddr is the read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is the sequential count of the read original infrared image data.
Further preferably, when the mirroring operation type is diagonal mirroring, the FPGA performs row processing on the original infrared image data, that is, uses the first Burst data at the head end of the row of original infrared image data as the initial read data of the read-write address control unit, reads the Burst data in the direction of the lower address according to the last address of the Burst data, and reads an adjacent Burst data of the row of original infrared image data after the current Burst data is read; until the reading of the whole line of original infrared image data is completed;
blockraddr= ((i &0xffc 0) | (63- (i &0x3 f))), i= {0,1,2, … w-2,w-1}, where BlockRaddr is the read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is the sequential count of the read original infrared image data.
Still further preferably, when the mirroring operation type is vertical mirroring or diagonal mirroring, the mirroring write address operation is performed by sequentially writing each Burst data of each line of complete infrared image data into the external memory from bottom to top in descending order of addresses; the write address offset starts from the base address, the base address of the external memory is defined as BaseAddr, the bus address of the first Burst data written by the AXI bus control unit is DDRWaddr=BaseAddr+ImageByte-Burst byte, and the number of bytes written by one Burst data is Burst byte; then the bus of the AXI bus control unit for writing adjacent Burst data decrements the address by Burst byte, namely the current bus writing address is BaseAddr+ImageByte-2. Burst byte; and the like, until all Burst data of each line of complete infrared image data are written into an external memory; imageByte is the size of the original infrared image data.
On the basis of the above technical solution, preferably, the external memory is DDRRAM.
On the other hand, the invention also provides a device for mirroring the infrared image based on the FPGA, which comprises an A/D conversion unit, the FPGA, an external memory and a CPU, wherein the CPU is respectively in communication connection with the FPGA and the external memory, and the A/D conversion unit, the FPGA, the external memory and the CPU can realize the mirroring method according to any one of claims 1-9; the CPU sends a mirror image operation instruction to the FPGA, the read-write address control unit of the FPGA performs line buffering and line processing on the original infrared image data sent by the A/D conversion unit, the AXI bus control unit stores the mirror image processed infrared image data to the external memory, and the CPU or the FPGA directly calls the mirror image processed infrared image data stored in the external memory for the subsequent processing of the image.
Compared with the prior art, the method and the device for mirroring the infrared image based on the FPGA have the following beneficial effects:
(1) According to the invention, the FPGA is used for carrying out real-time original image line data caching in the chip, carrying out line buffering, line processing and AXI bus address writing operation according to the actual demand of mirroring, and sending the data to an external memory for storage through a data bus so as to enable other devices to call infrared image data after mirroring, compared with the existing CPU for processing the image pixel by pixel from the external memory, the system overhead is greatly saved, especially in an embedded system with tense resources, a large amount of system resources are saved, and the response time of mirroring can be improved;
(2) Because the data is processed in real time and transmitted in real time, the real-time performance of the method of the invention is not reduced because of the increase of the resolution of the infrared image;
(3) The AXI bus used in the FPGA uses transmission based on Burst, has independent read address and write address channels, supports various addressing modes, and has wide applicability, good compatibility and high reliability;
(4) The CPU, the FPGA or other subsequent data processing units can directly read the image data subjected to mirror image processing from the external memory, and the data processing is not performed on the CPU itself, so that the device structure can be simplified, and the processing capability of the CPU can be improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a method and apparatus for mirroring an infrared image based on an FPGA of the present invention;
FIG. 2 is a schematic diagram of a ping-pong cache of an FPGA of the method and apparatus for mirroring an infrared image based on the FPGA of the present invention;
FIG. 3 is a line processing flow when the mirroring operation type of the method and the device for mirroring an infrared image based on an FPGA of the present invention is an original image;
FIG. 4 is a line processing flow when the mirroring operation type of the method and the device for mirroring the infrared image based on the FPGA is horizontal mirroring;
FIG. 5 is a line processing flow when the mirroring operation type of the method and the device for mirroring an infrared image based on an FPGA of the present invention is vertical mirroring;
FIG. 6 is a line processing flow when the mirroring operation type of the method and apparatus for mirroring an infrared image based on an FPGA of the present invention is diagonal mirroring;
FIG. 7 is a process flow of writing line processing data of an original image into an external memory according to the mirroring method and device of an infrared image based on an FPGA of the present invention;
FIG. 8 is a process flow of writing line processing data with the mirror operation type of horizontal mirror image into an external memory according to the method and the device for mirroring an infrared image based on an FPGA of the present invention;
FIG. 9 is a process flow of writing line processing data with the mirror operation type of vertical mirror image into an external memory according to the method and the device for mirroring an infrared image based on an FPGA of the present invention;
fig. 10 is a process flow of writing line processing data with a mirror operation type of diagonal mirror image into an external memory, according to the method and the device for mirroring an infrared image based on an FPGA of the present invention.
Detailed Description
The following description of the embodiments of the present invention will clearly and fully describe the technical aspects of the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
As shown in fig. 1 and 2, in one aspect, the present invention provides a method for mirroring an infrared image based on an FPGA, including an a/D conversion unit, an FPGA, an external memory, and a CPU, where the a/D conversion unit performs a/D conversion on an acquired original infrared image; after mirror image processing is carried out on the original infrared image data after the A/D conversion in the FPGA, the original infrared image data after mirror image processing is sent to an external memory for storage through a data bus of the FPGA; the CPU interacts with the FPGA to determine the operation type of the FPGA for mirroring the original infrared image data.
The image mirroring method comprises the following steps;
s1: the method comprises the steps that collected original infrared image data are sequentially sent to an input port of an FPGA from top to bottom according to the sequence of image rows after being processed by an A/D conversion unit in a digital format;
s2: a first intra-chip cache unit BlockRAM0, a second intra-chip cache unit BlockRAM1, a read-write address control unit and an AXI bus control unit are configured in a chip of the FPGA, the first intra-chip cache unit BlockRAM0 and the second intra-chip cache unit BlockRAM1 can perform read-write operation at the same time, and the first intra-chip cache unit BlockRAM0 and the second intra-chip cache unit BlockRAM1 are used for constructing ping-pong cache; the bit width pixw of the first intra-chip buffer memory unit BlockRAM0 and the second intra-chip buffer memory unit BlockRAM1 are the same as the pixel width of the original infrared image data, and the depth w of the first intra-chip buffer memory unit BlockRAM0 and the second intra-chip buffer memory unit BlockRAM1 are the same as the line pixel number of the original infrared image; the read-write address control unit distributes addresses in the table tennis buffer and performs read-write operation; the read-write address control unit is also connected with the AXI bus control unit in a signal way, and the data read by the read-write address control unit are sent to an external memory for storage through the AXI bus control unit; the ping-pong buffer can work alternately to realize continuous input of the original infrared image data; when the FPGA reads the line data of the original infrared image written in the first on-chip buffer memory unit BlockRAM0, the second on-chip buffer memory unit BlockRAM1 can write the line data of another line of the original infrared image, and the two on-chip buffer memory units alternately write the original infrared image data, so that the real-time processing capacity of the image data can be conveniently improved subsequently; namely, the input of the subsequent line processing is continuous, so that the real-time performance of the image data processing can be improved;
s3: the read-write address control unit of the FPGA writes the received original infrared image data of the first row into the first in-chip buffer memory unit BlockRAM0 from left to right, and the address written into the first in-chip buffer memory unit BlockRAM0 is increased from 0 to w-1 until the original infrared image data of the first row is completely written; then the read-write address control unit writes the received original infrared image data of the second line into a second on-chip buffer memory unit BlockRAM1 according to the left-to-right sequence, and the address written into the second on-chip buffer memory unit BlockRAM1 is increased according to 0 to w-1 until the original infrared image data of the second line is written; then the read-write address control unit writes the received original infrared image data of the third row into the first in-chip buffer memory unit Block RAM0 according to the left-to-right sequence, and so on, alternately writes the data of the original infrared image data of each row into the ping-pong buffer memory until the data of all rows of the original infrared image data are written into the ping-pong buffer memory;
s4: after each time the ping-pong buffer writes a line of complete original infrared image data, a read-write address control unit of the FPGA processes the line of the complete original infrared image data which is written in the ping-pong buffer last time and reads the address of the ping-pong buffer; according to different mirror image operation types, decomposing the complete infrared image data of each line into a plurality of Burst data, wherein the read-write address control unit reads the ping-pong cache addresses in different modes;
the mirror operation types mainly include original image, horizontal mirror, vertical mirror, and diagonal mirror types. The four mirror type row processing modes are described below.
ImageByte is the size of original infrared image data, the original infrared image data has a plurality of rows, and the width of each row of the original infrared image data is the same as the depth w of the first in-chip buffer memory unit BlockRAM0 and the second in-chip buffer memory unit BlockRAM 1; the bit width pixw of the first intra-chip buffer memory unit Block RAM0 and the second intra-chip buffer memory unit Block RAM1 are the same as the pixel width of the original infrared image data; if the height of the original infrared image is h, the image size ImageByte is (w.h.pixw)/8 in Byte.
The FPGA adopts an AXI bus to write into an external memory, and a Burst mode is adopted. The AXI bus has a data width of 64 bits and a number of bytes written to each Burst mirror write address of 128. The first on-chip buffer memory unit BlockRAM0 and the second on-chip buffer memory unit BlockRAM1 belong to dual-port RAM memories of the FPGA, and are used for storing two adjacent lines of data of original infrared image data.
As shown in fig. 3, fig. 4, fig. 5 and fig. 6, when the mirroring operation type is the original image, the FPGA performs row processing on the original infrared image data, that is, the read-write address control unit reads the data in each address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1 according to the ascending order of the addresses 0 to w-1 until the reading of the whole row of original infrared image data is completed; blockraddr=i, i= {0,1,2, … w-2,w-1}, blockRaddr is a read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is a sequential count of the read original infrared image data. As shown in fig. 3, the order of the original image at the time of writing and line processing is the same, and the original image is processed in order of addresses from small to large and from left to right.
When the mirror image operation type is horizontal mirror image, the FPGA performs row processing on the original infrared image data, namely the read-write address control unit reads the data in each address of the first on-chip buffer memory unit BlockRAM0 or the second on-chip buffer memory unit BlockRAM1 according to the descending order of the addresses w-1 to 0 until the reading of the whole row of original infrared image data is completed; blockraddr=w-1-i, i= {0,1,2, … w-2,w-1}, blockRaddr is a read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is a sequential count of the read original infrared image data. As shown in fig. 4, the horizontal mirrored line processing is to read the contents of each address of the first intra-chip cache unit BlockRAM0 or the second intra-chip cache unit BlockRAM1 from right to left.
When the mirror image operation type is vertical mirror image, the first Burst data at the tail end of the row of original infrared image data is used as the initial read data of the read-write address control unit, the Burst data is read to the direction of the low-order address according to the last-order address of the Burst data, and after the current Burst data is read, one Burst data adjacent to the row of original infrared image data is read; until the reading of the whole line of original infrared image data is completed;
blockraddr=w-1- ((i &0xffc 0) | (63- (i &0x3 f))), i= {0,1,2, … w-2,w-1}, where BlockRaddr is the read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is the sequential count of the read original infrared image data. As shown in fig. 5, the vertical mirrored row process starts with the last Burst data, but the contents in the Burst data are still read in left to right order.
When the mirror image operation type is diagonal mirror image, the FPGA processes the line of the original infrared image data, namely, the first Burst data at the head end of the line of the original infrared image data is used as the initial read data of the read-write address control unit, the Burst data is read to the lower address direction according to the last address of the Burst data, and after the current Burst data is read, the adjacent Burst data of the line of the original infrared image data is read; until the reading of the whole line of original infrared image data is completed;
blockraddr= ((i &0xffc 0) | (63- (i &0x3 f))), i= {0,1,2, … w-2,w-1}, where BlockRaddr is the read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is the sequential count of the read original infrared image data. As shown in fig. 6, the diagonally mirrored line processing is to sequentially read Burst data of each line from the head to the tail, but the contents of each Burst data are read out in reverse order.
S5: the read-write address control unit of the FPGA executes mirror image write address operation on the whole row of infrared image data after the row processing is finished in the previous step through the AXI bus control unit, and writes each Burst data into an external memory for storage through the AXI bus control unit until the data of all rows of the infrared image are written, so that infrared image data after mirror image processing is obtained; the way in which the entire line of infrared image data is written into the external memory differs according to the type of mirror operation.
The various write address operations are described below in connection with the figures for different mirror operation types.
As shown in fig. 7, the mirror write address operation is performed by sequentially writing each Burst data of each line of complete infrared image data into the external memory from top to bottom in the order of increasing read address; the write address offset starts from 0, the base address of the external memory locates BaseAddr, the AXI bus control unit writes the bus address DDRWaddr=BaseAddr of the first Burst data, and the number of bytes written by one Burst data is Burst; the bus address of the AXI bus control unit for writing adjacent Burst data is increased by Burst byte, namely the writing address of the current AXI bus control unit is BaseAddr+burst byte; and the like until all the Burst data of each complete line of infrared image data are written into the external memory.
As shown in fig. 8, when the mirroring operation type is horizontal mirroring, performing the mirroring write address operation is to sequentially write each Burst data of each line of complete infrared image data into the external memory from top to bottom according to the descending order of the read address; the write address offset starts from 0, the base address of the external memory is defined as BaseAddr, the bus address DDRWaddr=BaseAddr of the first Burst data written by the AXI bus control unit, and the byte number written by one Burst data is Burst byte; the bus address of the AXI bus control unit for writing adjacent Burst data is increased by Burst byte, namely the current bus writing address is BaseAddr+burst byte; and the like until all the Burst data of each complete line of infrared image data are written into the external memory.
As shown in fig. 9 and 10, when the mirroring operation type is vertical mirroring or diagonal mirroring, the mirroring write address operation is performed by sequentially writing each Burst data of each line of complete infrared image data into the external memory from bottom to top in descending order of addresses; the write address offset starts from the base address, the base address of the external memory is defined as BaseAddr, the bus address of the first Burst data written by the AXI bus control unit is DDRWaddr=BaseAddr+ImageByte-Burst byte, and the number of bytes written by one Burst data is Burst byte; then the bus of the AXI bus control unit for writing adjacent Burst data decrements the address by Burst byte, namely the current bus writing address is BaseAddr+ImageByte-2. Burst byte; and the like, until all Burst data of each line of complete infrared image data are written into an external memory; imageByte is the size of the original infrared image data. The data writing process is from bottom to top.
In the present invention, the external memory may be DDRRAM. Of course, other external memories are also possible.
In addition, the invention also provides a device for mirroring the infrared image based on the FPGA, which comprises an A/D conversion unit, the FPGA, an external memory and a CPU, wherein the CPU is respectively in communication connection with the FPGA and the external memory, and the A/D conversion unit, the FPGA, the external memory and the CPU can jointly realize the image mirroring method based on the FPGA; the CPU sends a mirror image operation instruction to the FPGA, the read-write address control unit of the FPGA performs line buffering and line processing on the original infrared image data sent by the A/D conversion unit, the AXI bus control unit stores the mirror image processed infrared image data to the external memory, and the CPU or the FPGA directly calls the mirror image processed infrared image data stored in the external memory for the subsequent processing of the image.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (10)
1. An infrared image mirroring method based on FPGA is characterized in that: the device comprises an A/D conversion unit, an FPGA, an external memory and a CPU, wherein the A/D conversion unit performs A/D conversion on an acquired original infrared image; after mirror image processing is carried out on the original infrared image data after the A/D conversion in the FPGA, the original infrared image data after mirror image processing is sent to an external memory for storage through a data bus of the FPGA; the CPU interacts with the FPGA to determine the operation type of the FPGA for mirroring the original infrared image data;
the method for mirroring the image by the FPGA comprises the following steps of;
s1: the method comprises the steps that collected original infrared image data are sequentially sent to an input port of an FPGA from top to bottom according to the sequence of image rows after being processed by an A/D conversion unit in a digital format;
s2: a first intra-chip cache unit BlockRAM0, a second intra-chip cache unit BlockRAM1, a read-write address control unit and an AXI bus control unit are configured in a chip of the FPGA, the first intra-chip cache unit BlockRAM0 and the second intra-chip cache unit BlockRAM1 can perform read-write operation at the same time, and the first intra-chip cache unit BlockRAM0 and the second intra-chip cache unit BlockRAM1 are used for constructing ping-pong cache; the bit width pixw of the first intra-chip buffer memory unit BlockRAM0 and the second intra-chip buffer memory unit BlockRAM1 are the same as the pixel width of the original infrared image data, and the depth w of the first intra-chip buffer memory unit BlockRAM0 and the second intra-chip buffer memory unit BlockRAM1 are the same as the line pixel number of the original infrared image; the read-write address control unit distributes addresses in the table tennis buffer and performs read-write operation; the read-write address control unit is also connected with the AXI bus control unit in a signal way, and the data read by the read-write address control unit are sent to an external memory for storage through the AXI bus control unit;
s3: the read-write address control unit of the FPGA writes the received original infrared image data of the first row into the first in-chip buffer memory unit BlockRAM0 from left to right, and the address written into the first in-chip buffer memory unit BlockRAM0 is increased from 0 to w-1 until the original infrared image data of the first row is completely written; then the read-write address control unit writes the received original infrared image data of the second line into a second on-chip buffer memory unit BlockRAM1 according to the left-to-right sequence, and the address written into the second on-chip buffer memory unit BlockRAM1 is increased according to 0 to w-1 until the original infrared image data of the second line is written; then the read-write address control unit writes the received original infrared image data of the third row into the first in-chip buffer memory unit Block RAM0 according to the left-to-right sequence, and so on, alternately writes the data of the original infrared image data of each row into the ping-pong buffer memory until the data of all rows of the original infrared image data are written into the ping-pong buffer memory;
s4: after each time the ping-pong buffer writes a line of complete original infrared image data, a read-write address control unit of the FPGA processes the line of the complete original infrared image data which is written in the ping-pong buffer last time and reads the address of the ping-pong buffer; according to different mirror image operation types, decomposing the complete infrared image data of each line into a plurality of Burst data, wherein the read-write address control unit reads the ping-pong cache addresses in different modes;
s5: the read-write address control unit of the FPGA executes mirror image write address operation on the whole row of infrared image data after the row processing is finished in the previous step through the AXI bus control unit, and writes each Burst data into an external memory for storage through the AXI bus control unit until the data of all rows of the infrared image are written, so that infrared image data after mirror image processing is obtained; the way in which the entire line of infrared image data is written into the external memory differs according to the type of mirror operation.
2. A method for mirroring an FPGA-based infrared image according to claim 1, wherein: when the mirror image operation type is an original image, the FPGA performs row processing on the original infrared image data, namely a read-write address control unit reads data in each address of a first in-chip buffer memory unit BlockRAM0 or a second in-chip buffer memory unit BlockRAM1 according to the ascending order of addresses 0 to w-1 until the reading of the whole row of original infrared image data is completed; blockraddr=i, i= {0,1,2, … w-2,w-1}, blockRaddr is a read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is a sequential count of the read original infrared image data.
3. A method for mirroring an FPGA-based infrared image according to claim 2, wherein: when the mirror image operation type is an original image, executing mirror image write address operation, namely writing each Burst data of each line of complete infrared image data into an external memory sequentially from top to bottom according to the increasing sequence of the read address; the write address offset starts from 0, the base address of the external memory locates BaseAddr, the AXI bus control unit writes the bus address DDRWaddr=BaseAddr of the first Burst data, and the number of bytes written by one Burst data is Burst; the bus address of the AXI bus control unit for writing adjacent Burst data is increased by Burst byte, namely the writing address of the current AXI bus control unit is BaseAddr+burst byte; and the like until all the Burst data of each complete line of infrared image data are written into the external memory.
4. A method for mirroring an FPGA-based infrared image according to claim 2, wherein: when the mirror image operation type is horizontal mirror image, the FPGA performs row processing on the original infrared image data, namely a read-write address control unit reads data in each address of a first in-chip buffer memory unit BlockRAM0 or a second in-chip buffer memory unit BlockRAM1 according to descending order of addresses w-1 to 0 until the reading of the whole row of original infrared image data is completed; blockraddr=w-1-i, i= {0,1,2, … w-2,w-1}, blockRaddr is a read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is a sequential count of the read original infrared image data.
5. The method for mirroring an FPGA-based infrared image according to claim 4, wherein: when the mirror image operation type is horizontal mirror image, executing mirror image write address operation, namely writing each Burst data of each line of complete infrared image data into an external memory sequentially from top to bottom according to the descending order of read addresses; the write address offset starts from 0, the base address of the external memory is defined as BaseAddr, the bus address DDRWaddr=BaseAddr of the first Burst data written by the AXI bus control unit, and the byte number written by one Burst data is Burst byte; the bus address of the AXI bus control unit for writing adjacent Burst data is increased by Burst byte, namely the current bus writing address is BaseAddr+burst byte; and the like until all the Burst data of each complete line of infrared image data are written into the external memory.
6. A method for mirroring an FPGA-based infrared image according to claim 2, wherein: when the mirror image operation type is vertical mirror image, the FPGA processes the row of original infrared image data, namely, the first Burst data at the tail end of the row of original infrared image data is used as initial read data of a read-write address control unit, the Burst data is read to the direction of a low-order address according to the last address of the Burst data, and after the current Burst data is read, one Burst data adjacent to the row of original infrared image data is read; until the reading of the whole line of original infrared image data is completed;
blockraddr=w-1- ((i &0xffc 0) | (63- (i &0x3 f))), i= {0,1,2, … w-2,w-1}, where BlockRaddr is the read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is the sequential count of the read original infrared image data.
7. A method for mirroring an FPGA-based infrared image according to claim 2, wherein: when the mirror image operation type is diagonal mirror image, the FPGA processes the row of original infrared image data, namely, the first Burst data at the head end of the row of original infrared image data is used as initial read data of a read-write address control unit, the Burst data is read to the direction of a low-order address according to the last address of the Burst data, and after the current Burst data is read, the adjacent Burst data of the row of original infrared image data is read; until the reading of the whole line of original infrared image data is completed;
blockraddr= ((i &0xffc 0) | (63- (i &0x3 f))), i= {0,1,2, … w-2,w-1}, where BlockRaddr is the read address of the first intra-chip buffer unit BlockRAM0 or the second intra-chip buffer unit BlockRAM1, and i is the sequential count of the read original infrared image data.
8. A method for mirroring an FPGA-based infrared image according to claim 6 or 7, wherein: when the mirror operation type is vertical mirror or diagonal mirror, executing mirror address writing operation, namely writing each Burst data of the infrared image data with each complete line into an external memory from bottom to top in descending order of addresses; the write address offset starts from the base address, the base address of the external memory is defined as BaseAddr, the bus address of the first Burst data written by the AXI bus control unit is DDRWaddr=BaseAddr+ImageByte-Burst byte, and the number of bytes written by one Burst data is Burst byte; then the bus of the AXI bus control unit for writing adjacent Burst data decrements the address by Burst byte, namely the current bus writing address is BaseAddr+ImageByte-2. Burst byte; and the like, until all Burst data of each line of complete infrared image data are written into an external memory; imageByte is the size of the original infrared image data.
9. A method for mirroring an FPGA-based infrared image according to claim 1, wherein: the external memory is a DDRRAM.
10. An apparatus for mirroring an infrared image based on an FPGA, characterized in that: the mirror image method of any one of claims 1-9 can be realized by the aid of the A/D conversion unit, the FPGA, the external memory and the CPU; the CPU sends a mirror image operation instruction to the FPGA, the read-write address control unit of the FPGA performs line buffering and line processing on the original infrared image data sent by the A/D conversion unit, the AXI bus control unit stores the mirror image processed infrared image data to the external memory, and the CPU and the FPGA directly call the mirror image processed infrared image data stored in the external memory for the subsequent processing of the image.
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