CN113658049A - Image transposition method, equipment and computer readable storage medium - Google Patents
Image transposition method, equipment and computer readable storage medium Download PDFInfo
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Abstract
The method comprises the steps of sequentially and respectively writing pixel points with the number of the set pixel points in an image to be transposed into in-chip storage areas correspondingly arranged by the column number of each pixel point according to the sequence from high to low of the row number of the pixel points, sequentially and respectively writing each pixel point in each column in each in-chip storage area into a display after the transposition according to the sequence from low to high of the column number of the pixel points, and thus, the bandwidth utilization rate can be improved when the image transposition is carried out.
Description
Technical Field
The present application relates to the field of image processing, and in particular, to a method, apparatus, and computer-readable storage medium for image transposing.
Background
In order to facilitate information dissemination, the same image information generally needs to be displayed on different devices, and because the display sizes of different devices are different, when the same image information is transmitted and displayed on different devices, images generally need to be transposed, for example, a 1920 × 1080 landscape screen image is converted into a 1080 × 1920 portrait screen image.
In the prior art, an image is generally transposed by combining a Field Programmable Gate Array (FPGA) and an off-chip Dynamic Memory (DRAM).
However, in this way, the bandwidth utilization rate of image transposition is low.
Therefore, how to improve the bandwidth utilization rate when performing image transposition is a problem to be solved.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method, an apparatus, and a computer-readable storage medium for image transposing, so as to improve bandwidth utilization rate when performing image transposing.
In a first aspect, an embodiment of the present application provides a method for image transposing, where the method includes:
and sequentially and respectively writing the pixels with the set pixel number in the image to be transposed into the in-chip storage area corresponding to the column serial number of each pixel according to the sequence from high to low of the row serial numbers of the pixels.
And sequentially and respectively transferring all the pixel points in each row in each in-chip storage area according to the sequence of the row serial numbers of the pixel points from low to high, and writing the transposed pixel points into the display.
In the implementation process, the pixels with the preset number of the pixels are sequentially written into the in-chip storage area of the image to be transposed according to the sequence of the row sequence numbers of the pixels from high to low, so that the image to be transposed is stored in the in-chip storage area, the bandwidth utilization rate in the image transposition process can be improved by sequentially reading the pixels, and the pixels in the in-chip storage area are further transposed and then written into the display, so that the display of the image to be transposed is realized.
With reference to the first aspect, in an implementation manner, before sequentially and respectively writing the pixels with the set number of pixels in the image to be transposed into the in-chip storage area corresponding to the column number of each pixel, the method further includes:
when at least one free buffer area exists in a first buffer area in the off-chip memory and a second buffer area in the off-chip memory, each video frame of the input video is written into each determined free buffer area in sequence.
And when determining that the first cache region and the second cache region have non-idle cache regions, determining the video frames in the non-idle cache regions as the images to be transposed.
The idle buffer area is a buffer area which does not store video frames or a buffer area which stores video frames and is written into the in-chip storage area; the non-idle buffer area is a buffer area in which the stored video frames are not written into the on-chip storage area.
In the implementation process, the hollow buffer area of the off-chip memory is determined, and each video frame of the input video is sequentially written into the hollow buffer area, so that the video frame is stored into the buffer area in a ping-pong operation mode, and the bandwidth utilization rate is further improved.
With reference to the first aspect, in an implementation manner, writing in an in-chip storage area corresponding to a column sequence number of each pixel point includes:
and if the column serial number of each pixel point accords with a preset division range, writing each pixel point into a first in-chip storage area in the in-chip storage areas, wherein the preset division range is determined according to the number of the set pixel points.
Otherwise, writing each pixel point into a second on-chip storage area in the on-chip storage areas.
In the implementation process, the pixel points corresponding to the set pixel point number are respectively and sequentially stored in the first in-chip storage area and the first in-chip storage area in the in-chip storage areas, and the storage positions of the in-chip storage areas are utilized to the maximum extent, so that the bandwidth utilization rate is improved.
With reference to the first aspect, in an implementation manner, the number of the set pixels is determined according to a bit depth of the image to be transposed, a bit width of the off-chip memory, and a burst length.
In the implementation process, the number of the set pixel points is determined according to the bit depth of the image to be transposed, the bit width of the off-chip memory and the burst length, so that when data in the cache region is read, the data of a plurality of pixel points can be read as many as possible at one time, and the bandwidth utilization rate is improved.
In a second aspect, an embodiment of the present application provides an apparatus for image transposing, where the apparatus includes:
and the image writing module is used for sequentially and respectively writing the pixel points with the set pixel point number in the image to be transposed into the in-chip storage area corresponding to the column serial number of each pixel point according to the sequence from high to low of the row serial numbers of the pixel points.
And the image transposition module is used for sequentially and respectively writing the pixel points in each row in each in-chip storage area into the display after transposition according to the sequence of the row serial numbers of the pixel points from low to high.
With reference to the second aspect, in an embodiment, the image writing module is further configured to:
when at least one free buffer area exists in a first buffer area in the off-chip memory and a second buffer area in the off-chip memory, each video frame of the input video is written into each determined free buffer area in sequence.
And when determining that the first cache region and the second cache region have non-idle cache regions, determining the video frames in the non-idle cache regions as the images to be transposed.
The idle buffer area is a buffer area which does not store video frames or a buffer area which stores video frames and is written into the in-chip storage area; the non-idle buffer area is a buffer area in which the stored video frames are not written into the on-chip storage area.
With reference to the second aspect, in an embodiment, the on-chip storage area where the column sequence number of each pixel point is correspondingly set includes:
the on-chip storage area that the column sequence number of each pixel corresponds the setting includes:
and if the column serial number of each pixel point accords with a preset division range, writing each pixel point into a first in-chip storage area in the in-chip storage areas, wherein the preset division range is determined according to the number of the set pixel points.
Otherwise, writing each pixel point into a second on-chip storage area in the on-chip storage areas.
With reference to the second aspect, in an embodiment, the number of the set pixels is determined according to a bit depth of the image to be transposed, a bit width of the off-chip memory, and a burst length.
In a third aspect, an embodiment of the present application provides an apparatus for image transposing, including:
the system comprises a processor, a memory and a bus, wherein the processor is connected with the memory through the bus, and the memory stores computer readable instructions for implementing the steps of the method provided by any one of the embodiments of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps in the method as provided in any one of the implementation manners of the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a flowchart of a method for image transposing according to an embodiment of the present disclosure;
fig. 2 is a diagram of an embodiment of image transposing according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a horizontal screen image data writing method according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating that image data is stored in a first buffer area according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating that image data is stored in a second buffer according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a writing method of vertical screen image data according to an embodiment of the present disclosure;
fig. 7 is a block diagram of an apparatus for image transposing according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of another image transposing apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
First, some terms referred to in the embodiments of the present application will be described to facilitate understanding by those skilled in the art.
With the continuous development of science and technology, various video information or picture information generally needs to be displayed on different terminal devices, for example, the video information needs to be adapted to different devices in the process of obtaining and displaying, a video image shot or monitored by a camera or a monitor generally has more horizontal pixels than vertical pixels, i.e., a landscape screen image, and a video image adapted to a display terminal screen of the video image generally has less horizontal pixels than vertical pixels, i.e., a portrait screen image, and therefore, in order to display a captured landscape screen image on a display terminal, the landscape screen image needs to be converted into a portrait screen image.
In the prior art, an FPGA and an off-chip dynamic memory (DRAM) are usually combined to transpose an image, and a standard DRAM read-write needs to convert a logical layer control command into a physical layer control command, and with this method, the bandwidth utilization rate of image transposition is low, and in order to improve the bandwidth utilization rate in the image transposition process, a related technician usually compresses an image data format, and after the transposition is completed, converts the image data format back to the original format, for example, the image data format is compressed from 4:4:4 to 4:2:2, and after the transposition, the image data format is converted back to 4:4:4, and in this process, image data processing needs to be performed twice, which inevitably results in image quality loss.
Therefore, the present application provides a method, an apparatus, and a computer-readable storage medium for image transposition, which improve the bandwidth utilization rate in the image transposition process without affecting the image quality during the image transposition.
In the embodiment of the present application, only the monitor is taken as a horizontal screen and the display terminal is taken as a vertical screen for illustration, but in practical applications, the monitor may also be taken as a vertical screen and the display terminal is taken as a horizontal screen, but the present application is not limited thereto.
In this embodiment of the present application, the execution main body may be an apparatus for image transposing, and optionally, the apparatus for image transposing may be a processor or a memory, but the present application is not limited thereto.
Referring to fig. 1, fig. 1 is a flowchart of an image transposing method according to an embodiment of the present disclosure. As an example, the specific implementation flow of the method shown in fig. 1 is as follows:
step 101: and sequentially and respectively writing the pixels with the set pixel number in the image to be transposed into the in-chip storage area corresponding to the column serial number of each pixel according to the sequence from high to low of the row serial numbers of the pixels.
As an embodiment, before performing step 101, the input video frame image may also be determined as an image to be transposed, specifically, the following steps may be performed to determine the image to be transposed:
s1011: when at least one free buffer area exists in a first buffer area in the off-chip memory and a second buffer area in the off-chip memory, each video frame of the input video is written into each determined free buffer area in sequence.
S1012: and when determining that the first cache region and the second cache region have non-idle cache regions, determining the video frames in the non-idle cache regions as the images to be transposed.
The idle buffer area is a buffer area which does not store video frames or a buffer area which stores video frames and is written into the in-chip storage area; the non-idle buffer area is a buffer area in which the stored video frames are not written into the on-chip storage area.
As shown in fig. 2, fig. 2 is a diagram of an image transpose implementation provided in an embodiment of the present application, in the image transpose implementation shown in fig. 2, two memories are used, one is an off-chip dynamic Memory 203, and the other is a Static Random-Access Memory (SRAM) 2022 based on an FPGA202, and both the two memories are used for storing data in an image transpose process.
As an embodiment, the off-chip dynamic memory 203 is a third generation double data rate synchronous dynamic memory (DDR3), and is divided into a first buffer 2031 and a second buffer 2032 according to DDR3 addresses.
It should be noted that, in the embodiment of the present application, only DDR3 is taken as an example to illustrate the off-chip dynamic memory 203, and in an actual application process, the off-chip dynamic memory 203 may also be a second generation double data rate synchronous dynamic memory (DDR2), or a fourth generation double data rate synchronous dynamic memory (DDR4), which may be other types of memories, which is not limited herein.
Further, when it is determined that there are free buffer areas in the first buffer area 2031 and the second buffer area 2032 in the off-chip dynamic memory 203 after the landscape data 201 entered by the monitor is input into the video landscape data 2021, the video landscape data 2021 is sequentially written into the free buffer areas frame by frame, and each buffer area stores one frame of video landscape data.
As an example, in the video raster data 2021, each frame of raster image is an n × m (n > m) raster image, where n represents the number of pixels in the image row direction and m represents the number of pixels in the image column direction.
Specifically, each frame of horizontal screen image is 1920 × 1080, that is, 1920 pixels in the row direction and 1080 pixels in the column direction of each frame of image are present. The method for writing each frame of horizontal screen image in the video horizontal screen data into the off-chip dynamic memory may be as shown in fig. 3, where fig. 3 is a schematic diagram of a horizontal screen image data writing method provided in an embodiment of the present application, and in fig. 3, the serial numbers of the columns gradually increase from left to right in the row direction, and the serial numbers of the rows gradually increase from top to bottom in the column direction. If the current line address of the image scanning is the first line, the next line address is the second line, that is, the scanning sequence of the image is from the left to the right from the first pixel (1,1) of the first line to (1,1920) and then from the left to the right from the first pixel (2,1) of the second line to the scanning of the frame image.
As an embodiment, if the image to be transposed is 1920 × 1080, the image format is rgb4:4:4, the bit depth is 8bit, i.e. rgb is 8bit, and the data of one pixel point is 24 bit. One piece of DDR3 has a data bit width of 16 bits, and one burst length is 8, so that data written at one time is 16 × 8-128 bits at most. One pixel point 24bit, 24 x 5 equals 120 bits, and 5 pixel points can be write to a burst length, and this application takes write 128 burst lengths once as an example, and 128 x 5 equals 640, is about to when horizontal screen image data write DDR3, once can write 640 pixel points. And a row of 1920 pixels is needed to be written into the DDR3 only three times.
Further, an image data writing instruction is sent to the DDR3 through the physical layer interface, and horizontal screen image data in the video horizontal screen data are sequentially written into empty buffer areas frame by frame according to the scanning sequence of fig. 3, if the first buffer area and the second buffer area are both empty buffer areas, the first frame of horizontal screen image data is written into the first buffer area in the video horizontal screen data, the second frame of horizontal screen image data is written into the second buffer area, and each buffer area stores one frame of horizontal screen image data.
After storing the horizontal screen image data into the buffer areas, sequentially determining the horizontal screen image in each non-idle buffer area as an image to be transposed according to the sequence of the video frames.
In the implementation process, the hollow buffer area of the off-chip memory is determined, and each video frame of the input video is sequentially written into the hollow buffer area, so that the video frame is stored into the buffer area in a ping-pong operation mode, and the bandwidth utilization rate is further improved.
Further, step 101 is executed to write the image to be transposed into the on-chip storage area.
The number of the set pixel points is determined according to the bit depth of the image to be transposed, the bit width of the off-chip memory and the burst length.
It should be noted that the Burst refers to a manner in which data transfer is continuously performed between adjacent memory cells in the same row, and the number of consecutive transfer cycles is a Burst Length (BL).
As an embodiment, if the image to be transposed is 1920 × 1080, the image format is rgb4:4:4, the bit depth is 8bit, that is, rgb is 8bit, a piece of DDR3 has a data bit width of 16bit, and a burst length is 8, the number of set pixels is determined according to the bit depth of the image to be transposed, the bit width of an off-chip memory, and the burst length, and the number of the set pixels is the number of pixels that are read from a buffer at least at each time.
In the embodiment of the present application, the example that the burst length of the DDR3 is 8 is described, but in practical applications, the burst length may be set as needed, and is not limited herein.
Specifically, if one rgb is an 8-bit image, the data of one pixel point is 24 bits.
One piece of DDR3 has a data bit width of 16 bits, and one burst length is 8, so that data written at one time is 16 × 8-128 bits at most. That is to say, one piece of DDR3 can write 128 bits at most for one burst length, one piece of DDR3 can write 128 ÷ 24 ═ 5.33 pixels at most for one burst length, and the number of pixels is an integer, that is, 5 pixels can be written in at most for one burst length of one piece of DDR3, and therefore, the number of pixels is set to 5.
Specifically, when step 101 is executed, the in-chip storage area correspondingly set by the column sequence number of each pixel point may be written in by the following manner: if the column serial number of each pixel point accords with a preset division range, writing each pixel point into a first in-chip storage area in the in-chip storage areas, wherein the preset division range is determined according to the number of the set pixel points; otherwise, writing each pixel point into a second on-chip storage area in the on-chip storage areas.
As an embodiment, the preset partition range is a range of column sequence numbers corresponding to each group of sequence numbers in the first sequence number set determined according to the number of the set pixel points.
The method comprises the steps of sequentially dividing the row sequence numbers of the image to be transposed into a plurality of sequence number sets according to the number of set pixel points, wherein each sequence number set comprises the row sequence numbers of the set number.
The method comprises the steps of sequentially numbering a plurality of column sequence number sets, and dividing the plurality of column sequence number sets into a first sequence number set and a second sequence number set according to the numbers, wherein the first sequence number set comprises a column sequence number set with an odd number, and the second sequence number set comprises a column sequence number set with an even number.
Specifically, in the row direction of the image to be transposed, the column sequence numbers are divided into a column sequence number set by taking 5 as a boundary, and each column sequence number set corresponds to a sequence number range, so that the image to be transposed can obtain 1920 ÷ 5 ═ 384 column sequence number sets.
Furthermore, each column sequence number set is numbered in sequence, the column sequence number sets with odd numbers are divided into a first sequence number set, each column sequence number set in the first sequence number set corresponds to a sequence number range, and the column sequence number sets with even numbers are divided into a second sequence number set.
And dividing the on-chip memory into a first on-chip memory area and a second on-chip memory area, wherein the first on-chip memory area is used for storing corresponding pixel points in the first sequence number set, and the second on-chip memory area is used for storing corresponding pixel points in the second sequence number set.
Further, the on-chip static memory SRAM is divided into a first on-chip storage area and a second on-chip storage area, a reading instruction is sent to the DDR3 through the physical layer interface, the image to be transposed is written into the on-chip static memory SRAM, corresponding pixel points in the first sequence number set are stored in the first on-chip storage area, and corresponding pixel points in the second sequence number set are stored in the second on-chip storage area in a ping-pong operation mode.
The ping-pong operation means that the buffered data stream is seamlessly (i.e., without time delay) sent to the data stream operation processing module for processing by switching the input data stream selection unit and the output data stream selection unit in a manner of matching with each other in terms of beats.
When a data frame synchronization command is detected, writing the image data of the frame into the DDR3 through the physical layer interface into the first buffer area, further writing the image data in the first buffer area into the first in-chip storage area, and simultaneously writing the next frame data into the second buffer area.
And writing the data of the second buffer area in the DDR3 into the second in-chip storage area, writing 5-10 columns of pixel point data into the second in-chip storage area, and simultaneously writing the image data of the first in-chip storage area into the display until the frame image is completely displayed.
Through two ping-pong operations of the on-chip memory and the off-chip memory, the video image of n multiplied by m is transposed into an image of m multiplied by n vertical screen, and the image is displayed on the vertical screen.
Specifically, according to the sequence from high to low of the row sequence numbers of the pixel points, the pixel points with the set pixel point number in the image to be transposed are sequentially and respectively written into the in-chip storage area corresponding to the column sequence number of each pixel point.
If the image to be transposed is a first frame of horizontal screen image, scanning 5 pixel points from left to right of the image to be transposed, scanning the second last line, namely, starting from the first pixel point (1080,1) in the 1080 th line to the left to the right, ending at the fifth pixel point (1080,5) in the 1080 th line, scanning the first pixel point (1079,1) in the 1079 th line to the left to the right, ending at the fifth pixel point (1079,5) in the 1079 th line, ending at the fifth pixel point (1,5) in the first line of the image to be transposed, obtaining each pixel point corresponding to the first group of row sequence numbers in the first sequence number set, and writing each pixel point obtained by scanning into the first in-chip storage area according to the scanning sequence.
In the process, the first frame of horizontal screen image data is written into the first in-chip storage area, and simultaneously, the second frame of horizontal screen image data is written into the second buffer area in a horizontal screen image writing mode, so that the ping-pong operation of storing the video frame image is realized.
In the implementation process, the video frame data cache region is written into the in-chip storage region in a ping-pong operation mode, and when the cache region is written into the in-chip storage region, the data of 5 continuous pixel points are read each time, so that a plurality of pixel points can be read simultaneously during the process of image transposition, and the bandwidth utilization rate is improved.
Fig. 4 is a schematic diagram of storing image data in a first cache region according to an embodiment of the present application, in the above process, a result obtained after each pixel point corresponding to a first group of column sequence numbers of an image to be transposed is stored in a first in-chip storage region, as shown in fig. 4, a row sequence number of each pixel point in the first cache region is opposite to a row sequence number of the image to be transposed, and a column sequence number of each pixel point in the first cache region is the same as a column sequence number of the image to be transposed.
Further, writing each pixel point corresponding to the second group of serial numbers into the second in-chip storage area according to the writing mode of each pixel point corresponding to the first group of serial numbers, and simultaneously, writing each pixel point in the first cache area into the display after being transferred according to a ping-pong operation mode.
Fig. 5 is a schematic diagram of storing image data in a second cache region according to an embodiment of the present application, where in the foregoing process, a result of storing each pixel point corresponding to a second group of column sequence numbers of an image to be transposed in a second intra-chip storage region is shown in fig. 5.
Specifically, step 102 is executed in the method of transposing each pixel point in the first cache area and writing the transposed pixel point into the display.
In the implementation process, the DRAM is directly controlled through a physical layer interface in a mode of stripping off the DRAM control logic layer interface. Therefore, DRAM control commands can be flexibly and tightly sent continuously, the bandwidth is utilized to the maximum extent, the bandwidth utilization rate is improved, the read-write of DDR3 is controlled directly through an interface of a physical layer, the read-write commands of DDR3 are tightly arranged, the process of reading data is completed, the SRAM in an FPGA chip with a small amount of use is used up, the data read out from the DDR3 are cached, and the equipment cost of image transposition is saved.
Step 102: and sequentially and respectively transferring all the pixel points in each row in each in-chip storage area according to the sequence of the row serial numbers of the pixel points from low to high, and writing the transposed pixel points into the display.
As an embodiment, each pixel point in each in-chip storage area is written into the display by column unit from bottom to top and from left to right, fig. 6 is a schematic diagram of a vertical screen image data writing method provided by the embodiment of the present application, as shown in fig. 6, taking the first in-chip storage area as an example, the scanning sequence is that the current column address is the first column, the next column address is the second column, that is, the scanning sequence starts from the last row of the pixel points (1,1) of the first column from bottom to top, ends to the first row of the pixel points (1080,1) of the first column, scans the last row of the pixel points (1,2) of the second column from bottom to top, ends to the last row of the second column (1080,2), until all the pixel points corresponding to each column in the first in-chip storage area are scanned, and after all the pixel points of each column are scanned, the scanning sequence is written into the row direction of the display, finally, the first 5 rows of data after the image to be transposed is transposed can be displayed on the display.
Furthermore, the data in the second in-chip storage area is written into the 6 th to 10 th rows of the display in a manner that the data in the first in-chip storage area is written into the display, and simultaneously, the pixel points corresponding to the third group of column sequence numbers in the first cache area are written into the first in-chip storage area according to the writing manner of the pixel points corresponding to the first group of column sequence numbers, so as to realize the ping-pong operation of reading the data in the cache area.
In the implementation process, the pixels with the preset number of pixels are sequentially written into the in-chip storage area of the image to be transposed from high to low according to the sequence of the row sequence numbers of the pixels, so that the image to be transposed is stored in the in-chip storage area, the bandwidth utilization rate in the image transposition process can be improved by sequentially reading a plurality of pixels, each pixel in the in-chip storage area is further transposed and written into a display, the display after the image to be transposed is realized, the video data is not required to be compressed, the data processing is carried out under the condition of rgb4:4:4, the video precision is retained to the maximum extent, and no additional data loss exists.
Referring to fig. 7, fig. 7 is a block diagram of an apparatus for image transposing according to an embodiment of the present application, where the apparatus 700 includes:
the image writing module 701 is configured to sequentially and respectively write the pixel points with the set number of the pixel points in the image to be transposed into the in-chip storage areas corresponding to the column number of each pixel point according to a sequence from high to low of the row number of the pixel points.
The image transposing module 702 is configured to sequentially and respectively transpose each pixel point in each row in each in-chip storage area according to a sequence of the row number of the pixel point from low to high, and then write the transposed pixel point into the display.
In one embodiment, the image writing module 701 is further configured to:
when at least one free buffer area exists in a first buffer area in the off-chip memory and a second buffer area in the off-chip memory, each video frame of the input video is written into each determined free buffer area in sequence.
And when determining that the first cache region and the second cache region have non-idle cache regions, determining the video frames in the non-idle cache regions as the images to be transposed.
The idle buffer area is a buffer area which does not store video frames or a buffer area which stores video frames and is written into the in-chip storage area; the non-idle buffer area is a buffer area in which the stored video frames are not written into the on-chip storage area.
In one embodiment, the on-chip storage area in which the column sequence number of each pixel point is correspondingly set includes:
the on-chip storage area that the column sequence number of each pixel corresponds the setting includes:
and if the column serial number of each pixel point accords with a preset division range, writing each pixel point into a first in-chip storage area in the in-chip storage areas, wherein the preset division range is determined according to the number of the set pixel points.
Otherwise, writing each pixel point into a second on-chip storage area in the on-chip storage areas.
In one embodiment, the number of pixels to be set is determined according to the bit depth of the image to be transposed, the bit width of the off-chip memory, and the burst length.
It should be noted that the apparatus 700 shown in fig. 7 can implement the processes of the method in the embodiment of the method in fig. 1. The operations and/or functions of the respective units in the device 700 are respectively for implementing the corresponding flows in the method embodiment in fig. 1. Reference may be made specifically to the description of the above method embodiments, and a detailed description is appropriately omitted herein to avoid redundancy.
Referring to fig. 8, fig. 8 is a schematic structural diagram of another image transposing apparatus according to an embodiment of the present application, and the image transposing apparatus 800 shown in fig. 8 may include: a processor 810, a memory 820 and a bus 830, wherein the processor is connected to the memory through the bus, the memory stores computer readable instructions, and when the computer readable instructions are executed by the processor, the method is implemented in any of the above embodiments.
Wherein the bus is used for realizing direct connection communication of the components. The processor in the embodiment of the present application may be an integrated circuit chip having signal processing capability. The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The Memory may be, but is not limited to, an off-chip Dynamic Memory (DRAM), a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like. The memory stores computer readable instructions that, when executed by the processor, perform the methods described in the embodiments above.
It will be appreciated that the configuration shown in fig. 8 is merely illustrative and may include more or fewer components than shown in fig. 8 or have a different configuration than shown in fig. 8. The components shown in fig. 8 may be implemented in hardware, software, or a combination thereof.
An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the method process shown in fig. 1.
In the several embodiments provided in the present application, it should be understood that the disclosed system and method may be implemented in other ways. The above-described system embodiments are merely illustrative, and for example, the division of the system apparatus into only one logical functional division may be implemented in other ways, and for example, a plurality of apparatuses or components may be combined or integrated into another system, or some features may be omitted, or not implemented.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method of image transposition, the method comprising:
sequentially and respectively writing the pixel points with the set pixel point number in the image to be transposed into an in-chip storage area correspondingly set by the column serial number of each pixel point according to the sequence from high to low of the row serial numbers of the pixel points;
and sequentially and respectively transferring all the pixel points in each row in each in-chip storage area according to the sequence of the row serial numbers of the pixel points from low to high, and writing the transposed pixel points into the display.
2. The method according to claim 1, wherein before sequentially and respectively writing the pixels with the set number of pixels in the image to be transposed into the on-chip storage area corresponding to the column number of each pixel, the method further comprises:
when at least one idle cache area exists in a first cache area in an off-chip memory and a second cache area in the off-chip memory, respectively writing each video frame of an input video into each determined idle cache area in sequence;
when determining that a non-idle cache region exists in the first cache region and the second cache region, determining a video frame in the non-idle cache region as the image to be transposed;
the idle buffer area is a buffer area which does not store video frames or a buffer area which stores video frames and is written into an on-chip storage area; the non-idle buffer area is a buffer area in which the stored video frames are not written into the on-chip storage area.
3. The method according to claim 1 or 2, wherein the writing of the on-chip storage area corresponding to the column sequence number of each pixel point comprises:
if the column serial number of each pixel point accords with a preset division range, writing each pixel point into a first in-chip storage area in the in-chip storage areas, wherein the preset division range is determined according to the number of the set pixel points;
otherwise, writing each pixel point into a second on-chip storage area in the on-chip storage areas.
4. The method according to claim 1 or 2, wherein the number of the set pixels is determined according to a bit depth of the image to be transposed, a bit width of the off-chip memory, and a burst length.
5. An apparatus for image transposition, characterized in that the apparatus comprises:
the image writing module is used for sequentially and respectively writing the pixel points with the set pixel point number in the image to be transposed into the in-chip storage area correspondingly arranged by the column serial numbers of the pixel points according to the sequence from high to low of the row serial numbers of the pixel points;
and the image transposition module is used for sequentially and respectively writing the pixel points in each row in each in-chip storage area into the display after transposition according to the sequence of the row serial numbers of the pixel points from low to high.
6. The device of claim 5, wherein the image writing module is further configured to:
when at least one idle cache area exists in a first cache area in an off-chip memory and a second cache area in the off-chip memory, respectively writing each video frame of an input video into each determined idle cache area in sequence;
when determining that a non-idle cache region exists in the first cache region and the second cache region, determining a video frame in the non-idle cache region as the image to be transposed;
the idle buffer area is a buffer area which does not store video frames or a buffer area which stores video frames and is written into an on-chip storage area; the non-idle buffer area is a buffer area in which the stored video frames are not written into the on-chip storage area.
7. The apparatus according to claim 5 or 6, wherein the on-chip storage area corresponding to the column sequence number of each pixel point comprises:
if the column serial number of each pixel point accords with a preset division range, writing each pixel point into a first in-chip storage area in the in-chip storage areas, wherein the preset division range is determined according to the number of the set pixel points;
otherwise, writing each pixel point into a second on-chip storage area in the on-chip storage areas.
8. The apparatus according to claim 5 or 6, wherein the number of pixels is determined according to a bit depth of the image to be transposed, a bit width of the off-chip memory, and a burst length.
9. An apparatus for image transposition, comprising:
a processor, a memory, and a bus, the processor being connected to the memory through the bus, the memory storing computer readable instructions for implementing the method of any one of claims 1-4 when the computer readable instructions are executed by the processor.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the method according to any one of claims 1 to 4.
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