CN111684694A

CN111684694A - Drive circuit and switching power supply

Info

Publication number: CN111684694A
Application number: CN201880087346.6A
Authority: CN
Inventors: 刘一
Original assignee: Shenzhen A&E Intelligent Technology Institute Co Ltd
Current assignee: Shenzhen A&E Intelligent Technology Institute Co Ltd
Priority date: 2018-10-29
Filing date: 2018-10-29
Publication date: 2020-09-18
Also published as: WO2020087224A1

Abstract

A driving circuit and a switching power supply are provided. The driving circuit (10) at least comprises a control chip (11), a first driving chip (U1), a second driving chip (U2), a third driving chip (U3), a fourth driving chip (U4), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a first transformer (14) and a second transformer (15), wherein the first driving chip (U1) is coupled with a first input end of the first transformer (14), the second driving chip (U2) is coupled with a second input end of the first transformer (14), the third driving chip (U3) is coupled with a first input end of the second transformer (15), and the fourth driving chip (U4) is coupled with a second input end of the second transformer (15). The first transformer (14) and the second transformer (15) are used for isolation, namely the driving circuit (10) is coupled with the full-bridge inverter circuit (10) through the first transformer (14) and the second transformer (15), so that the signal transmission delay time is reduced, and high-frequency signals can be transmitted.

Description

Drive circuit and switching power supply

[ technical field ] A method for producing a semiconductor device

The present application relates to the field of power supply technologies, and in particular, to a driving circuit and a switching power supply.

[ background ] of the inventionTechnique (C)

At present, a full-bridge inverter circuit is widely applied, and a plurality of high-power application switching power supplies adopt the circuit structure. The full-bridge circuit has the advantages of high output power, low requirement on voltage resistance of the power switch tube and convenience in selecting the power switch tube.

The driving circuit is used for amplifying the PWM signal output by the control circuit so as to meet the requirement of driving the power switch tube. The performance of the driving circuit is directly related to the switching speed and power consumption of the switching tube, the efficiency and reliability of the whole machine. Wherein, the driving circuit must realize the electric isolation of the control circuit and the grid electrode of the driven switch tube.

In the prior art, the control circuit is electrically isolated from the gate of the driven switching tube by an optocoupler, which includes a light emitting diode and a phototransistor, and the phototransistor is turned on when the light emitting diode emits light. However, the optical coupler has a narrow frequency band and is not suitable for transmitting high-frequency switching signals; furthermore, the optical coupler has a long delay time and thus has a slow response.

[ summary of the invention ]

The technical problem that this application mainly solved provides a drive circuit and switching power supply, can reduce signal transmission delay time to transmit high frequency signal.

In order to solve the technical problem, the application adopts a technical scheme that: providing a driving circuit coupled to a full-bridge inverter circuit, wherein the driving circuit at least comprises a control chip, a first driving chip, a second driving chip, a third driving chip, a fourth driving chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer and a second transformer, the control chip is coupled to the first driving chip, the second driving chip, the third driving chip and the fourth driving chip, a primary coil of the first transformer is coupled to a first secondary coil of the first transformer and a second secondary coil of the first transformer respectively, the first secondary coil of the first transformer comprises a first output end of the first transformer and a second output end of the first transformer, the second secondary coil of the first transformer comprises a third output end of the first transformer and a fourth output end of the first transformer, the primary coil of the first transformer comprises a first input end of the first transformer and a second input end of the first transformer, the first driving chip is coupled with the first input end of the first transformer, and the second driving chip is coupled with the second input end of the first transformer; the primary coil of the second transformer is coupled to a first secondary coil of the second transformer and a second secondary coil of the second transformer respectively, the first secondary coil of the second transformer includes a first output end of the second transformer and a second output end of the second transformer, the second secondary coil of the second transformer includes a third output end of the second transformer and a fourth output end of the second transformer, the primary coil of the second transformer includes a first input end of the second transformer and a second input end of the second transformer, the third driving chip is coupled to the first input end of the second transformer, and the fourth driving chip is coupled to the second input end of the second transformer;

the full-bridge inverter circuit at least comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein a first output end of the first transformer is connected with a grid electrode of the first MOS tube through the first resistor, a source electrode of the first MOS tube is coupled with a second output end of the first transformer and a drain electrode of the second MOS tube, a fourth output end of the first transformer is connected with a grid electrode of the second MOS tube through the second resistor, a source electrode of the second MOS tube is coupled with a third output end of the first transformer, a third output end of the second transformer and a source electrode of the fourth MOS tube, a fourth output end of the second transformer is connected with a grid electrode of the fourth MOS tube through the fourth resistor, a drain electrode of the fourth MOS tube is coupled with a second output end of the second transformer and a source electrode of the third MOS tube, a first output end of the second transformer is connected with a grid electrode of the third MOS tube through the third resistor, the drain electrode of the third MOS tube is coupled with the drain electrode of the first MOS tube; the first input end of the first transformer, the first output end of the first transformer and the third output end of the first transformer are homonymous ends, and the first input end of the second transformer, the first output end of the second transformer and the third output end of the second transformer are homonymous ends.

In order to solve the above technical problem, another technical solution adopted by the present application is: providing a switching power supply, which comprises a driving circuit, wherein the driving circuit is coupled to a full-bridge inverter circuit, the driving circuit at least comprises a control chip, a first driving chip, a second driving chip, a third driving chip, a fourth driving chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer and a second transformer, the control chip is coupled to the first driving chip, the second driving chip, the third driving chip and the fourth driving chip, a primary coil of the first transformer is coupled to a first secondary coil of the first transformer and a second secondary coil of the first transformer respectively, the first secondary coil of the first transformer comprises a first output end of the first transformer and a second output end of the first transformer, the second secondary coil of the first transformer comprises a third output end of the first transformer and a fourth output end of the first transformer, the primary coil of the first transformer comprises a first input end of the first transformer and a second input end of the first transformer, the first driving chip is coupled with the first input end of the first transformer, and the second driving chip is coupled with the second input end of the first transformer; the primary coil of the second transformer is coupled to a first secondary coil of the second transformer and a second secondary coil of the second transformer respectively, the first secondary coil of the second transformer includes a first output end of the second transformer and a second output end of the second transformer, the second secondary coil of the second transformer includes a third output end of the second transformer and a fourth output end of the second transformer, the primary coil of the second transformer includes a first input end of the second transformer and a second input end of the second transformer, the third driving chip is coupled to the first input end of the second transformer, and the fourth driving chip is coupled to the second input end of the second transformer;

The beneficial effect of this application is: different from the prior art, the first driver chip of the present application is coupled to the first input terminal of the first transformer, the second driver chip is coupled to the second input terminal of the first transformer, the third driver chip is coupled to the first input terminal of the second transformer, and the fourth driver chip is coupled to the second input terminal of the second transformer; the first output end of the first transformer is connected with the grid electrode of the first MOS tube through a first resistor, the source electrode of the first MOS tube is coupled with the second output end of the first transformer and the drain electrode of the second MOS tube, the fourth output end of the first transformer is connected with the grid electrode of the second MOS tube through a second resistor, the source electrode of the second MOS tube is coupled with the third output end of the first transformer, the third output end of the second transformer and the source electrode of the fourth MOS tube, the fourth output end of the second transformer is connected with the grid electrode of the fourth MOS tube through a fourth resistor, the drain electrode of the fourth MOS tube is coupled with the second output end of the second transformer and the source electrode of the third MOS tube, the first output end of the second transformer is connected with the grid electrode of the third MOS tube through a third resistor, and the drain electrode of the third MOS tube is coupled with the drain electrode of the first MOS tube, because the driving circuit of the application adopts the first transformer and the second transformer for isolation, namely, the driving circuit is coupled with the full-bridge inverter circuit through the first transformer, the signal transmission delay time is reduced and high frequency signals can be transmitted.

[ description of the drawings ]

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a circuit diagram of a driving circuit of a first embodiment of the present application;

fig. 2 is a circuit diagram of a driving circuit of a second embodiment of the present application;

fig. 3 is a schematic structural diagram of a switching power supply according to a first embodiment of the present application.

[ detailed description ] embodiments

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 is a circuit diagram of a driving circuit according to a first embodiment of the present application. The driving circuit 10 of the present embodiment is coupled to the full-bridge inverter circuit 20, and is configured to drive the MOS transistor of the full-bridge inverter circuit 20.

The driving circuit 10 at least includes a control chip 11, a first driving chip U1, a second driving chip U2, a third driving chip U3, a fourth driving chip U4, a first transformer 14, a second transformer 15, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

The control chip 11 is coupled to the first driving chip U1, the second driving chip U2, the third driving chip U3 and the fourth driving chip U4, wherein the first driving chip U1 may include a first amplifier 121, the second driving chip U2 may include a second amplifier 122, the third driving chip U3 may include a third amplifier 123, and the fourth driving chip U4 may include a fourth amplifier 124; the input terminal of the first amplifier 121 is connected to the first output terminal Q1 of the control chip 11, the input terminal of the second amplifier 122 is connected to the second output terminal Q2 of the control chip 11, the input terminal of the third amplifier 123 is connected to the third output terminal Q3 of the control chip 11, and the input terminal of the fourth amplifier 124 is connected to the fourth output terminal Q4 of the control chip 11.

The primary coil of the first transformer 14 is coupled to a first secondary coil of the first transformer 14 and a second secondary coil of the first transformer 14, respectively, the first secondary coil of the first transformer 14 includes a first output terminal of the first transformer 14 and a second output terminal of the first transformer 14, the second secondary coil of the first transformer 14 includes a third output terminal of the first transformer 14 and a fourth output terminal of the first transformer 14, the primary coil of the first transformer 14 includes a first input terminal of the first transformer 14 and a second input terminal of the first transformer 14, the first driving chip U1 is coupled to the first input terminal of the first transformer 14, the second driving chip U2 is coupled to the second input terminal of the first transformer 14, i.e. the output of the first amplifier 121 is connected to a first input of the first transformer 14 and the output of the second amplifier 122 is connected to a second input of the first transformer 14.

The primary winding of the second transformer 15 is coupled to the first secondary winding of the second transformer 15 and the second secondary winding of the second transformer 15, respectively, the first secondary winding of the second transformer 15 includes a first output terminal of the second transformer 15 and a second output terminal of the second transformer 15, the second secondary winding of the second transformer 15 includes a third output terminal of the second transformer 15 and a fourth output terminal of the second transformer 15, the primary winding of the second transformer 15 includes a first input terminal of the second transformer 15 and a second input terminal of the second transformer 15, the third driving chip U3 is coupled to the first input terminal of the second transformer 15, the fourth driving chip U4 is coupled to the second input terminal of the second transformer 15, i.e. the output of the third amplifier 123 is connected to a first input of the second transformer 15 and the output of the fourth amplifier 124 is connected to a second input of the second transformer 15.

The logic signal output by the first output terminal Q1 of the control chip 11 is amplified by the first amplifier 121 and then input to the first input terminal of the first transformer 14, the logic signal output by the second output terminal Q2 of the control chip 11 is amplified by the second amplifier 122 and then input to the second input terminal of the first transformer 14, the logic signal output by the third output terminal Q3 of the control chip 11 is amplified by the third amplifier 131 and then input to the first input terminal of the second transformer 15, and the logic signal output by the fourth output terminal Q4 of the control chip 11 is amplified by the fourth amplifier 132 and then input to the second input terminal of the second transformer 15.

The full-bridge inverter circuit 20 at least includes a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, and a fourth MOS transistor T4. The first output terminal of the first transformer 14 is connected to the gate of the first MOS transistor T1 through a first resistor R1, and the source of the first MOS transistor T1 is coupled to the second output terminal of the first transformer 14 and the drain of the second MOS transistor T2; the fourth output terminal of the first transformer 14 is connected to the gate of the second MOS transistor T2 through a second resistor R2, and the source of the second MOS transistor T2 is coupled to the third output terminal of the first transformer 14, the third output terminal of the second transformer 15, and the source of the fourth MOS transistor T4; the fourth output terminal of the second transformer 15 is connected to the gate of the fourth MOS transistor T4 through a fourth resistor R4, and the drain of the fourth MOS transistor T4 is coupled to the second output terminal of the second transformer 15 and the source of the third MOS transistor T3; the first output terminal of the second transformer 15 is connected to the gate of the third MOS transistor T3 through a third resistor R3, and the drain of the third MOS transistor T3 is coupled to the drain of the first MOS transistor T1.

The first input end of the first transformer 14, the first output end and the third output end of the first transformer 14 are homonymous ends, and the first input end of the second transformer 15, the first output end and the third output end of the second transformer 15 are homonymous ends. In other embodiments, the first input terminal of the first transformer 14 may be a homonymous terminal with the second output terminal and the fourth output terminal of the first transformer 14; the first input terminal of the second transformer 15 may be a dotted terminal with the second output terminal and the fourth output terminal of the second transformer 15, so that the output windings respectively connected to the first MOS transistor T1 and the second MOS transistor T2 are wound in the same direction.

The full-bridge inverter circuit 20 may further include a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a sixteenth resistor R16; one end of the first capacitor C1, one end of the second capacitor C2, one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14 are connected to the source of the first MOS transistor T1; one end of the third capacitor C3, one end of the fourth capacitor C4, one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16 are connected to the source of the third MOS transistor; the other end of the first capacitor C1, the other end of the thirteenth resistor R13, the other end of the third capacitor C3 and the other end of the fifteenth resistor R15 are connected with the drain electrode of the first MOS transistor T1; the other end of the second capacitor C2, the other end of the fourth capacitor C4, the other end of the fourteenth resistor R14 and the other end of the sixteenth resistor R16 are connected to the source of the second MOS transistor T2. The thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16 respectively perform a voltage division function to respectively adjust voltages at two ends of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3 and the fourth MOS transistor T4, and the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are used for eliminating voltage spikes generated when the parallel MOS transistors of the switches are respectively connected, so as to protect the MOS transistors.

The first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 are P-type MOS transistors. In other embodiments, the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 may be other MOS transistors, for example, the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 are all N-type MOS transistors.

The following describes the operation principle of the driving circuit 10 of the present embodiment driving the full-bridge inverter circuit 20:

when the logic signal received by the first input terminal of the first transformer 14 flows to the second input terminal of the first transformer 14, the first output terminal of the first transformer 14 controls the first MOS transistor T1 to be turned on, and the second MOS transistor T2 is turned off; when the logic signal received by the first input terminal of the second transformer 15 flows to the second input terminal of the second transformer 15, the first output terminal of the second transformer 15 controls the third MOS transistor T3 to be turned on, and the fourth MOS transistor T4 to be turned off.

When the logic signal received by the second input terminal of the first transformer 14 flows to the first input terminal of the first transformer 14, at this time, the first MOS transistor T1 is turned off, and the fourth output terminal 146 of the first transformer 14 controls the second MOS transistor T2 to be turned on; when the logic signal received by the second input terminal of the second transformer 15 flows to the first input terminal of the second transformer 15, the third MOS transistor T3 is turned off, and the fourth output terminal of the second transformer 15 controls the fourth MOS transistor T4 to be turned on.

The first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are driving resistors, and are used for suppressing oscillation and limiting current. The driving resistor has a large influence on the turn-on process of the MOSFET, the driving resistor is small, which is beneficial to accelerating the turn-off speed and reducing the turn-off loss, but causes overlarge di/dt, and a large collector voltage spike is generated, so that the resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 need to be reasonably set, preferably, the resistance values can be set to 60-90 ohms, so as to ensure the driving currents of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3 and the fourth MOS transistor T4, and avoid the overhigh driving voltages of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3 and the fourth MOS transistor T4.

In the embodiment, the first driving chip U1 and the second driving chip U2 drive the first MOS transistor T1 and the second MOS transistor T2 of the full-bridge inverter circuit 20 in an isolated manner through the first transformer 14, and the third driving chip U3 and the fourth driving chip U4 drive the third MOS transistor T3 and the fourth MOS transistor T4 of the full-bridge inverter circuit 20 in an isolated manner through the second transformer 15, so that the isolated driving can be realized, the structure is simple, the cost is reduced, the delay time of signal transmission of the first transformer 14 and the second transformer 15 is short, and the high-frequency signal transmission is suitable for transmitting high-frequency signals; in addition, the output windings respectively connected to the first MOS transistor T1 and the second MOS transistor T2 are wound in the same direction, but two output paths are reversely connected to the gates of the first MOS transistor T1 and the second MOS transistor T2, so that the MOS transistors on the same arm of the full-bridge inverter circuit 20 are reversed, the first MOS transistor T1 and the second MOS transistor T2 are not simultaneously turned on, and similarly, the third MOS transistor T3 and the fourth MOS transistor T4 are not simultaneously turned on, thereby preventing the full-bridge inverter circuit 20 from short circuit. It can be understood that, in the process of turning off the MOS transistors, there is a tailing effect, that is, the turn-off time is relatively longer than the turn-on time, in order to further prevent the simultaneous conduction of the upper and lower MOS transistors of the same bridge arm, a certain dead time may be set, that is, the conduction and the turn-off of the upper and lower MOS transistors of the same bridge arm are staggered by a certain time, and there are various technical schemes for setting the dead time, such as delay conduction and early conduction compensation, etc. since the technical scheme for setting the dead time is the prior art and is not the key content of the present case, the description is not provided here.

The present application further provides a driving circuit of the second embodiment, which is described on the basis of the driving circuit 10 disclosed in the first embodiment. As shown in fig. 2, the driving circuit 10 of the present embodiment further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12.

The anode of the first diode D1 is connected to the gate of the first MOS transistor T1 through the fifth resistor R5, and the cathode of the first diode D1 is connected to the first output terminal of the first transformer 14; the anode of the second diode D2 is connected to the gate of the second MOS transistor T2 through the sixth resistor R6, and the cathode of the second diode D2 is connected to the fourth output terminal of the first transformer 14; the anode of the third diode D3 is connected to the gate of the third MOS transistor T3 through the seventh resistor R7, and the cathode of the third diode D3 is connected to the first output terminal of the second transformer 15; the anode of the fourth diode D4 is connected to the gate of the fourth MOS transistor T4 through the eighth resistor R8, and the cathode of the fourth diode D4 is connected to the fourth output terminal of the second transformer 15.

The fifth resistor R5 and the first diode D1 form a discharge loop of the first MOS transistor T1, the sixth resistor R6 and the second diode D2 form a discharge loop of the second MOS transistor T2, the seventh resistor R7 and the third diode D3 form a discharge loop of the third MOS transistor T3, and the eighth resistor R8 and the fourth diode D4 form a discharge loop of the fourth MOS transistor T4. The resistance of the fifth resistor R5 is smaller than that of the first resistor R1, the resistance of the sixth resistor R6 is smaller than that of the second resistor R2, the resistance of the seventh resistor R7 is smaller than that of the third resistor R3, and the resistance of the eighth resistor R8 is smaller than that of the fourth resistor R4, so that the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 can discharge fast, and the turn-off speed is increased. For example, the resistance values of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 may be set to 10-30 ohms.

The first driving chip U1 is connected to the first input terminal of the first transformer 14 through a ninth resistor R9, the second driving chip U2 is connected to the second input terminal of the first transformer 14 through a tenth resistor R10, the third driving chip U3 is connected to the first input terminal of the second transformer 15 through an eleventh resistor R11, and the fourth driving chip U4 is connected to the second input terminal of the second transformer 15 through a twelfth resistor R12.

Compared with the driving circuit of the first embodiment, the fifth resistor R5 and the first diode D1 of the present embodiment form a discharge loop of the first MOS transistor T1, the sixth resistor R6 and the second diode D2 form a discharge loop of the second MOS transistor T2, the seventh resistor R7 and the third diode D3 form a discharge loop of the third MOS transistor T3, and the eighth resistor R8 and the fourth diode D4 form a discharge loop of the fourth MOS transistor T4, so that the fast discharge of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3 and the fourth MOS transistor T4 can be realized, and the turn-off speed can be improved.

As shown in fig. 3, the switching power supply 30 disclosed in the present embodiment includes a driving circuit 31, and the driving circuit 31 is the driving circuit disclosed in the above embodiments and is not described herein again.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

A driving circuit is characterized in that the driving circuit is coupled with a full-bridge inverter circuit, the driving circuit at least comprises a control chip, a first driving chip, a second driving chip, a third driving chip, a fourth driving chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer and a second transformer, the control chip is coupled with the first driving chip, the second driving chip, the third driving chip and the fourth driving chip, a primary coil of the first transformer is respectively coupled with a first secondary coil of the first transformer and a second secondary coil of the first transformer, the first secondary coil of the first transformer comprises a first output end of the first transformer and a second output end of the first transformer, the second secondary coil of the first transformer comprises a third output end of the first transformer and a fourth output end of the first transformer, the primary coil of the first transformer comprises a first input end of the first transformer and a second input end of the first transformer, the first driving chip is coupled with the first input end of the first transformer, and the second driving chip is coupled with the second input end of the first transformer; the primary coil of the second transformer is coupled to a first secondary coil of the second transformer and a second secondary coil of the second transformer respectively, the first secondary coil of the second transformer includes a first output end of the second transformer and a second output end of the second transformer, the second secondary coil of the second transformer includes a third output end of the second transformer and a fourth output end of the second transformer, the primary coil of the second transformer includes a first input end of the second transformer and a second input end of the second transformer, the third driving chip is coupled to the first input end of the second transformer, and the fourth driving chip is coupled to the second input end of the second transformer;

the full-bridge inverter circuit at least comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein a first output end of the first transformer is connected with a grid electrode of the first MOS tube through the first resistor, a source electrode of the first MOS tube is coupled with a second output end of the first transformer and a drain electrode of the second MOS tube, a fourth output end of the first transformer is connected with a grid electrode of the second MOS tube through the second resistor, a source electrode of the second MOS tube is coupled with a third output end of the first transformer, a third output end of the second transformer and a source electrode of the fourth MOS tube, a fourth output end of the second transformer is connected with a grid electrode of the fourth MOS tube through the fourth resistor, a drain electrode of the fourth MOS tube is coupled with a second output end of the second transformer and a source electrode of the third MOS tube, a first output end of the second transformer is connected with a grid electrode of the third MOS tube through the third resistor, the drain electrode of the third MOS tube is coupled with the drain electrode of the first MOS tube; the first input end of the first transformer, the first output end of the first transformer and the third output end of the first transformer are homonymous ends, and the first input end of the second transformer, the first output end of the second transformer and the third output end of the second transformer are homonymous ends.
The driving circuit according to claim 1, further comprising a first diode, a second diode, a third diode, a fourth diode, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein an anode of the first diode is connected to the gate of the first MOS transistor through the fifth resistor, and a cathode of the first diode is connected to the first output terminal of the first transformer; the anode of the second diode is connected with the grid electrode of the second MOS tube through the sixth resistor, and the cathode of the second diode is connected with the fourth output end of the first transformer; the anode of the third diode is connected with the grid electrode of the third MOS tube through the seventh resistor, and the cathode of the third diode is connected with the first output end of the second transformer; the anode of the fourth diode is connected with the gate of the fourth MOS transistor through the eighth resistor, and the cathode of the fourth diode is connected with the fourth output end of the second transformer.
The driving circuit according to claim 2, wherein the resistance of the fifth resistor is smaller than the resistance of the first resistor, the resistance of the sixth resistor is smaller than the resistance of the second resistor, the resistance of the seventh resistor is smaller than the resistance of the third resistor, and the resistance of the eighth resistor is smaller than the resistance of the fourth resistor.
The driving circuit according to claim 2, further comprising a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor, wherein the first driving chip is connected to the first input terminal of the first transformer through the ninth resistor, the second driving chip is connected to the second input terminal of the first transformer through the tenth resistor, the third driving chip is connected to the first input terminal of the second transformer through the eleventh resistor, and the fourth driving chip is connected to the second input terminal of the second transformer through the twelfth resistor.
The driving circuit according to claim 1, wherein the full-bridge inverter circuit further comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a sixteenth resistor, and one end of the first capacitor, one end of the second capacitor, one end of the thirteenth resistor and one end of the fourteenth resistor are connected to the source of the first MOS transistor; one end of the third capacitor, one end of the fourth capacitor, one end of the fifteenth resistor and one end of the sixteenth resistor are connected with the source electrode of the third MOS tube; the other end of the first capacitor, the other end of the thirteenth resistor, the other end of the third capacitor and the other end of the fifteenth resistor are connected with the drain electrode of the first MOS tube; the other end of the second capacitor, the other end of the fourth capacitor, the other end of the fourteenth resistor and the other end of the sixteenth resistor are connected with the source electrode of the second MOS tube.
A switching power supply is characterized in that the switching power supply comprises a driving circuit, the driving circuit is coupled with a full-bridge inverter circuit, the driving circuit at least comprises a control chip, a first driving chip, a second driving chip, a third driving chip, a fourth driving chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer and a second transformer, the control chip is coupled with the first driving chip, the second driving chip, the third driving chip and the fourth driving chip, a primary coil of the first transformer is coupled with a first secondary coil of the first transformer and a second secondary coil of the first transformer respectively, the first secondary coil of the first transformer comprises a first output end of the first transformer and a second output end of the first transformer, and the second secondary coil of the first transformer comprises a third output end of the first transformer and a second output end of the first transformer The primary coil of the first transformer comprises a first input terminal of the first transformer and a second input terminal of the first transformer, the first driver chip is coupled to the first input terminal of the first transformer, and the second driver chip is coupled to the second input terminal of the first transformer; the primary coil of the second transformer is coupled to a first secondary coil of the second transformer and a second secondary coil of the second transformer respectively, the first secondary coil of the second transformer includes a first output end of the second transformer and a second output end of the second transformer, the second secondary coil of the second transformer includes a third output end of the second transformer and a fourth output end of the second transformer, the primary coil of the second transformer includes a first input end of the second transformer and a second input end of the second transformer, the third driving chip is coupled to the first input end of the second transformer, and the fourth driving chip is coupled to the second input end of the second transformer;

the full-bridge inverter circuit at least comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein a first output end of the first transformer is connected with a grid electrode of the first MOS tube through the first resistor, a source electrode of the first MOS tube is coupled with a second output end of the first transformer and a drain electrode of the second MOS tube, a fourth output end of the first transformer is connected with a grid electrode of the second MOS tube through the second resistor, a source electrode of the second MOS tube is coupled with a third output end of the first transformer, a third output end of the second transformer and a source electrode of the fourth MOS tube, a fourth output end of the second transformer is connected with a grid electrode of the fourth MOS tube through the fourth resistor, a drain electrode of the fourth MOS tube is coupled with a second output end of the second transformer and a source electrode of the third MOS tube, a first output end of the second transformer is connected with a grid electrode of the third MOS tube through the third resistor, the drain electrode of the third MOS tube is coupled with the drain electrode of the first MOS tube; the first input end of the first transformer, the first output end of the first transformer and the third output end of the first transformer are homonymous ends, and the first input end of the second transformer, the first output end of the second transformer and the third output end of the second transformer are homonymous ends.
The switching power supply according to claim 6, wherein the driving circuit further comprises a first diode, a second diode, a third diode, a fourth diode, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor, wherein an anode of the first diode is connected to the gate of the first MOS transistor through the fifth resistor, and a cathode of the first diode is connected to the first output terminal of the first transformer; the anode of the second diode is connected with the grid electrode of the second MOS tube through the sixth resistor, and the cathode of the second diode is connected with the fourth output end of the first transformer; the anode of the third diode is connected with the grid electrode of the third MOS tube through the seventh resistor, and the cathode of the third diode is connected with the first output end of the second transformer; the anode of the fourth diode is connected with the gate of the fourth MOS transistor through the eighth resistor, and the cathode of the fourth diode is connected with the fourth output end of the second transformer.
The switching power supply according to claim 7, wherein a resistance value of the fifth resistor is smaller than a resistance value of the first resistor, a resistance value of the sixth resistor is smaller than a resistance value of the second resistor, a resistance value of the seventh resistor is smaller than a resistance value of the third resistor, and a resistance value of the eighth resistor is smaller than a resistance value of the fourth resistor.
The switching power supply according to claim 7, wherein the driving circuit further comprises a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor, the first driving chip is connected to the first input terminal of the first transformer through the ninth resistor, the second driving chip is connected to the second input terminal of the first transformer through the tenth resistor, the third driving chip is connected to the first input terminal of the second transformer through the eleventh resistor, and the fourth driving chip is connected to the second input terminal of the second transformer through the twelfth resistor.
The switching power supply according to claim 6, wherein the full-bridge inverter circuit further comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a sixteenth resistor, wherein one end of the first capacitor, one end of the second capacitor, one end of the thirteenth resistor and one end of the fourteenth resistor are connected to the source of the first MOS transistor; one end of the third capacitor, one end of the fourth capacitor, one end of the fifteenth resistor and one end of the sixteenth resistor are connected with the source electrode of the third MOS tube; the other end of the first capacitor, the other end of the thirteenth resistor, the other end of the third capacitor and the other end of the fifteenth resistor are connected with the drain electrode of the first MOS tube; the other end of the second capacitor, the other end of the fourth capacitor, the other end of the fourteenth resistor and the other end of the sixteenth resistor are connected with the source electrode of the second MOS tube.