WO2020087224A1 - Driving circuit and switch power supply - Google Patents

Abstract

A driving circuit and a switch power supply. The driving circuit (10) at least comprises a control chip (11), a first driving chip (U1), a second driving chip (U2), a third driving chip (U3), a fourth driving chip (U4), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a first transformer (14) and a second transformer (15), wherein the first driving chip (U1) is coupled to a first input end of the first transformer (14); the second driving chip (U2) is coupled to a second input end of the first transformer (14); the third driving chip (U3) is coupled to a first input end of the second transformer (15); and the fourth driving chip (U4) is coupled to a second input end of the second transformer (15). By means of isolating the first transformer (14) and the second transformer (15), that is, the driving circuit (10) being coupled to a full-bridge inverter circuit (20) through the first transformer (14) and the second transformer (15), a signal transmission delay time is reduced, and high-frequency signals can be transmitted.

Description

Drive circuit and switching power supply The

【Technical Field】

This application relates to the technical field of power supply, in particular to a driving circuit and a switching power supply.

 【Background technique】

At present, full-bridge inverter circuits are widely used, and many high-power switching power supplies use this circuit structure. The advantage of the full-bridge circuit is that the output power is large, and the power switch tube is required to have a low withstand voltage, which is convenient for selecting the power switch tube.

The driving circuit is used to amplify the PWM signal output by the control circuit, thereby meeting the requirements of driving the power switch tube. The performance of the drive circuit is directly related to the switching speed and power consumption of the switch tube, the overall efficiency and reliability. Among them, the driving circuit must realize the electrical isolation of the control circuit and the gate of the driven switch tube.

In the prior art, the electrical isolation of the control circuit and the gate of the driven switch tube is achieved by a photocoupler. The photocoupler includes a light emitting diode and a phototransistor. When the light emitting diode emits light, the phototransistor is turned on. However, the optical coupler has a narrow frequency band, and is not suitable for transmitting high-frequency switching signals; in addition, the optical coupler has a long delay time, and therefore the response is slow.

 [Invention content]

The main technical problem solved by this application is to provide a driving circuit and a switching power supply, which can reduce the signal transmission delay time and transmit high-frequency signals.

In order to solve the above technical problems, a technical solution adopted by the present application is to provide a driving circuit which is coupled to a full-bridge inverter circuit, and the driving circuit at least includes a control chip, a first driving chip, and a second driving chip. A third driving chip, a fourth driving chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer, and a second transformer, the control chip is coupled to the first driving chip, the first Two driving chips, the third driving chip and the fourth driving chip, the primary coil of the first transformer and the first secondary coil of the first transformer and the second secondary of the first transformer respectively Coil coupling, the first secondary coil of the first transformer includes a first output terminal of the first transformer and a second output terminal of the first transformer, the second secondary coil of the first transformer includes A third output terminal of the first transformer and a fourth output terminal of the first transformer, a primary coil of the first transformer includes a first input terminal of the first transformer and the first transformer The second input terminal, the first driving chip is coupled to the first input terminal of the first transformer, the second driving chip is coupled to the second input terminal of the first transformer; the primary of the second transformer The coils are respectively coupled to the first secondary coil of the second transformer and the second secondary coil of the second transformer, the first secondary coil of the second transformer includes the first output of the second transformer Terminal and the second output terminal of the second transformer, the second secondary coil of the second transformer includes a third output terminal of the second transformer and a fourth output terminal of the second transformer, the first The primary coil of the two transformers includes a first input end of the second transformer and a second input end of the second transformer, the third driving chip is coupled to the first input end of the second transformer, the first Four driving chips are coupled to the second input end of the second transformer;

The full-bridge inverter circuit includes at least a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube. The first output terminal of the first transformer is connected to the first The gate of a MOS tube, the source of the first MOS tube is coupled to the second output terminal of the first transformer and the drain of the second MOS tube, the fourth output terminal of the first transformer passes The second resistor is connected to the gate of the second MOS tube, and the source of the second MOS tube is coupled to the third output terminal of the first transformer, the third output terminal of the second transformer and all The source of the fourth MOS tube, the fourth output terminal of the second transformer is connected to the gate of the fourth MOS tube through the fourth resistor, and the drain of the fourth MOS tube is coupled to the first A second output terminal of the second transformer and a source of the third MOS tube, a first output terminal of the second transformer is connected to the gate of the third MOS tube through the third resistor, and the third MOS The drain of the tube is coupled to the drain of the first MOS tube; the first input terminal of the first transformer and the first output terminal of the first transformer A third output terminal and the dotted terminals, a first input terminal of said second transformer and said second transformer first output terminal and third output terminal of the same name.

In order to solve the above technical problems, another technical solution adopted by the present application is to provide a switching power supply including a driving circuit, the driving circuit is coupled to a full-bridge inverter circuit, and the driving circuit includes at least a control chip and a A driving chip, a second driving chip, a third driving chip, a fourth driving chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer and a second transformer, the control chip is coupled to the The first driving chip, the second driving chip, the third driving chip and the fourth driving chip, the primary coil of the first transformer and the first secondary coil and the first transformer of the first transformer respectively The second secondary coil of the first transformer is coupled. The first secondary coil of the first transformer includes a first output terminal of the first transformer and a second output terminal of the first transformer. A second secondary coil of a transformer includes a third output terminal of the first transformer and a fourth output terminal of the first transformer, and a primary coil of the first transformer includes the first transformer A first input terminal and a second input terminal of the first transformer, the first driving chip is coupled to the first input terminal of the first transformer, and the second driving chip is coupled to the first input terminal of the first transformer Two input terminals; the primary coil of the second transformer is respectively coupled to the first secondary coil of the second transformer and the second secondary coil of the second transformer, the first secondary of the second transformer The coil includes a first output terminal of the second transformer and a second output terminal of the second transformer, and a second secondary coil of the second transformer includes a third output terminal of the second transformer and the first A fourth output end of the second transformer, the primary coil of the second transformer includes a first input end of the second transformer and a second input end of the second transformer, and the third driving chip is coupled to the first A first input end of two transformers, the fourth driving chip is coupled to a second input end of the second transformer;

The full-bridge inverter circuit includes at least a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube. The first output terminal of the first transformer is connected to the first The gate of a MOS tube, the source of the first MOS tube is coupled to the second output terminal of the first transformer and the drain of the second MOS tube, the fourth output terminal of the first transformer passes The second resistor is connected to the gate of the second MOS tube, and the source of the second MOS tube is coupled to the third output terminal of the first transformer, the third output terminal of the second transformer and all The source of the fourth MOS tube, the fourth output terminal of the second transformer is connected to the gate of the fourth MOS tube through the fourth resistor, and the drain of the fourth MOS tube is coupled to the first A second output terminal of the second transformer and a source of the third MOS tube, a first output terminal of the second transformer is connected to the gate of the third MOS tube through the third resistor, and the third MOS The drain of the tube is coupled to the drain of the first MOS tube; the first input terminal of the first transformer and the first output terminal of the first transformer A third output terminal and the dotted terminals, a first input terminal of said second transformer and said second transformer first output terminal and third output terminal of the same name.

The beneficial effects of the present application are: different from the situation in the prior art, the first driving chip of the present application is coupled to the first input terminal of the first transformer, the second driving chip is coupled to the second input terminal of the first transformer, and the third The driving chip is coupled to the first input terminal of the second transformer, and the fourth driving chip is coupled to the second input terminal of the second transformer; the first output terminal of the first transformer is connected to the gate of the first MOS tube through the first resistor, The source of a MOS tube is coupled to the second output terminal of the first transformer and the drain of the second MOS tube, the fourth output terminal of the first transformer is connected to the gate of the second MOS tube through the second resistor, and the second MOS tube Is coupled to the third output terminal of the first transformer, the third output terminal of the second transformer, and the source electrode of the fourth MOS tube, and the fourth output terminal of the second transformer is connected to the gate of the fourth MOS tube through a fourth resistor Electrode, the drain of the fourth MOS tube is coupled to the second output of the second transformer and the source of the third MOS tube, the first output of the second transformer is connected to the gate of the third MOS tube through a third resistor, The drain of the three MOS tube is coupled to the drain of the first MOS tube. A driving circuit using a first and second transformers isolation, i.e., a first driving circuit and second transformers and a full bridge inverter circuit is coupled to reduce the signal propagation delay time, and transmitting a high frequency signal.

 【Explanation】

In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some of the applications For the embodiment, for those of ordinary skill in the art, without paying any creative labor, other drawings may be obtained based on these drawings.

FIG. 1 is a circuit diagram of the driving circuit of the first embodiment of the present application;

2 is a circuit diagram of a driving circuit of a second embodiment of the present application;

3 is a schematic structural diagram of a switching power supply according to the first embodiment of the present application.

【detailed description】

The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work fall within the protection scope of the present application.

Please refer to FIG. 1, which is a circuit diagram of the driving circuit of the first embodiment of the present application. The driving circuit 10 of this embodiment is coupled to the full-bridge inverter circuit 20 and is used to drive the MOS transistor of the full-bridge inverter circuit 20.

The driving circuit 10 includes at least a control chip 11, a first driving chip U1, a second driving chip U2, a third driving chip U3, a fourth driving chip U4, a first transformer 14, a second transformer 15, a first resistor R1 The second resistor R2, the third resistor R3, and the fourth resistor R4.

The control chip 11 is coupled to the first driving chip U1, the second driving chip U2, the third driving chip U3, and the fourth driving chip U4, wherein the first driving chip U1 may include a first amplifier 121, and the second driving chip U2 may include a first Two amplifiers 122, the third driving chip U3 may include a third amplifier 123, the fourth driving chip U4 may include a fourth amplifier 124; the input terminal of the first amplifier 121 is connected to the first output terminal Q1 of the control chip 11, and the second amplifier The input of 122 is connected to the second output Q2 of the control chip 11, the input of the third amplifier 123 is connected to the third output Q3 of the control chip 11, and the input of the fourth amplifier 124 is connected to the fourth output of the control chip 11 Q4 connection.

The primary coil of the first transformer 14 is coupled to the first secondary coil of the first transformer 14 and the second secondary coil of the first transformer 14 respectively. The first secondary coil of the first transformer 14 includes the first An output terminal and a second output terminal of the first transformer 14, the second secondary coil of the first transformer 14 includes a third output terminal of the first transformer 14 and a fourth output terminal of the first transformer 14, the The primary coil includes a first input end of the first transformer 14 and a second input end of the first transformer 14, the first driving chip U1 is coupled to the first input end of the first transformer 14, and the second driving chip U2 is coupled to the first transformer The second input terminal of 14, that is, the output terminal of the first amplifier 121 is connected to the first input terminal of the first transformer 14, and the output terminal of the second amplifier 122 is connected to the second input terminal of the first transformer 14.

The primary coil of the second transformer 15 is coupled to the first secondary coil of the second transformer 15 and the second secondary coil of the second transformer 15 respectively. The first secondary coil of the second transformer 15 includes the first An output terminal and a second output terminal of the second transformer 15, the second secondary coil of the second transformer 15 includes a third output terminal of the second transformer 15 and a fourth output terminal of the second transformer 15, The primary coil includes a first input terminal of the second transformer 15 and a second input terminal of the second transformer 15, the third driving chip U3 is coupled to the first input terminal of the second transformer 15, and the fourth driving chip U4 is coupled to the second transformer The second input terminal of 15, that is, the output terminal of the third amplifier 123 is connected to the first input terminal of the second transformer 15, and the output terminal of the fourth amplifier 124 is connected to the second input terminal of the second transformer 15.

The logic signal output from the first output terminal Q1 of the control chip 11 is amplified by the first amplifier 121 and input to the first input terminal of the first transformer 14, and the logic signal output from the second output terminal Q2 of the control chip 11 passes through the second amplifier 122 After being amplified and input to the second input terminal of the first transformer 14, the logic signal output from the third output terminal Q3 of the control chip 11 is amplified and input to the first input terminal of the second transformer 15 through the third amplifier 131 to control the The logic signal output from the fourth output terminal Q4 is amplified by the fourth amplifier 132 and input to the second input terminal of the second transformer 15.

The full-bridge inverter circuit 20 includes at least a first MOS tube T1, a second MOS tube T2, a third MOS tube T3, and a fourth MOS tube T4. The first output terminal of the first transformer 14 is connected to the gate of the first MOS transistor T1 through a first resistor R1, and the source of the first MOS transistor T1 is coupled to the second output terminal of the first transformer 14 and the second MOS transistor T2 Drain; the fourth output of the first transformer 14 is connected to the gate of the second MOS transistor T2 through a second resistor R2, the source of the second MOS transistor T2 is coupled to the third output of the first transformer 14, the second transformer The third output terminal of 15 and the source of the fourth MOS transistor T4; the fourth output terminal of the second transformer 15 is connected to the gate of the fourth MOS transistor T4 through a fourth resistor R4, and the drain of the fourth MOS transistor T4 is coupled The second output terminal of the second transformer 15 and the source of the third MOS transistor T3; the first output terminal of the second transformer 15 is connected to the gate of the third MOS transistor T3 through the third resistor R3, and the drain of the third MOS transistor T3 The pole is coupled to the drain of the first MOS transistor T1.

Among them, the first input terminal of the first transformer 14 and the first output terminal and the third output terminal of the first transformer 14 have the same name, the first input terminal of the second transformer 15 and the first output terminal of the second transformer 15 and The third output is the same name. In other embodiments, the first input end of the first transformer 14 may be the same name as the second output end and the fourth output end of the first transformer 14; the first input end of the second transformer 15 may be the same as the second transformer 15 The second output terminal and the fourth output terminal have the same name, so that the output windings connected to the first MOS tube T1 and the second MOS tube T2 can be wound in the same direction.

The full-bridge inverter circuit 20 may further include a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a tenth Six resistors R16; one end of the first capacitor C1, one end of the second capacitor C2, one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14 are connected to the source of the first MOS transistor T1; one end of the third capacitor C3, One end of the fourth capacitor C4, one end of the fifteenth resistor R15 and one end of the sixteenth resistor R16 are connected to the source of the third MOS tube; the other end of the first capacitor C1, the other end of the thirteenth resistor R13, the third The other end of the capacitor C3 and the other end of the fifteenth resistor R15 are connected to the drain of the first MOS transistor T1; the other end of the second capacitor C2, the other end of the fourth capacitor C4, the other end of the fourteenth resistor R14 and the first The other end of the sixteen resistor R16 is connected to the source of the second MOS transistor T2. Among them, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16 respectively play a voltage dividing role to adjust the first MOS tube T1, the second MOS tube T2, the third MOS tube The voltage across T3 and the fourth MOS transistor T4. The first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are used to eliminate voltage spikes generated when the switches are connected in parallel to protect the MOS. tube.

The first MOS tube T1, the second MOS tube T2, the third MOS tube T3, and the fourth MOS tube T4 are all P-type MOS tubes. In other embodiments, the first MOS tube T1, the second MOS tube T2, the third MOS tube T3, and the fourth MOS tube T4 may be other MOS tubes, such as the first MOS tube T1, the second MOS tube T2, the third Both the MOS tube T3 and the fourth MOS tube T4 are N-type MOS tubes.

The following describes the working principle of the driving circuit 10 driving the full-bridge inverter circuit 20 of this embodiment:

When the logic signal received by the first input terminal of the first transformer 14 flows to the second input terminal of the first transformer 14, the first output terminal of the first transformer 14 controls the first MOS transistor T1 to turn on, and the second MOS The tube T2 is disconnected; when the logic signal received at the first input terminal of the second transformer 15 flows to the second input terminal of the second transformer 15, the first output terminal of the second transformer 15 controls the third MOS transistor T3 to conduct On, the fourth MOS transistor T4 is off.

When the logic signal received by the second input terminal of the first transformer 14 flows to the first input terminal of the first transformer 14, the first MOS transistor T1 is disconnected, and the fourth output terminal 146 of the first transformer 14 controls the second The MOS transistor T2 is turned on; when the logic signal received at the second input terminal of the second transformer 15 flows to the first input terminal of the second transformer 15, the third MOS transistor T3 is disconnected, and the fourth of the second transformer 15 The output terminal controls the fourth MOS transistor T4 to be turned on.

Among them, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are driving resistors, and their functions are to suppress oscillation and limit the current. The driving resistance has a great influence on the MOSFET turn-on process. The small driving resistance is helpful to accelerate the turn-off speed and reduce the turn-off loss, but it will cause excessive di / dt and produce a large collector voltage spike. Therefore, it is necessary to set the first resistor reasonably The resistance values of R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are preferably set to 60-90 ohms, thereby ensuring the first MOS tube T1, the second MOS tube T2 and the third MOS tube The driving current of T3 and the fourth MOS tube T4, and to avoid the driving voltage of the first MOS tube T1, the second MOS tube T2, the third MOS tube T3 and the fourth MOS tube T4 is too high.

The first driving chip U1 and the second driving chip U2 of this embodiment isolate and drive the first MOS transistor T1 and the second MOS transistor T2 of the full-bridge inverter circuit 20 through the first transformer 14, and the third driving chip U3 and the fourth The driving chip U4 isolates and drives the third MOS transistor T3 and the fourth MOS transistor T4 of the full-bridge inverter circuit 20 through the second transformer 15, which can realize the isolated driving. The structure is simple and the cost is reduced. The first transformer 14 and the second transformer 15 The delay time of the transmission signal is small, suitable for transmitting high-frequency signals; in addition, the output windings connected to the first MOS tube T1 and the second MOS tube T2 are wound in the same direction, but the two outputs are reversely connected to the first MOS tube T1 With the gate of the second MOS tube T2, the MOS tube on the same bridge arm of the full-bridge inverter circuit 20 is reversed, so that the first MOS tube T1 and the second MOS tube T2 will not be turned on at the same time. The third MOS transistor T3 and the fourth MOS transistor T4 will not be turned on at the same time, thereby preventing the full-bridge inverter circuit 20 from being short-circuited. It is understandable that due to the tailing effect in the process of turning off the MOS tube, that is, the turn-off time is relatively longer than the turn-on time, in order to further prevent the upper and lower MOS tubes of the same bridge arm from turning on at the same time, a certain Dead time, that is, the turn-on and turn-off of the upper and lower MOS tubes of the same bridge arm are staggered by a certain time. There are many technical solutions for setting the dead time, such as delayed turn-on and early turn-on compensation. The technical solution for setting the dead time is the existing technology and is not the focus of this case, so it will not be described here.

The present application further provides the driving circuit of the second embodiment, which is described on the basis of the driving circuit 10 disclosed in the first embodiment. As shown in FIG. 2, the driving circuit 10 of this embodiment further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first diode D1, a second diode D2, a first Three diodes D3, fourth diodes D4, ninth resistor R9, tenth resistor R10, eleventh resistor R11 and twelfth resistor R12.

The anode of the first diode D1 is connected to the gate of the first MOS transistor T1 through a fifth resistor R5, and the cathode of the first diode D1 is connected to the first output of the first transformer 14; the second diode D2 The anode of the second diode is connected to the gate of the second MOS transistor T2 through a sixth resistor R6, the cathode of the second diode D2 is connected to the fourth output terminal of the first transformer 14; the anode of the third diode D3 is connected through the seventh resistor R7 The gate of the third MOS transistor T3, the cathode of the third diode D3 is connected to the first output terminal of the second transformer 15; the anode of the fourth diode D4 is connected to the gate of the fourth MOS transistor T4 through the eighth resistor R8 The cathode of the fourth diode D4 is connected to the fourth output terminal of the second transformer 15.

Among them, the fifth resistor R5 and the first diode D1 constitute the discharge circuit of the first MOS transistor T1, the sixth resistor R6 and the second diode D2 constitute the discharge circuit of the second MOS transistor T2, the seventh resistor R7 and the first The three diodes D3 constitute the discharge circuit of the third MOS transistor T3, and the eighth resistor R8 and the fourth diode D4 constitute the discharge circuit of the fourth MOS transistor T4. The resistance of the fifth resistor R5 is smaller than that of the first resistor R1, the resistance of the sixth resistor R6 is smaller than that of the second resistor R2, the resistance of the seventh resistor R7 is smaller than that of the third resistor R3, the eighth The resistance of the resistor R8 is smaller than the resistance of the fourth resistor R4, so the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 can quickly discharge, increasing the turn-off speed. For example, the resistance values of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 can all be set to 10-30 ohms.

The first driving chip U1 is connected to the first input terminal of the first transformer 14 through a ninth resistor R9, the second driving chip U2 is connected to the second input terminal of the first transformer 14 through a tenth resistor R10, and the third driving chip U3 is connected through The eleventh resistor R11 is connected to the first input terminal of the second transformer 15, and the fourth driving chip U4 is connected to the second input terminal of the second transformer 15 through the twelfth resistor R12.

Compared with the drive circuit of the first embodiment, the fifth resistor R5 and the first diode D1 of this embodiment constitute the discharge circuit of the first MOS transistor T1, and the sixth resistor R6 and the second diode D2 constitute the second MOS The discharge circuit of the tube T2, the seventh resistor R7 and the third diode D3 constitute the discharge circuit of the third MOS tube T3, and the eighth resistor R8 and the fourth diode D4 constitute the discharge circuit of the fourth MOS tube T4. The first MOS tube T1, the second MOS tube T2, the third MOS tube T3, and the fourth MOS tube T4 are quickly discharged to increase the turn-off speed.

The present application also provides a switching power supply 30. As shown in FIG. 3, the switching power supply 30 disclosed in this embodiment includes a driving circuit 31. The driving circuit 31 is the driving circuit disclosed in the foregoing embodiment, and details are not described herein again.

The above are only the embodiments of the present application, and therefore do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by the description and drawings of this application, or directly or indirectly used in other related technologies In the field, the same reason is included in the scope of patent protection of this application.

Claims (10)

1. A driving circuit, characterized in that the driving circuit is coupled to a full-bridge inverter circuit, and the driving circuit at least includes a control chip, a first driving chip, a second driving chip, a third driving chip, and a fourth driving chip , A first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer and a second transformer, the control chip is coupled to the first drive chip, the second drive chip, the third drive Chip and the fourth driving chip, the primary coil of the first transformer is respectively coupled to the first secondary coil of the first transformer and the second secondary coil of the first transformer, the first transformer Of the first secondary coil includes the first output of the first transformer and the second output of the first transformer, the second secondary coil of the first transformer includes the third output of the first transformer Terminal and the fourth output terminal of the first transformer, the primary coil of the first transformer includes a first input terminal of the first transformer and a second input terminal of the first transformer, the first driver chip Connected to the first input end of the first transformer, the second driving chip is coupled to the second input end of the first transformer; the primary coil of the second transformer is respectively connected to the first time of the second transformer Primary coil and the second secondary coil of the second transformer, the first secondary coil of the second transformer includes a first output terminal of the second transformer and a second output terminal of the second transformer , The second secondary coil of the second transformer includes a third output terminal of the second transformer and a fourth output terminal of the second transformer, and the primary coil of the second transformer includes the The first input terminal and the second input terminal of the second transformer, the third driving chip is coupled to the first input terminal of the second transformer, and the fourth driving chip is coupled to the first input terminal of the second transformer Two input terminals;

   The full-bridge inverter circuit includes at least a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube. The first output terminal of the first transformer is connected to the first The gate of a MOS tube, the source of the first MOS tube is coupled to the second output terminal of the first transformer and the drain of the second MOS tube, the fourth output terminal of the first transformer passes The second resistor is connected to the gate of the second MOS tube, and the source of the second MOS tube is coupled to the third output terminal of the first transformer, the third output terminal of the second transformer and all The source of the fourth MOS tube, the fourth output terminal of the second transformer is connected to the gate of the fourth MOS tube through the fourth resistor, and the drain of the fourth MOS tube is coupled to the first A second output terminal of the second transformer and a source of the third MOS tube, a first output terminal of the second transformer is connected to the gate of the third MOS tube through the third resistor, and the third MOS The drain of the tube is coupled to the drain of the first MOS tube; the first input terminal of the first transformer and the first output terminal of the first transformer A third output terminal and the dotted terminals, a first input terminal of said second transformer and said second transformer first output terminal and third output terminal of the same name.
2. The driving circuit according to claim 1, wherein the driving circuit further comprises a first diode, a second diode, a third diode, a fourth diode, a fifth resistor, a sixth A resistor, a seventh resistor, and an eighth resistor, the anode of the first diode is connected to the gate of the first MOS tube through the fifth resistor, and the cathode of the first diode is connected to the first The first output of the transformer; the anode of the second diode is connected to the gate of the second MOS tube through the sixth resistor, and the cathode of the second diode is connected to the first of the first transformer Four output terminals; the anode of the third diode is connected to the gate of the third MOS tube through the seventh resistor, and the cathode of the third diode is connected to the first output terminal of the second transformer The anode of the fourth diode is connected to the gate of the fourth MOS tube through the eighth resistor, and the cathode of the fourth diode is connected to the fourth output end of the second transformer.
3. The driving circuit according to claim 2, wherein the resistance of the fifth resistor is smaller than the resistance of the first resistor, and the resistance of the sixth resistor is smaller than the resistance of the second resistor, The resistance of the seventh resistor is less than the resistance of the third resistor, and the resistance of the eighth resistor is less than the resistance of the fourth resistor.
4. The driving circuit according to claim 2, wherein the driving circuit further comprises a ninth resistance, a tenth resistance, an eleventh resistance and a twelfth resistance, and the first driving chip passes the ninth resistance Connected to the first input terminal of the first transformer, the second driver chip is connected to the second input terminal of the first transformer through the tenth resistor, and the third driver chip is connected through the eleventh resistor The first input terminal of the second transformer, the fourth driving chip is connected to the second input terminal of the second transformer through the twelfth resistor.
5. The driving circuit according to claim 1, wherein the full-bridge inverter circuit further includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a thirteenth resistor, a fourteenth resistor, A fifteenth resistor and a sixteenth resistor, one end of the first capacitor, one end of the second capacitor, one end of the thirteenth resistor and one end of the fourteenth resistor are connected to the first MOS tube The source of the third capacitor, the end of the fourth capacitor, the end of the fifteenth resistor, and the end of the sixteenth resistor connected to the source of the third MOS tube; The other end of the first capacitor, the other end of the thirteenth resistor, the other end of the third capacitor, and the other end of the fifteenth resistor are connected to the drain of the first MOS tube; the second The other end of the capacitor, the other end of the fourth capacitor, the other end of the fourteenth resistor, and the other end of the sixteenth resistor are connected to the source of the second MOS tube.
6. A switching power supply, characterized in that the switching power supply includes a driving circuit, the driving circuit is coupled to a full-bridge inverter circuit, the driving circuit at least includes a control chip, a first driving chip, a second driving chip, a Three driving chips, a fourth driving chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transformer and a second transformer, the control chip is coupled to the first driving chip and the second A driving chip, the third driving chip and the fourth driving chip, the primary coil of the first transformer and the first secondary coil of the first transformer and the second secondary coil of the first transformer respectively Coupling, the first secondary coil of the first transformer includes a first output terminal of the first transformer and a second output terminal of the first transformer, the second secondary coil of the first transformer includes all A third output terminal of the first transformer and a fourth output terminal of the first transformer, a primary coil of the first transformer includes a first input terminal of the first transformer and a first output terminal of the first transformer At the input end, the first driving chip is coupled to the first input end of the first transformer, and the second driving chip is coupled to the second input end of the first transformer; the primary coils of the second transformer are respectively Coupled to the first secondary coil of the second transformer and the second secondary coil of the second transformer, the first secondary coil of the second transformer includes the first output end of the second transformer and A second output terminal of the second transformer, a second secondary coil of the second transformer includes a third output terminal of the second transformer and a fourth output terminal of the second transformer, the second transformer The primary coil includes a first input end of the second transformer and a second input end of the second transformer, the third driving chip is coupled to the first input end of the second transformer, and the fourth drive The chip is coupled to the second input end of the second transformer;

   The full-bridge inverter circuit includes at least a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube. The first output terminal of the first transformer is connected to the first The gate of a MOS tube, the source of the first MOS tube is coupled to the second output terminal of the first transformer and the drain of the second MOS tube, the fourth output terminal of the first transformer passes The second resistor is connected to the gate of the second MOS tube, and the source of the second MOS tube is coupled to the third output terminal of the first transformer, the third output terminal of the second transformer and all The source of the fourth MOS tube, the fourth output terminal of the second transformer is connected to the gate of the fourth MOS tube through the fourth resistor, and the drain of the fourth MOS tube is coupled to the first A second output terminal of the second transformer and a source of the third MOS tube, a first output terminal of the second transformer is connected to the gate of the third MOS tube through the third resistor, and the third MOS The drain of the tube is coupled to the drain of the first MOS tube; the first input terminal of the first transformer and the first output terminal of the first transformer A third output terminal and the dotted terminals, a first input terminal of said second transformer and said second transformer first output terminal and third output terminal of the same name.
7. The switching power supply according to claim 6, wherein the driving circuit further comprises a first diode, a second diode, a third diode, a fourth diode, a fifth resistor, a sixth A resistor, a seventh resistor, and an eighth resistor, the anode of the first diode is connected to the gate of the first MOS tube through the fifth resistor, and the cathode of the first diode is connected to the first The first output of the transformer; the anode of the second diode is connected to the gate of the second MOS tube through the sixth resistor, and the cathode of the second diode is connected to the first of the first transformer Four output terminals; the anode of the third diode is connected to the gate of the third MOS tube through the seventh resistor, and the cathode of the third diode is connected to the first output terminal of the second transformer The anode of the fourth diode is connected to the gate of the fourth MOS tube through the eighth resistor, and the cathode of the fourth diode is connected to the fourth output end of the second transformer.
8. The switching power supply according to claim 7, wherein the resistance of the fifth resistor is smaller than the resistance of the first resistor, and the resistance of the sixth resistor is smaller than the resistance of the second resistor, The resistance of the seventh resistor is less than the resistance of the third resistor, and the resistance of the eighth resistor is less than the resistance of the fourth resistor.
9. The switching power supply according to claim 7, wherein the driving circuit further comprises a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor, and the first driving chip passes the ninth resistor Connected to the first input terminal of the first transformer, the second driver chip is connected to the second input terminal of the first transformer through the tenth resistor, and the third driver chip is connected through the eleventh resistor The first input terminal of the second transformer, the fourth driving chip is connected to the second input terminal of the second transformer through the twelfth resistor.
10. The switching power supply according to claim 6, wherein the full-bridge inverter circuit further includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a thirteenth resistor, a fourteenth resistor, A fifteenth resistor and a sixteenth resistor, one end of the first capacitor, one end of the second capacitor, one end of the thirteenth resistor and one end of the fourteenth resistor are connected to the first MOS tube The source of the third capacitor, the end of the fourth capacitor, the end of the fifteenth resistor, and the end of the sixteenth resistor connected to the source of the third MOS tube; The other end of the first capacitor, the other end of the thirteenth resistor, the other end of the third capacitor, and the other end of the fifteenth resistor are connected to the drain of the first MOS tube; the second The other end of the capacitor, the other end of the fourth capacitor, the other end of the fourteenth resistor, and the other end of the sixteenth resistor are connected to the source of the second MOS tube.