CN111669168A - A high-speed level conversion circuit - Google Patents

Abstract

The application relates to a high-speed level shift circuit for shifting different levels of two ports, comprising at least one shift unit, wherein the shift unit comprises a first shift branch, a unidirectional level shift circuit, a first control circuit and a second control circuit, the first shift branch comprises a power supply Vdd, a resistor Rpu and a transistor NM 0; the unidirectional level conversion circuit is used for converting the level of the port for leading communication and outputting a converted level signal; the first control circuit is used for controlling the other port to be directly connected with a power supply Vdd or connected with the power supply Vdd through a resistor Rpu according to the converted level signal; the second control circuit is used for controlling the connection or disconnection between the other port and the ground according to the level signal output by the unidirectional level conversion circuit. The application provides a high-speed level shift circuit, signal rising speed is very fast, signal transmission rate is high when carrying out level shift.

Description

A high-speed level conversion circuit

technical field

The present application relates to the technical field of analog integrated circuits, and in particular, to a high-speed level conversion circuit.

Background technique

At present, in the design of electronic circuits, two digital integrated circuits that communicate with each other often work on different supply voltages. For example, the first chip works at 1.8V and the second chip works at 5V, so the second chip may not be correct. Receive and judge the logic signal sent by the first chip. Conversely, the voltage of the signal sent by the second chip is as high as 5V, which may cause damage to the first chip. Therefore, it is necessary to increase the bidirectional power between the first chip and the second chip. Flat conversion circuit.

Referring to FIG. 1, the bidirectional level conversion circuit in the prior art includes a resistor Rpua1, a load capacitor Cla, a resistor Rpub1, a load capacitor Clb, a transistor NM0, an A port for connecting the first chip and a port for connecting the second chip The B port of the power supply Vdda is grounded through the series resistor Rpua1 and the load capacitor Cla, the power source Vddb is grounded through the series resistor Rpub1 and the load capacitor Clb, the gate of the transistor NM0 is connected to the bias voltage, and the source of the transistor NM0 and the A port Both are connected between the resistor Rpua1 and the load capacitor Cla, and the drain and the B port of the transistor NM0 are both connected between the resistor Rpub1 and the load capacitor Clb.

In the bidirectional level conversion circuit of the prior art, when the level of the A port is pulled low, the transistor NM0 is turned on, and the level of the B port is also pulled down through the transistor NM0; when the level of the A port is pulled high , the transistor NM0 is turned off, and the level of the B port will be pulled to the level of the power supply Vddb through the resistor Rpub1, thereby realizing bidirectional level conversion, and protecting the chip connected to the A port and the B port.

However, in the above-mentioned bidirectional level conversion circuit, when the level of port A is pulled high, it can only rely on the resistor Rpub1 to increase the signal voltage. When the load capacitance Clb is large, the signal rises slowly, so that it can only work below 1Mbps The signal transmission rate cannot meet the current development needs of high-speed transmission signals.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a high-speed bidirectional level conversion circuit to solve the technical problems of slow signal rise and low signal transmission rate during bidirectional level conversion in the related art.

The present application provides a high-speed level conversion circuit, which is used to convert different levels of two ports, and includes at least one conversion unit, the input end of the conversion unit is connected to a port that dominates communication, and the output end is connected to Another port, the conversion unit includes:

a first conversion branch, which includes a power supply Vdd, a resistor Rpu, and a transistor NM0, the transistor NM0 is connected across the port leading the communication and another port, and the power supply Vdd is connected to the other port through the resistor Rpu;

A one-way level conversion circuit, which is used to convert the level of the port that dominates the communication, and output the converted level signal;

The first control circuit, the two ends of which are respectively connected to the power supply Vdd and the other port, which is used to control the other port to be directly connected to the power supply Vdd or connected to the power supply Vdd according to the converted level signal, so that the first control circuit Quickly pull up the level of another port within a preset time;

The second control circuit, the two ends of which are respectively connected to the other port and the ground, is used to control the turn-on or turn-off between the other port and the ground according to the level signal output by the unidirectional level conversion circuit, so as to make the The second control circuit rapidly pulls down the level of the other port within a preset time.

In some embodiments, the first control circuit includes a rising edge detection circuit and a transistor PM2;

The input end of the rising edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end is connected with the gate of the transistor PM2;

The source of the transistor PM2 is connected to the power supply Vdd, and the drain of the transistor PM2 is connected to the other port.

In some embodiments, the rising edge detection circuit includes an inverter INV1 and a NAND gate NAND1 connected in sequence, the input end of the inverter INV1 is connected to the output end of the unidirectional level conversion circuit, and the NAND The two input terminals of the gate NAND1 are respectively connected to the output terminal of the inverter INV1 and the output terminal of the unidirectional level conversion circuit, and the output terminal of the NAND gate NAND1 is connected to the gate of the transistor PM2.

In some embodiments, the second control circuit includes a falling edge detection circuit and a transistor NM2;

The input end of the falling edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end is connected with the gate of the transistor NM2;

The source of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to the other port.

In some embodiments, the falling edge detection circuit includes an inverter INV2 and a NOR gate NOR1 connected in sequence, and the input end of the inverter INV2 is connected to the output end of the unidirectional level conversion circuit, and the NOR Two input terminals of the gate NOR1 are respectively connected to the output terminal of the inverter INV2 and the output terminal of the unidirectional level conversion circuit, and the output terminal of the NOR gate NOR1 is connected to the gate of the transistor NM2. 6. The high-speed level conversion circuit according to claim 1, wherein the first conversion branch further comprises a load capacitor C1, one end of the load capacitor C1 is connected to the other port, and the other end of the load capacitor C1 is connected to the other port. One end is grounded.

In some embodiments, the resistor Rpu includes a resistor Rpub1 and a resistor Rpub2 connected in series, and the conversion unit further includes a third control circuit configured to adjust the resistance value of the resistor Rpub2 according to the converted level signal.

In some embodiments, the third control circuit includes a reset/set RS flip-flop and a transistor PM4, and two input terminals of the RS flip-flop are respectively connected to the output terminal of the rising edge detection circuit and the output of the falling edge detection circuit. terminal, the output terminal of the RS flip-flop is connected to the gate of the transistor PM4, and the source and drain of the transistor PM4 are connected to both ends of the resistor Rpub2.

In some embodiments, the resistance value of the resistor Rpu2 is much larger than the resistance value of the resistor Rpu1.

In some embodiments, the high-speed level conversion circuit includes two conversion units, and each port is connected to the input terminal of one conversion unit and the output terminal of the other conversion unit.

The beneficial effects brought by the technical solution provided by the present application include: when the level conversion is performed, the signal rising speed is relatively fast, and the signal transmission rate is high.

The embodiment of the present application provides a high-speed level conversion circuit. Since the first control circuit and the second control circuit are provided, the level of the other port can be quickly pulled up and down, so that the signal rises or falls faster. The signal transmission rate is greatly improved.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic diagram of a bidirectional level conversion circuit in the prior art;

2 is a schematic diagram of a high-speed level conversion circuit provided by an embodiment of the present application;

3 is a schematic diagram of a rising edge detection circuit and a falling edge detection circuit in an embodiment of the application;

4 is a schematic diagram of a unidirectional level conversion circuit in an embodiment of the application;

5 is a schematic diagram of a high-speed level conversion circuit with a third control circuit provided in an embodiment of the application;

FIG. 6 provides a first high-speed level conversion circuit with two conversion units provided by an embodiment of the present application;

FIG. 7 provides a second high-speed level conversion circuit with two conversion units provided by an embodiment of the present application;

Fig. 8 is the waveform diagram of the main signal in the second high-speed level conversion circuit with two conversion units when the A port dominates the communication;

FIG. 9 is a waveform diagram of main signals in the second type of high-speed level conversion circuit with two conversion units when the B port dominates the communication.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present application.

Referring to FIG. 2, the present application provides a high-speed level conversion circuit, which is used to convert different levels of two ports, and includes at least one conversion unit, the input end of which is connected to one of the main communication port, the output is connected to another port.

The conversion unit includes a first conversion branch, a unidirectional level conversion circuit, a first control circuit and a second control circuit. The first conversion branch includes a power supply Vdd, a resistor Rpu, and a transistor NM0, the transistor NM0 is connected between the port leading the communication and another port, and the power supply Vdd is connected to the other port through the resistor Rpu; unidirectional level The conversion circuit is used to convert the level of the port that dominates the communication, and output the converted level signal; the two ends of the first control circuit are respectively connected to the power supply Vdd and another port, which is used for according to the converted level signal. The other port is controlled to be directly connected to the power supply Vdd or connected through the resistor Rpu, so that the first control circuit can quickly pull up the level of the other port within a preset time; the two ends of the second control circuit are respectively connected to the other port and the ground , which is used to control the turn-on or turn-off between the other port and the ground according to the level signal output by the unidirectional level conversion circuit, so that the second control circuit quickly pulls down the other port within a preset time. level of the port.

It should be noted that the fast pull-up and fast pull-down in the embodiments of the present application should be understood as the same as in the prior art, one port pulls down the level of the other port through the transistor NM0, and pulls up the level of the other port through a power supply and a resistor. Compared with the level of another port, in this embodiment of the present application, the first control circuit can quickly pull the level high, and the second control circuit can quickly pull the low level. In addition, the time for quickly pulling the high level through the first control circuit is preset, the first control circuit pulls the high level within the preset time, and the first control circuit stops pulling the high level outside the preset time, The principle of the second control circuit is similar and will not be repeated here.

In the embodiment of the present application, the port leading the communication is the A port, and the other port is the B port. The working principle of the high-speed level conversion circuit of the embodiment of the present application is as follows:

When the level of the A port is pulled high, the transistor NM0 is turned off, and the first control circuit switches the connection channel between the power supply Vdd and the B port within a preset time so that the power supply Vdd is directly connected to the B port, and the power supply Vdd is connected to the B port. Charging, so that the level of the B port is quickly pulled up, thereby improving the signal transmission rate; when the preset time ends, the first control circuit switches the connection channel between the power supply Vdd and the B port to the power supply Vdd through the resistor Rpu and the connection channel. The other port is connected. At this time, the size of the total pull-up resistor is the resistor Rpu, and the level of the B port is determined by the resistor Rpu, so that the signal transmission rate is no longer limited by the pull-up resistor. to adjust the signal transmission rate;

When the level of the A port is pulled low, the transistor NM0 is turned on, the second control circuit turns on the connection between the B port and the ground according to the level change of the A port within a preset time, and the B port discharges to the ground , so that the level of the B port quickly changes from high to low, thereby increasing the signal transmission rate; when the preset time ends, the second control circuit disconnects the connection between the B port and the ground, and after the A port is pulled low, the The current will flow from the power supply Vdd to the ground through the resistor Rpu, the transistor NM0 and the A port. At this time, the level of the B port is the divided voltage between the resistor Rpu, the internal resistance of the transistor NM0 and the internal resistance of the driving circuit connected to the A port. The B port is kept low by the voltage divider.

Since the first control circuit and the second control circuit are provided in the high-speed level conversion circuit of the embodiment of the present application, the level of the other port can be quickly pulled up and down, so that the signal rises or falls faster, which greatly improves the the signal transmission rate.

Further, in the embodiment of the present application, the first control circuit includes a rising edge detection circuit and a transistor PM2; the input end of the rising edge detection circuit is connected to the output end of the unidirectional level conversion circuit, and the output end is connected to the transistor PM2. The gate of the transistor PM2 is connected to the power supply Vdd, and the drain of the transistor PM2 is connected to another port.

Further, in the embodiment of the present application, the second control circuit includes a falling edge detection circuit and a transistor NM2; the input end of the falling edge detection circuit is connected to the output end of the unidirectional level conversion circuit, and the output end is connected to the transistor NM2. The gate of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to another port.

In some other embodiments, the first control circuit and the second control circuit may also be in other structural forms, as long as the functions of quickly pulling up and pulling down the level of another port can be implemented.

Referring to FIG. 3 , the rising edge detection circuit of the embodiment of the present application includes an inverter INV1 and a NAND gate NAND1 connected in sequence, and the input end of the inverter INV1 is connected to the output end of the unidirectional level conversion circuit, The two input terminals of the NAND gate NAND1 are respectively connected to the output terminal of the inverter INV1 and the output terminal of the unidirectional level conversion circuit, and the output terminal of the NAND gate NAND1 is connected to the gate of the transistor PM2.

The falling edge detection circuit of the embodiment of the present application includes an inverter INV2 and a NOR gate NOR1 connected in sequence, the input end of the inverter INV2 is connected to the output end of the unidirectional level conversion circuit, and the NOR gate NOR1 The two input terminals of the NOR gate are respectively connected to the output terminal of the inverter INV2 and the output terminal of the unidirectional level conversion circuit, and the output terminal of the NOR gate NOR1 is connected to the gate of the transistor NM2.

4 , specifically, in the embodiment of the present application, the unidirectional level conversion circuit includes a power supply V1, a power supply V2, a transistor PM10, a transistor NM10, a transistor PM20, a transistor NM20, a transistor PM21, and a transistor NM21, wherein the transistor PM10 and NM10 constitute an inverter in the power domain of V1. The input of the inverter is the input of the unidirectional level conversion circuit, denoted as VI, and the output of the inverter is the connection point of the transistors PM10 and NM10. The position is marked as N10, the gate of transistor NM20 is connected to VI, the source of transistor NM20 is grounded, the drain of transistor NM20 is connected to the drain of transistor PM20 and the gate of transistor PM21, the connection point is marked as N20, transistor NM21 The gate of the transistor NM21 is connected to N10, the source of the transistor NM21 is connected to the ground, the drain of the transistor NM21 is connected to the drain of the transistor PM21, and is used as the output terminal VO of unidirectional level conversion; the gate of the transistor PM20 is connected to VO, and the The source is connected to the power supply V2; the source of the transistor PM21 is connected to the power supply V2.

In the embodiment of the present application, the logic signal VI input by the unidirectional level conversion circuit is in the V1 power domain, and the circuit converts and outputs it as the logic signal VO in the V2 power domain.

In the embodiment of the present application, the working principle of the unidirectional level conversion circuit is:

When VI is high, the inverter output N10 is low. NM21 is turned off, NM20 is turned on, N20 is pulled low, PM21 is turned on, VO is pulled to V2 by PM21, that is, a high level of the V2 power domain is output.

When VI is low, the inverter output N10 is high. NM20 is turned off, NM21 is turned on, VO is pulled low, PM20 is turned on, N20 is pulled to V2 by PM20, PM21 is turned off, and VO is stable at a low level.

Further, in the embodiment of the present application, the first conversion branch further includes a load capacitor C1, one end of the load capacitor C1 is connected to another port, and the other end of the load capacitor C1 is grounded. The load capacitor C1 in the embodiment of the present application can improve the capability of driving the load, so that the performance of the level conversion circuit is better.

Referring to FIG. 5 , further, in the embodiment of the present application, the resistor Rpu includes a resistor Rpub1 and a resistor Rpub2 connected in series, and the conversion unit further includes a third control circuit, the third control circuit and the resistor Rpub2 connected, the third control circuit is configured to adjust the resistance value of the resistor Rpub2 according to the converted level signal.

Since the high-speed level conversion circuit of the embodiment of the present application further includes a third control circuit, the resistance value of Rpub2 can be adjusted according to the converted level signal, so that when the level of the dominant communication port changes from low to high, the resistance value of Rpub2 is reduced. It is advisable to reduce the resistance value of Rpub2 to a value of approximately 0 when the resistance value of Rpub2 is small. At this time, the size of the total pull-up circuit is approximately equal to the resistance value of the resistance Rpub1; when the level of the dominant communication port changes from high to low, Increase the resistance value of the resistor Rpub2. At this time, the size of the total pull-up circuit is approximately equal to the sum of the resistance values of the resistor Rpub1 and the resistor Rpub2. The large resistor Rpub2 can significantly reduce the static current when the two ports are in the low level state. , reduce energy waste and achieve low power consumption. Therefore, the high-speed level conversion circuit can achieve low power consumption and save energy while increasing the signal transmission rate.

Preferably, in the embodiment of the present application, the resistance value of the resistor Rpub2 is selected to be much larger than the resistance value of the resistor Rpub1, so that the power consumption can be better reduced. Usually, the resistance value of the resistor Rpub1 is selected as 5KΩ, and the resistance value of the resistor Rpub2 is 50KΩ.

Specifically, in the embodiment of the present application, the third control circuit includes a reset/set RS flip-flop and a transistor PM4, and two input ends of the RS flip-flop are respectively connected to the output end of the rising edge detection circuit and the falling edge detection circuit. Along the output end of the detection circuit, the output end of the RS flip-flop is connected to the gate of the transistor PM4, and the source and drain of the transistor PM4 are connected to both ends of the resistor Rpub2.

The working principle of the third control circuit in the embodiment of the present application is as follows:

Assume that one port leading the communication is port A and the other port is port B;

When the level of the RS trigger at port A changes from low to high, the RS trigger outputs a low level, and the transistor PM4 is turned on. Since the on-resistance of the transistor PM4 is very small, the resistance Rpub2 can be ignored. At this time, the total The size of the pull circuit is approximately equal to the resistance value of the resistor Rpub1, generally around 5KΩ;

When the level of the RS flip-flop changes from high to low at the A port, the RS flip-flop outputs a high level, and the transistor PM4 is turned off. At this time, the size of the total pull-up circuit is approximately equal to the resistance of the resistor Rpub1 and the resistance of the resistor Rpub2. The sum of the value, that is, about 55KΩ, such a large resistance can significantly reduce the quiescent current of the two ports in a low-level state, reduce energy waste, and achieve low power consumption;

At the same time, when the level of the A port changes from high to low, the current will flow from the resistor Rpub1, the resistor Rpub2, the transistor NM0 and the A port to the ground, and the level of the B port is the sum of the resistor Rpub1 and the resistor Rpub2, and the inside of the transistor NM0. The voltage divider between the resistance and the internal resistance of the driving circuit connected to the A port, since the sum of the resistance Rpub1 and the resistance Rpub2 is much larger than the resistance Rpub1, it can ensure that the low level of the B port is low enough and will not lead to a low level logic judgment. error, the circuit reliability is higher.

As a better implementation manner, the specific manner of the RS flip-flop is as follows: the reset input terminal Reset of the RS flip-flop is connected to the output terminal of the rising edge detection circuit, and the set input terminal Set of the RS flip-flop is connected. It is connected to the output end of the falling edge detection circuit, and the primary end Q of the RS flip-flop is connected to the gate of the transistor PM4.

In the embodiment of the present application, the first control circuit, the second control circuit and the third control circuit are closely connected in addition to realizing their respective independent functions, which makes the structure design of the high-speed level conversion circuit of the present application more ingenious and the structure more compact. to be compact.

Preferably, in the embodiment of the present application, the transistor PM2 and the transistor PM4 are PMOS transistors, and the transistor NM2 is an NMOS transistor.

Referring to FIG. 6 , an embodiment of the present application provides a first high-speed level conversion circuit with two conversion units, which includes two conversion units, and each port is connected to an input end of one conversion unit and another conversion unit 's output.

In this embodiment of the present application, the two conversion units are a first conversion unit and a second conversion unit, respectively. The first conversion unit is used to perform level conversion when the A port is the main communication port, and the second conversion unit is used to perform level conversion when the port A is the main communication port. Level conversion is performed when the B port is the port that dominates the communication.

More specifically, in the embodiment of the present application, both conversion units include a first conversion branch, a first control circuit, a second control circuit, and a unidirectional level conversion circuit.

In the first conversion unit, the first conversion branch includes a power supply Vddb, a resistor Rpub, a load capacitor Clb, and a transistor NM0. The power supply Vddb is grounded after passing through the series-connected resistor Rpub and the load capacitor Clb in sequence, and the gate of the transistor NM0 is grounded. The bias voltage Vbias is connected, the source of the transistor NM0 is connected to the A port, the drain of the transistor NM0 is connected between the resistor Rpub and the load capacitor Clb, and the connection point of the resistor Rpub and the load capacitor Clb is connected to the B port .

In the first conversion unit, one end of the unidirectional level conversion circuit is connected to the A port, and the other end is connected to the input end of the first control circuit and the input end of the second control circuit. The first control circuit includes a rising edge detection circuit and a transistor PM2; the input end of the rising edge detection circuit is connected to the output end of the unidirectional level conversion circuit, and the output end is connected to the gate of the transistor PM2; the source electrode of the transistor PM2 is connected to the power supply Vddb connected, the drain of the transistor PM2 is connected to the other port. The second control circuit includes a falling edge detection circuit and a transistor NM2; the input end of the falling edge detection circuit is connected to the output end of the unidirectional level conversion circuit, and its output end is connected to the gate of the transistor NM2; the source of the transistor NM2 is grounded, and the transistor The drain of NM2 is connected to another port.

Similarly, the second conversion unit includes a power supply Vdda, a transistor PM1, a transistor NM1, a resistor Rpua, a capacitor Cla, etc. The structure and principle process of the second conversion unit are the same as those of the first conversion unit, which will not be repeated here.

It should be noted that, in order to make the circuit structure simpler, the first conversion unit and the second conversion unit only need to share one transistor NM0. In addition, the resistance values of the resistor Rpua and the resistor Rpub in the embodiments of the present application are equivalent to the resistance values of the resistors Rpua1 or Rpua2 commonly used in the prior art, and are usually 5KΩ. The first high-speed level conversion circuit with two conversion units provided by the embodiments of the present application. On the one hand, since the first control circuit and the second control circuit are included, the signal transmission rate can be improved, that is, high-speed level conversion can be realized, and the other is On the one hand, because two conversion units are included, bidirectional level conversion can be realized, and it is applicable to the situation where the A port is the dominant communication and the B port is the dominant communication; The level conversion circuit can realize high-speed and bidirectional conversion functions at the same time.

Referring to FIG. 7 , the embodiment of the present application provides a second type of high-speed level conversion circuit with two conversion units, which includes two conversion units, each port is connected to the input end of one conversion unit, and another conversion unit output of the unit.

In this embodiment of the present application, the two conversion units are a first conversion unit and a second conversion unit, respectively. The first conversion unit is used to perform level conversion when the A port is the main communication port, and the second conversion unit is used to perform level conversion when the port A is the main communication port. Level conversion is performed when the B port is the port that dominates the communication.

More specifically, in the embodiment of the present application, both conversion units include a first conversion branch, a first control circuit, a second control circuit, a third control circuit, and a unidirectional level conversion circuit.

In the first conversion unit, the first conversion branch includes a power supply Vddb, a resistor Rpub, a load capacitor Clb, and a transistor NM0. The power supply Vddb is grounded after passing through the series-connected resistor Rpub and the load capacitor Clb in sequence, and the gate of the transistor NM0 is grounded. The bias voltage is connected, the source of the transistor NM0 is connected to the A port, the drain of the transistor NM0 is connected between the resistor Rpub and the load capacitor Clb, and the connection point of the resistor Rpub and the load capacitor Clb is connected to the B port.

In the first conversion unit, the resistor Rpub includes a resistor Rpub1 and a resistor Rpub2 connected in series. It should be understood that the resistance value of the resistor Rpub1 is equivalent to the resistance value of the resistor Rpua1 or Rpua2 commonly used in the prior art, usually 5KΩ, and the resistor Rpub2 For the newly added resistor, the resistance value is usually 50KΩ, and the resistance value of the resistor Rpub2 is much larger than the resistance value of the Rpub1.

In the first conversion unit, one end of the unidirectional level conversion circuit is connected to the A port, and the other end is connected to the input end of the first control circuit and the input end of the second control circuit. The first control circuit includes a rising edge detection circuit and a transistor PM2; the input end of the rising edge detection circuit is connected to the output end of the unidirectional level conversion circuit, and the output end is connected to the gate of the transistor PM2; the source electrode of the transistor PM2 is connected to the power supply Vddb connected, the drain of the transistor PM2 is connected to the other port. The second control circuit includes a falling edge detection circuit and a transistor NM2; the input end of the falling edge detection circuit is connected to the output end of the unidirectional level conversion circuit, and its output end is connected to the gate of the transistor NM2; the source of the transistor NM2 is grounded, and the transistor The drain of NM2 is connected to another port.

In the first conversion unit, the third control circuit includes a reset/set RS flip-flop and a transistor PM4, the reset input terminal Reset of the RS flip-flop is connected to the output terminal of the rising edge detection circuit, and the RS flip-flop The set input terminal Set is connected to the output terminal of the falling edge detection circuit, and the primary terminal Q of the RS flip-flop is connected to the gate of the transistor PM4, and the source and drain of the transistor PM4 are connected to the two terminals of the resistor Rpub2. end.

Similarly, the second conversion unit includes a power supply Vdda, a transistor PM1, a transistor NM1, a resistor Rpua1, a resistor Rpua2, a capacitor Cla, etc. The structure and principle process of the second conversion unit are the same as those of the first conversion unit, which will not be repeated here.

When the A port dominates the communication, the waveform diagram of the main signals in the second type of high-speed level conversion circuit with two conversion units is shown in Figure 8, where the A signal is the level of the A port, and the S2 signal is the first conversion The output signal of the unidirectional level conversion circuit of the unit, the SP2 signal is the output signal of the rising edge detection circuit of the first conversion unit, the SN2 signal is the output signal of the falling edge detection circuit of the first conversion unit, and the SR2 signal is the first conversion unit. The output signal of the Q terminal of the RS flip-flop, and the B signal is the level signal of the B port.

Referring to Figure 8, it can be seen that when the level of port A changes from low to high, the S2 signal also changes from low to high, the rising edge of the S2 signal is detected, and the SP2 signal is output. Return to high level, the length of time tp is determined by the gate delay of the inverter INV1 in the rising edge detection circuit. During the tp time, PM2 is turned on, and the power supply Vddb charges the B port, so that the level signal of the B port increases rapidly, that is, the B signal becomes high.

After the tp time, PM2 is turned off, and the power supply Vddb maintains the high-level state of the B port through the resistor Rpub1 and the resistor Rpub2.

After the SP2 signal becomes low, the output signal SR2 of the RS flip-flop also becomes low, and PM4 is turned on. At this time, the size of the total pull-up resistor is approximately equal to the resistance value of the resistor Rpub1, which is approximately 5KΩ.

After a period of time, the level signal of port A changes from high to low, and the S2 signal also changes from high to low. The falling edge of S2 is detected, and the SN2 signal is output. After the SN2 signal maintains the logic high of the time tn, it returns automatically. Low level, the length of time tn is determined by the gate delay of the inverter INV2 in the falling edge detection circuit. During the tn time, NM2 is turned on, and the B port is discharged to the ground, so that the level of the B port quickly becomes low, that is, the B signal becomes low.

After tn time, NM2 is turned off, and the low level of port A is maintained at the low level of port B through NM0.

After SN2 becomes high, the output signal SR2 of the RS flip-flop also becomes high, and PM4 is turned off. At this time, the size of the total pull-up resistor is approximately equal to the sum of the resistors Rpub1 and Rpub2, that is, about 55KΩ, such a large resistance can significantly The quiescent current in the low-level state is reduced, and it can also ensure that the level of the B port is low enough to not cause a low-level logic judgment error.

When the B port dominates the communication, the waveform diagram of the main signals in the second type of high-speed level conversion circuit with two conversion units is shown in Figure 9, where the B signal is the level signal of the B port, and the S1 signal is the second The output signal of the unidirectional level conversion circuit of the conversion unit, the SP1 signal is the output signal of the rising edge detection circuit of the second conversion unit, the SN1 signal is the output signal of the falling edge detection circuit of the second conversion unit, and SR1 is the second conversion unit. The output signal of the Q terminal of the RS flip-flop of the unit, the A signal is the level of the A port.

When the B port dominates the communication, the principle process is similar to the principle of the A port leading the communication, and the implementation process is not repeated here.

It should be noted that, in this embodiment of the present application, the first control circuit is used to quickly pull up the level of another port within a preset time, and the preset time of the first control circuit is time tp, and the The length is determined by the gate delay of the inverter INV1 in the rising edge detection circuit. In other embodiments, it may be set according to different configurations of the first control circuit.

The second control circuit is used to quickly pull down the level of the other port within a preset time, the preset time of the second control circuit is time tn, and the length of time tn is determined by the inverter INV2 in the falling edge detection circuit is determined by the gate delay. In other embodiments, it may be set according to different configurations of the second control circuit.

The second kind of high-speed level conversion circuit with two conversion units provided by the embodiment of the present application, on the one hand, since the first control circuit and the second control circuit are included, the signal transmission rate can be improved, that is, high-speed level conversion can be realized, and the other is On the one hand, due to the addition of a large resistance Rpub2, the quiescent current of the two ports in the low-level state is significantly reduced, that is, low-power level conversion is realized; on the other hand, due to the inclusion of two conversion units, bidirectional current can be realized. Level conversion is also applicable to the case where the A port is the dominant communication and the B port is the dominant communication; therefore, the second high-speed level conversion circuit with two conversion units provided by this application can achieve high speed and low power consumption at the same time. , Two-way conversion function.

After testing, compared with the bidirectional level conversion circuit of the prior art in FIG. 1 , the bidirectional level conversion circuit in FIG. 1 can only achieve a rate of 1 Mbps, while the high-speed level conversion circuit of the embodiment of the present application, the increased signal The transmission rate can reach more than 60Mbps, which improves the signal quality and reduces the system power consumption.

In the description of the application, it should be noted that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the application and simplifying the description, It is not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the application. Unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

It should be noted that, in this application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply Any such actual relationship or sequence exists between these entities or operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The above descriptions are only specific embodiments of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, this application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. a high-speed level conversion circuit, which is used to convert the different levels of two ports, it is characterized in that: It includes at least one conversion unit, the input end of the conversion unit is connected to a port that dominates communication, and the output end is connected to another port, and the conversion unit includes: a first conversion branch, which includes a power supply Vdd, a resistor Rpu, and a transistor NM0, the transistor NM0 is connected across the port leading the communication and another port, and the power supply Vdd is connected to the other port through the resistor Rpu; A one-way level conversion circuit, which is used to convert the level of the port that dominates the communication, and output the converted level signal; The first control circuit, the two ends of which are respectively connected to the power supply Vdd and the other port, which is used to control the other port to be directly connected to the power supply Vdd or connected to the power supply Vdd according to the converted level signal, so that the first control circuit Quickly pull up the level of another port within a preset time; The second control circuit, the two ends of which are respectively connected to the other port and the ground, is used to control the turn-on or turn-off between the other port and the ground according to the level signal output by the unidirectional level conversion circuit, so as to make the The second control circuit rapidly pulls down the level of the other port within a preset time. 2. The high-speed level shifting circuit according to claim 1, wherein the first control circuit comprises a rising edge detection circuit and a transistor PM2; The input end of the rising edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end is connected with the gate of the transistor PM2; The source of the transistor PM2 is connected to the power supply Vdd, and the drain of the transistor PM2 is connected to the other port. 3. The high-speed level conversion circuit according to claim 2, wherein the rising edge detection circuit comprises an inverter INV1 and a NAND gate NAND1 connected in sequence, and the input end of the inverter INV1 is connected to the single connected to the output end of the level shift circuit, the two input ends of the NAND gate NAND1 are respectively connected to the output end of the inverter INV1 and the output end of the unidirectional level shift circuit, the output end of the NAND gate NAND1 The terminal is connected to the gate of the transistor PM2. 4. The high-speed level conversion circuit according to claim 2, wherein the second control circuit comprises a falling edge detection circuit and a transistor NM2; The input end of the falling edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end is connected with the gate of the transistor NM2; The source of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to the other port. 5. The high-speed level conversion circuit according to claim 4, wherein the falling edge detection circuit comprises an inverter INV2 and a NOR gate NOR1 connected in sequence, and the input end of the inverter INV2 is connected to the single Connected to the output end of the level shift circuit, the two input ends of the NOR gate NOR1 are respectively connected to the output end of the inverter INV2 and the output end of the unidirectional level shift circuit, the output end of the NOR gate NOR1 The terminal is connected to the gate of the transistor NM2. 6. The high-speed level conversion circuit of claim 1, wherein the first conversion branch further comprises a load capacitor C1, one end of the load capacitor C1 is connected to another port, and the load capacitor C1 is another port. One end is grounded. 7. The high-speed level conversion circuit according to claim 4, wherein the resistor Rpu comprises a resistor Rpub1 and a resistor Rpub2 connected in series, the conversion unit further comprises a third control circuit, the third control circuit is used for The converted level signal adjusts the resistance value of the resistor Rpub2. 8. The high-speed level shift circuit according to claim 7, wherein the third control circuit comprises a reset/set RS flip-flop and a transistor PM4, and two input ends of the RS flip-flop are respectively connected to rise The output terminal of the edge detection circuit and the output terminal of the falling edge detection circuit, the output terminal of the RS flip-flop is connected to the gate of the transistor PM4, and the source and drain of the transistor PM4 are connected to both ends of the resistor Rpub2. 9 . The high-speed level conversion circuit of claim 7 , wherein the resistance value of the resistor Rpu2 is much larger than the resistance value of the resistor Rpu1 . 10 . 10. The high-speed level conversion circuit according to any one of claims 1 to 9, wherein the high-speed level conversion circuit comprises two conversion units, and each port is connected to an input end of one conversion unit and another The output of a conversion unit.

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