CN111669168A - High-speed level switching circuit - Google Patents
High-speed level switching circuit Download PDFInfo
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Abstract
The application relates to a high-speed level shift circuit for shifting different levels of two ports, comprising at least one shift unit, wherein the shift unit comprises a first shift branch, a unidirectional level shift circuit, a first control circuit and a second control circuit, the first shift branch comprises a power supply Vdd, a resistor Rpu and a transistor NM 0; the unidirectional level conversion circuit is used for converting the level of the port for leading communication and outputting a converted level signal; the first control circuit is used for controlling the other port to be directly connected with a power supply Vdd or connected with the power supply Vdd through a resistor Rpu according to the converted level signal; the second control circuit is used for controlling the connection or disconnection between the other port and the ground according to the level signal output by the unidirectional level conversion circuit. The application provides a high-speed level shift circuit, signal rising speed is very fast, signal transmission rate is high when carrying out level shift.
Description
Technical Field
The present invention relates to the field of analog integrated circuit technologies, and in particular, to a high-speed level shifter.
Background
At present, in an electronic circuit design, two digital integrated circuits that communicate with each other often work at different power supply voltages, for example, a first chip works at 1.8V, and a second chip works at 5V, so that the second chip is likely to be unable to correctly receive and judge a logic signal sent from the first chip, and conversely, a signal voltage sent by the second chip is up to 5V, which may cause damage to the first chip, and therefore, a bidirectional level conversion circuit needs to be added between the first chip and the second chip.
Referring to fig. 1, the prior art bidirectional level shift circuit includes a resistor Rpua1, a load capacitor Cla, a resistor Rpub1, a load capacitor Clb, a transistor NM0, an a port for connecting the first chip, and a B port for connecting the second chip, a power supply Vdda is grounded through the resistor Rpua1 and the load capacitor Cla connected in series, a power supply Vddb is grounded through the resistor Rpub1 and the load capacitor Clb connected in series, a gate of the transistor NM0 is connected to a bias voltage, a source and an a port of the transistor NM0 are connected between the resistor Rpua1 and the load capacitor Cla, and a drain and a B port of the transistor NM0 are connected between the resistor Rpub1 and the load capacitor Clb.
In the bidirectional level shift circuit of the prior art, when the level of the a port is pulled down, the transistor NM0 is turned on, and the level of the B port is also pulled down through the transistor NM 0; when the level of the a port is pulled high, the transistor NM0 is turned off, and the level of the B port is pulled to the level of the power supply Vddb through the resistor Rpub1, so that bidirectional level conversion is realized, and a chip connected with the a port and the B port is protected.
However, in the bidirectional level shifter circuit, when the level of the a port is pulled high, the signal voltage can only be raised by the resistor Rpub1, and when the load capacitor Clb is large, the signal rises slowly, so that the bidirectional level shifter circuit can only operate at a signal transmission rate of less than 1Mbps, and cannot meet the development requirement of the current high-speed transmission signal.
Disclosure of Invention
The embodiment of the application provides a high-speed bidirectional level conversion circuit to solve the technical problems of slow signal rising and low signal transmission rate in bidirectional level conversion in the related art.
The application provides a high-speed level switching circuit, it is used for carrying on the conversion to the different level of two ports, it includes at least one switching unit, the input of the switching unit connects a port of leading communication, the output connects another port, the switching unit includes:
a first switching branch comprising a power supply Vdd, a resistor Rpu, a transistor NM0, said transistor NM0 being connected across the port of the dominant communication and the other port, said power supply Vdd being connected to the other port through the resistor Rpu;
the unidirectional level conversion circuit is used for converting the level of the port of the dominant communication and outputting a converted level signal;
the first control circuit is connected with the power supply Vdd and the other port at two ends respectively and used for controlling the other port to be directly connected with the power supply Vdd or connected through a resistor Rpu according to the converted level signal so as to enable the first control circuit to quickly pull up the level of the other port within preset time;
and the two ends of the second control circuit are respectively connected with the other port and the ground, and the second control circuit is used for controlling the connection or disconnection between the other port and the ground according to the level signal output by the unidirectional level conversion circuit so as to enable the second control circuit to quickly pull down the level of the other port within preset time.
In some embodiments, the first control circuit includes a rising edge detection circuit and a transistor PM 2;
the input end of the rising edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the rising edge detection circuit is connected with the grid electrode of the transistor PM 2;
the source of the transistor PM2 is connected to the supply Vdd and the drain of the transistor PM2 is connected to the other port.
In some embodiments, the rising edge detection circuit includes an inverter INV1 and a NAND gate NAND1 connected in sequence, an input terminal of the inverter INV1 is connected to an output terminal of the unidirectional level shift circuit, two input terminals of the NAND gate NAND1 are respectively connected to an output terminal of the inverter INV1 and an output terminal of the unidirectional level shift circuit, and an output terminal of the NAND gate NAND1 is connected to a gate of the transistor PM 2.
In some embodiments, the second control circuit includes a falling edge detection circuit and a transistor NM 2;
the input end of the falling edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the falling edge detection circuit is connected with the grid electrode of the transistor NM 2;
the source of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to the other port.
In some embodiments, the falling edge detection circuit includes an inverter INV2 and a NOR gate NOR1 connected in sequence, an input terminal of the inverter INV2 is connected to an output terminal of the unidirectional level shift circuit, two input terminals of the NOR gate NOR1 are respectively connected to an output terminal of the inverter INV2 and an output terminal of the unidirectional level shift circuit, and an output terminal of the NOR gate NOR1 is connected to a gate of the transistor NM 2. 6. The high speed level shift circuit of claim 1, wherein: the first conversion branch circuit further comprises a load capacitor Cl, one end of the load capacitor Cl is connected with the other port, and the other end of the load capacitor Cl is grounded.
In some embodiments, the resistor Rpu includes a resistor Rpub1 and a resistor Rpub2 connected in series, and the switching unit further includes a third control circuit for adjusting a resistance value of the resistor Rpub2 according to the converted level signal.
In some embodiments, the third control circuit comprises a reset/set RS flip-flop and a transistor PM4, wherein two input terminals of the RS flip-flop are respectively connected with an output terminal of the rising edge detection circuit and an output terminal of the falling edge detection circuit, an output terminal of the RS flip-flop is connected with a gate of the transistor PM4, and a source and a drain of the transistor PM4 are connected with two ends of the resistor Rpub 2.
In some embodiments, the resistance of the resistor Rpu2 is much larger than the resistance of the resistor Rpu 1.
In some embodiments, the high speed level shift circuit includes two shift units, each port connected to an input of one shift unit and an output of the other shift unit.
The beneficial effect that technical scheme that this application provided brought includes: when level conversion is carried out, the signal rising speed is high, and the signal transmission rate is high.
The embodiment of the application provides a high-speed level switching circuit, and due to the fact that the first control circuit and the second control circuit are arranged, the level of the other port can be quickly pulled up and quickly pulled down, so that the signal rising or falling speed is high, and the signal transmission rate is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art bi-directional level shift circuit;
FIG. 2 is a schematic diagram of a high speed level shift circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a rising edge detection circuit and a falling edge detection circuit in an embodiment of the present application;
FIG. 4 is a schematic diagram of a unidirectional level shift circuit in an embodiment of the present application;
FIG. 5 is a schematic diagram of a high speed level shift circuit with a third control circuit provided in an embodiment of the present application;
FIG. 6 is a first high-speed level shifter circuit with two shift units according to an embodiment of the present disclosure;
FIG. 7 is a second high-speed level shifter circuit with two shift units according to an embodiment of the present application;
FIG. 8 is a waveform diagram of the main signals in a second high-speed level shifter circuit with two shift units when the A port is dominating the communication;
fig. 9 is a waveform diagram of main signals in a second high-speed level shift circuit having two shift units when the B port dominates communication.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, the present application provides a high-speed level shift circuit for shifting different levels of two ports, which includes at least one shift unit having an input terminal connected to one port of the master communication and an output terminal connected to the other port.
The conversion unit comprises a first conversion branch circuit, a unidirectional level conversion circuit, a first control circuit and a second control circuit. The first conversion branch comprises a power supply Vdd, a resistor Rpu and a transistor NM0, wherein the transistor NM0 is connected between a port for leading communication and another port in a bridging mode, and the power supply Vdd is connected with the other port through the resistor Rpu; the unidirectional level conversion circuit is used for converting the level of the port for leading communication and outputting a converted level signal; the two ends of the first control circuit are respectively connected with a power supply Vdd and the other port, and the first control circuit is used for controlling the other port to be directly connected with the power supply Vdd or connected through a resistor Rpu according to the converted level signal so as to enable the first control circuit to quickly pull up the level of the other port within preset time; and two ends of the second control circuit are respectively connected with the other port and the ground, and the second control circuit is used for controlling the connection or disconnection between the other port and the ground according to the level signal output by the unidirectional level conversion circuit so as to enable the second control circuit to rapidly pull down the level of the other port within preset time.
It should be noted that, in the embodiment of the present application, the fast pull-up and the fast pull-down should be understood that, compared to the prior art in which one port pulls down the level of the other port through the transistor NM0, and pulls up the level of the other port through the power supply and the resistor, the fast pull-up level in the embodiment of the present application may be performed by the first control circuit, and the fast pull-down level may be performed by the second control circuit. And, the time of pulling high the level through first control circuit is preset, first control circuit pulls high the level in the time of presetting, first control circuit stops pulling high the level outside the time of presetting, the second control circuit principle is similar, no longer repeated.
In the embodiment of the present application, the port that dominates communication is an a port, and the other port is a B port. The working principle of the high-speed level conversion circuit of the embodiment of the application is as follows:
when the level of the port A is pulled high, the transistor NM0 is cut off, the first control circuit switches the connection channel between the power supply Vdd and the port B within a preset time to enable the power supply Vdd to be directly connected with the port B, and the power supply Vdd charges the port B, so that the level of the port B is quickly pulled high, and the signal transmission rate is further improved; after the preset time is over, the first control circuit switches a connecting channel between the power supply Vdd and the port B to enable the power supply Vdd to be connected with the other port through the resistor Rpu, at the moment, the size of the total pull-up resistor is the resistor Rpu, and the level of the port B is determined by the resistor Rpu, so that the signal transmission rate is not limited by the pull-up resistor any more, and the signal transmission rate can be adjusted according to the preset time;
when the level of the port A is pulled down, the transistor NM0 is conducted, the second control circuit conducts the connection between the port B and the ground according to the level change condition of the port A in a preset time, and the port B discharges to the ground, so that the level of the port B is quickly changed from high to low, and the signal transmission rate is further improved; when the preset time is over, the second control circuit disconnects the connection between the port B and the ground, after the port a is pulled down, the current flows from the power supply Vdd to the ground through the resistor Rpu, the transistor NM0 and the port a, at this time, the level of the port B is the divided voltage between the resistor Rpu, the internal resistance of the transistor NM0 and the internal resistance of the driving circuit connected to the port a, and the level of the port B is kept low by the divided voltage.
The high-speed level switching circuit provided by the embodiment of the application can rapidly pull up and rapidly pull down the level of the other port due to the arrangement of the first control circuit and the second control circuit, so that the signal rising or falling speed is high, and the signal transmission rate is greatly improved.
Further, in the embodiment of the present application, the first control circuit includes a rising edge detection circuit and a transistor PM 2; the input end of the rising edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the rising edge detection circuit is connected with the grid electrode of the transistor PM 2; the source of the transistor PM2 is connected to the supply Vdd and the drain of the transistor PM2 is connected to the other port.
Further, in the embodiment of the present application, the second control circuit includes a falling edge detection circuit and a transistor NM 2; the input end of the falling edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the falling edge detection circuit is connected with the grid electrode of the transistor NM 2; the source of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to the other port.
In some other embodiments, the first control circuit and the second control circuit may have other structures as long as the functions of quickly pulling up and pulling down the level of the other port can be achieved.
Referring to fig. 3, the rising edge detection circuit according to the embodiment of the present application includes an inverter INV1 and a NAND gate NAND1 connected in sequence, an input end of the inverter INV1 is connected to an output end of the unidirectional level shift circuit, two input ends of the NAND gate NAND1 are respectively connected to an output end of the inverter INV1 and an output end of the unidirectional level shift circuit, and an output end of the NAND gate NAND1 is connected to a gate of the transistor PM 2.
The falling edge detection circuit of the embodiment of the application comprises a phase inverter INV2 and a NOR gate NOR1 which are connected in sequence, wherein the input end of the phase inverter INV2 is connected with the output end of the unidirectional level conversion circuit, the two input ends of the NOR gate NOR1 are respectively connected with the output end of the phase inverter INV2 and the output end of the unidirectional level conversion circuit, and the output end of the NOR gate NOR1 is connected with the grid electrode of a transistor NM 2.
Referring to fig. 4, specifically, in the embodiment of the present application, the unidirectional level shift circuit includes a power supply V1, a power supply V2, a transistor PM10, a transistor NM10, a transistor PM20, a transistor NM20, a transistor PM21, and a transistor NM21, where the transistors PM10 and NM10 constitute an inverter of a V1 power domain, an input terminal of the inverter is an input terminal of the unidirectional level shift circuit, denoted by VI, an output terminal of the inverter is a connection point position of the transistors PM10 and NM10, denoted by N10, a gate of the transistor NM20 is connected to VI, a source of the transistor NM20 is connected to ground, a drain of the transistor NM20 is connected to both a drain of the transistor PM20 and a gate of the transistor PM21, the connection point is denoted by N20, a gate of the transistor NM21 is connected to N10, a source of the transistor NM21 is connected to ground, a drain of the transistor NM21 is connected to the drain of the transistor PM 21; the gate of the transistor PM20 is connected with VO, and the source of the transistor PM20 is connected with the power supply V2; the source of the transistor PM21 is connected to the power supply V2.
In the embodiment of the application, the logic signal VI input by the unidirectional level shift circuit is in the V1 power domain, and the unidirectional level shift circuit shifts and outputs the logic signal VI as a logic signal VO in the V2 power domain.
In the embodiment of the application, the working principle of the unidirectional level conversion circuit is as follows:
when VI is high, the inverter output N10 is low. NM21 is off, NM20 is on, pulling N20 low, PM21 is on, VO is pulled by PM21 to V2, i.e., a high level of the V2 power supply domain is output.
When VI is low, the inverter output N10 is high. NM20 is off, NM21 is on, pulling VO low, PM20 is on, N20 is pulled by PM20 to V2, PM21 is off, and VO is stabilized at low.
Furthermore, in this embodiment, the first converting branch further includes a load capacitor Cl, one end of the load capacitor Cl is connected to the other port, and the other end of the load capacitor Cl is grounded. The load capacitor Cl of the embodiment of the application can improve the load driving capacity, so that the level conversion circuit has better performance.
Referring to fig. 5, in the embodiment of the present application, the resistor Rpu includes a resistor Rpub1 and a resistor Rpub2 connected in series, and the switching unit further includes a third control circuit connected to the resistor Rpub2, and the third control circuit is configured to adjust a resistance of the resistor Rpub2 according to the level signal after switching.
The high-speed level conversion circuit of the embodiment of the application further comprises a third control circuit, and the resistance value of Rpub2 can be adjusted according to the converted level signal, so that when the level of the leading communication port changes from low to high, the resistance value of Rpub2 is reduced, preferably, the resistance value of Rpub2 is reduced to be approximately equal to 0, and at the moment, the size of the total pull-up circuit is approximately equal to the resistance value of Rpub 1; when the level of the leading communication port is changed from high to low, the resistance value of the resistor Rpub2 is increased, at the moment, the size of the total pull-up circuit is approximately equal to the sum of the resistance values of the resistor Rpub1 and the resistor Rpub2, the static current of the two ports in a low level state can be obviously reduced through the large resistor Rpub2, energy waste is reduced, and low power consumption is achieved. Therefore, the high-speed level conversion circuit can realize low power consumption and energy saving while improving the signal transmission rate.
Preferably, in the embodiment of the present application, the resistance of the resistor Rpub2 is selected to be much larger than that of the resistor Rpub1, so as to reduce power consumption better. In general, the resistance of the resistor Rpub1 is selected to be 5K Ω, and the resistance of the resistor Rpub2 is selected to be 50K Ω.
Specifically, in the embodiment of the present application, the third control circuit includes a reset/set RS flip-flop whose two input terminals are connected to the output terminal of the rising edge detection circuit and the output terminal of the falling edge detection circuit, respectively, and a transistor PM4 whose output terminal is connected to the gate of the transistor PM4, and the source and drain of the transistor PM4 are connected to both ends of the resistor Rpub 2.
The working principle of the third control circuit of the embodiment of the application is as follows:
assuming that one port for leading communication is an A port, and the other port is a B port;
when the level of the port A of the RS trigger is changed from low to high, the RS trigger outputs low level, the transistor PM4 is conducted, the on-resistance of the transistor PM4 is very small, the resistance Rpub2 can be ignored, and at the moment, the size of the total pull-up circuit is approximately equal to the resistance value of the resistance Rpub1 and is generally about 5K omega;
when the level of the port A of the RS trigger is changed from high to low, the RS trigger outputs high level, the transistor PM4 is cut off, at the moment, the size of the total pull-up circuit is approximately equal to the sum of the resistance value of the resistor Rpub1 and the resistance value of the resistor Rpub2, namely about 55K omega, and the large resistor can obviously reduce the static current of the two ports in a low level state, reduce energy waste and realize low power consumption;
meanwhile, when the level of the port A is changed from high to low, current can flow to the ground from the resistor Rpub1, the resistor Rpub2, the transistor NM0 and the port A, the level of the port B is the voltage division between the sum of the resistor Rpub1 and the resistor Rpub2, the internal resistance of the transistor NM0 and the internal resistance of a driving circuit connected with the port A, and the sum of the resistor Rpub1 and the resistor Rpub2 is much larger than the resistor Rpub1, so that the low level of the port B can be ensured to be low enough, the logic judgment error of the low level cannot be caused, and the reliability of the circuit is higher.
As a better implementation manner, the specific manner of the RS flip-flop is: the Reset input end Reset of the RS trigger is connected with the output end of the rising edge detection circuit, the Set input end Set of the RS trigger is connected with the output end of the falling edge detection circuit, and the primary end Q of the RS trigger is connected with the grid electrode of the transistor PM 4.
In the embodiment of the application, the first control circuit, the second control circuit and the third control circuit are closely connected besides realizing respective independent functions, so that the high-speed level conversion circuit is more ingenious in structural design and more compact in structure.
Preferably, in the embodiment of the present application, the transistors PM2 and PM4 are PMOS transistors, and the transistor NM2 is an NMOS transistor.
Referring to fig. 6, the present embodiment provides a first high-speed level shift circuit having two shift units, which includes two shift units, and each port is connected to an input terminal of one shift unit and an output terminal of another shift unit.
In this embodiment, the two conversion units are a first conversion unit and a second conversion unit, respectively, the first conversion unit is configured to perform level conversion when the port a is a port for dominant communication, and the second conversion unit is configured to perform level conversion when the port B is a port for dominant communication.
More specifically, in the embodiment of the present application, each of the two conversion units includes a first conversion branch, a first control circuit, a second control circuit, and a unidirectional level conversion circuit.
In the first conversion unit, the first conversion branch comprises a power supply Vddb, a resistor Rpub, a load capacitor Clb and a transistor NM0, wherein the power supply Vddb is grounded after sequentially passing through the resistor Rpub and the load capacitor Clb which are connected in series, the gate of the transistor NM0 is connected with a bias voltage Vbias, the source of the transistor NM0 is connected with an A port, the drain of the transistor NM0 is connected between the resistor Rpub and the load capacitor Clb, and the connection point of the resistor Rpub and the load capacitor Clb is connected with a B port.
In the first conversion unit, one end of the unidirectional level conversion circuit is connected with the port A, and the other end of the unidirectional level conversion circuit is connected with the input end of the first control circuit and the input end of the second control circuit. The first control circuit includes a rising edge detection circuit and a transistor PM 2; the input end of the rising edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the rising edge detection circuit is connected with the grid electrode of the transistor PM 2; the source of transistor PM2 is connected to the power supply Vddb and the drain of transistor PM2 is connected to the other port. The second control circuit includes a falling edge detection circuit and a transistor NM 2; the input end of the falling edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the falling edge detection circuit is connected with the grid electrode of the transistor NM 2; the source of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to the other port.
Similarly, the second converting unit includes a power supply Vdda, a transistor PM1, a transistor NM1, a resistor Rpua, a capacitor Cla, and the like, and the structure and principle process of the second converting unit are as the first converting unit, which are not described herein again.
In order to simplify the circuit configuration, the first conversion unit and the second conversion unit may share one transistor NM 0. In addition, the resistances of the resistor Rpua and the resistor Rpub in the embodiment of the present application are equivalent to the resistance of the resistor Rpua1 or Rpua2 commonly used in the prior art, and are usually 5K Ω. In the first high-speed level shift circuit with two shift units provided in the embodiment of the present application, on one hand, since the first control circuit and the second control circuit are included, the signal transmission rate can be increased, that is, high-speed level shift is realized, and on the other hand, since the two shift units are included, bidirectional level shift can be realized, and the first high-speed level shift circuit is suitable for the case where the port a is the dominant communication and the port B is the dominant communication; therefore, the first high-speed level shift circuit with two shift units provided by the present application can simultaneously realize the high-speed and bidirectional shift functions.
Referring to fig. 7, the embodiment of the present application provides a second high-speed level shift circuit with two shift units, which includes two shift units, and each port is connected to an input terminal of one shift unit and an output terminal of the other shift unit.
In this embodiment, the two conversion units are a first conversion unit and a second conversion unit, respectively, the first conversion unit is configured to perform level conversion when the port a is a port for dominant communication, and the second conversion unit is configured to perform level conversion when the port B is a port for dominant communication.
More specifically, in the embodiment of the present application, each of the two conversion units includes a first conversion branch, a first control circuit, a second control circuit, a third control circuit, and a unidirectional level conversion circuit.
In the first conversion unit, the first conversion branch comprises a power supply Vddb, a resistor Rpub, a load capacitor Clb and a transistor NM0, wherein the power supply Vddb is grounded after sequentially passing through the resistor Rpub and the load capacitor Clb which are connected in series, the gate of the transistor NM0 is connected with a bias voltage, the source of the transistor NM0 is connected with an A port, the drain of the transistor NM0 is connected between the resistor Rpub and the load capacitor Clb, and the connection point of the resistor Rpub and the load capacitor Clb is connected with a B port.
In the first conversion unit, the resistor Rpub includes a resistor Rpub1 and a resistor Rpub2 connected in series, it should be understood that the resistance of the resistor Rpub1 is equivalent to that of the resistor Rpua1 or Rpua2 commonly used in the prior art, typically 5K Ω, the resistor Rpub2 is a newly added resistor, typically 50K Ω, and the resistance of the resistor Rpub2 is much larger than that of the resistor Rpub 1.
In the first conversion unit, one end of the unidirectional level conversion circuit is connected with the port A, and the other end of the unidirectional level conversion circuit is connected with the input end of the first control circuit and the input end of the second control circuit. The first control circuit includes a rising edge detection circuit and a transistor PM 2; the input end of the rising edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the rising edge detection circuit is connected with the grid electrode of the transistor PM 2; the source of transistor PM2 is connected to the power supply Vddb and the drain of transistor PM2 is connected to the other port. The second control circuit includes a falling edge detection circuit and a transistor NM 2; the input end of the falling edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the falling edge detection circuit is connected with the grid electrode of the transistor NM 2; the source of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to the other port.
In the first conversion unit, the third control circuit comprises a Reset/Set RS flip-flop and a transistor PM4, a Reset input Reset of the RS flip-flop is connected with an output end of the rising edge detection circuit, a Set input Set of the RS flip-flop is connected with an output end of the falling edge detection circuit, a primary terminal Q of the RS flip-flop is connected with a gate of the transistor PM4, and a source and a drain of the transistor PM4 are connected to two ends of the resistor Rpub 2.
Similarly, the second conversion unit includes a power supply Vdda, a transistor PM1, a transistor NM1, a resistor Rpua1, a resistor Rpua2, a capacitor Cla, and the like, and the structure and principle process of the second conversion unit are as the first conversion unit, which are not described herein again.
When the a port dominates the communication, the waveform diagram of the main signals in the second high-speed level shift circuit with two shift units is shown in fig. 8, where the a signal is the level of the a port, the S2 signal is the output signal of the unidirectional level shift circuit of the first shift unit, the SP2 signal is the output signal of the rising edge detection circuit of the first shift unit, the SN2 signal is the output signal of the falling edge detection circuit of the first shift unit, the SR2 signal is the output signal of the Q terminal of the RS flip-flop of the first shift unit, and the B signal is the level signal of the B port.
Referring to fig. 8, when the level of the a port is changed from low to high, the S2 signal is also changed from low to high, the rising edge of the S2 signal is detected and outputs the SP2 signal, the SP2 signal automatically returns to high after holding logic low for a time tp, and the time tp is determined by the gate delay of the inverter INV1 in the rising edge detection circuit. In the time tp, the PM2 is turned on, and the power supply Vddb charges the B port, so that the level signal of the B port is rapidly raised, that is, the B signal goes high.
After the time tp, the PM2 is turned off, and the power supply Vddb maintains the high state of the B port through the resistor Rpub1 and the resistor Rpub 2.
When the SP2 signal goes low, the output signal SR2 of the RS flip-flop also goes low, and PM4 is turned on, and the total pull-up resistor is equal to the resistance of the resistor Rpub1, i.e., 5K Ω.
When a period of time elapses, the level signal of the a port changes from high to low, the S2 signal also changes from high to low, the falling edge of S2 is detected and outputs the SN2 signal, the SN2 signal automatically returns to low after being kept at logic high for a time tn, and the length of the time tn is determined by the gate delay of the inverter INV2 in the falling edge detection circuit. During time tn, NM2 is turned on and the B port discharges to ground, causing the level of the B port to go low quickly, i.e., the B signal goes low.
After tn, NM2 is turned off, and the low level of the a port maintains the low state of the B port through NM 0.
After the SN2 goes high, the output signal SR2 of the RS flip-flop goes high, and the PM4 is turned off, at this time, the total pull-up resistance is approximately equal to the sum of the resistance Rpub1 and the resistance Rpub2, i.e., approximately 55K Ω, such a large resistance can significantly reduce the static current in the low level state, and it can also ensure that the level of the B port is low enough, which will not cause a logic determination error in the low level.
When the B port dominates the communication, the waveform diagram of the main signals in the second high-speed level shift circuit with two switching units is shown in fig. 9, where the B signal is the level signal of the B port, the S1 signal is the output signal of the unidirectional level shift circuit of the second switching unit, the SP1 signal is the output signal of the rising edge detection circuit of the second switching unit, the SN1 signal is the output signal of the falling edge detection circuit of the second switching unit, the SR1 signal is the output signal of the Q terminal of the RS flip-flop of the second switching unit, and the a signal is the level of the a port.
When the port B dominates the communication, the principle process is similar to the principle of the port a dominates the communication, and the implementation process is not described herein again.
It should be noted that, in the embodiment of the present application, the first control circuit is configured to pull up the level of the other port quickly within a preset time, where the preset time of the first control circuit is a time tp, and a length of the time tp is determined by a gate delay of the inverter INV1 in the rising edge detection circuit. In other embodiments, the setting may be performed according to a different configuration of the first control circuit.
The second control circuit is used for rapidly pulling down the level of the other port within a preset time, the preset time of the second control circuit is time tn, and the length of the time tn is determined by the gate delay of the inverter INV2 in the falling edge detection circuit. In other embodiments, the setting may be performed according to a different configuration of the second control circuit.
In the second high-speed level shift circuit with two shift units provided in the embodiment of the present application, on one hand, the first control circuit and the second control circuit can improve the signal transmission rate, that is, implement high-speed level shift, and on the other hand, the newly increased resistance Rpub2 significantly reduces the quiescent current of the two ports in the low level state, that is, implement low power consumption level shift; moreover, the two conversion units are included, so that bidirectional level conversion can be realized, and the bidirectional level conversion device is suitable for the condition that the port A is used for leading communication and the port B is used for leading communication; therefore, the second high-speed level shift circuit with two shift units provided by the present application can simultaneously realize the functions of high speed, low power consumption and bidirectional shift.
Through tests, compared with the bidirectional level conversion circuit in the prior art in fig. 1, the bidirectional level conversion circuit in fig. 1 can only realize the rate of 1Mbps, but the high-speed level conversion circuit in the embodiment of the application can improve the signal transmission rate to be more than 60Mbps, improve the signal quality and reduce the system power consumption.
In the description of the present application, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A high speed level shift circuit for shifting different levels of two ports, comprising:
the switching unit comprises at least one switching unit, wherein the input end of the switching unit is connected with one port for leading communication, the output end of the switching unit is connected with the other port, and the switching unit comprises:
a first switching branch comprising a power supply Vdd, a resistor Rpu, a transistor NM0, said transistor NM0 being connected across the port of the dominant communication and the other port, said power supply Vdd being connected to the other port through the resistor Rpu;
the unidirectional level conversion circuit is used for converting the level of the port of the dominant communication and outputting a converted level signal;
the first control circuit is connected with the power supply Vdd and the other port at two ends respectively and used for controlling the other port to be directly connected with the power supply Vdd or connected through a resistor Rpu according to the converted level signal so as to enable the first control circuit to quickly pull up the level of the other port within preset time;
and the two ends of the second control circuit are respectively connected with the other port and the ground, and the second control circuit is used for controlling the connection or disconnection between the other port and the ground according to the level signal output by the unidirectional level conversion circuit so as to enable the second control circuit to quickly pull down the level of the other port within preset time.
2. The high speed level shift circuit of claim 1 in which said first control circuit comprises a rising edge detection circuit and a transistor PM 2;
the input end of the rising edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the rising edge detection circuit is connected with the grid electrode of the transistor PM 2;
the source of the transistor PM2 is connected to the supply Vdd and the drain of the transistor PM2 is connected to the other port.
3. The high speed level shift circuit of claim 2, wherein: the rising edge detection circuit comprises an inverter INV1 and a NAND gate NAND1 which are sequentially connected, wherein the input end of the inverter INV1 is connected with the output end of the unidirectional level conversion circuit, two input ends of the NAND gate NAND1 are respectively connected with the output end of the inverter INV1 and the output end of the unidirectional level conversion circuit, and the output end of the NAND gate 1 is connected with the grid of the transistor PM 2.
4. The high speed level shift circuit according to claim 2, wherein said second control circuit includes a falling edge detection circuit and a transistor NM 2;
the input end of the falling edge detection circuit is connected with the output end of the unidirectional level conversion circuit, and the output end of the falling edge detection circuit is connected with the grid electrode of the transistor NM 2;
the source of the transistor NM2 is grounded, and the drain of the transistor NM2 is connected to the other port.
5. The high speed level shift circuit of claim 4, wherein: the falling edge detection circuit comprises an inverter INV2 and a NOR gate NOR1 which are connected in sequence, wherein the input end of the inverter INV2 is connected with the output end of the unidirectional level conversion circuit, two input ends of the NOR gate NOR1 are respectively connected with the output end of the inverter INV2 and the output end of the unidirectional level conversion circuit, and the output end of the NOR gate NOR1 is connected with the grid electrode of the transistor NM 2.
6. The high speed level shift circuit of claim 1, wherein: the first conversion branch circuit further comprises a load capacitor Cl, one end of the load capacitor Cl is connected with the other port, and the other end of the load capacitor Cl is grounded.
7. The high speed level shift circuit of claim 4, wherein: the resistor Rpu includes a resistor Rpub1 and a resistor Rpub2 connected in series, and the conversion unit further includes a third control circuit for adjusting a resistance value of the resistor Rpub2 according to the converted level signal.
8. The high speed level shift circuit of claim 7, wherein: the third control circuit comprises a reset/set RS trigger and a transistor PM4, two input ends of the RS trigger are respectively connected with an output end of the rising edge detection circuit and an output end of the falling edge detection circuit, an output end of the RS trigger is connected with a grid electrode of the transistor PM4, and a source electrode and a drain electrode of the transistor PM4 are connected with two ends of the resistor Rpub 2.
9. The high speed level shift circuit of claim 7, wherein: the resistance value of the resistor Rpu2 is far larger than that of the resistor Rpu 1.
10. A high speed level shifter circuit as claimed in any one of claims 1 to 9, wherein the high speed level shifter circuit includes two shifter units, each port connected to an input of one shifter unit and an output of the other shifter unit.
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| CN202010570622.3A CN111669168A (en) | 2020-06-18 | 2020-06-18 | High-speed level switching circuit |
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| CN202010570622.3A CN111669168A (en) | 2020-06-18 | 2020-06-18 | High-speed level switching circuit |
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| CN118074702A (en) * | 2024-04-24 | 2024-05-24 | 瓴科微(上海)集成电路有限责任公司 | Edge detection acceleration level conversion circuit |
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Application publication date: 20200915 |