WO2020164434A1

WO2020164434A1 - Bidirectional level conversion circuit and bidirectional level conversion chip

Info

Publication number: WO2020164434A1
Application number: PCT/CN2020/074417
Authority: WO
Inventors: 董渊; 王云松; 黄建刚; 程剑涛; 孙洪军
Original assignee: 上海艾为电子技术股份有限公司
Priority date: 2019-02-14
Filing date: 2020-02-06
Publication date: 2020-08-20
Also published as: CN109687862A

Abstract

A bidirectional level conversion circuit and a bidirectional level conversion chip, the circuit comprising a signal transmission tube (MN), a first pull-up tube (MP1), a second pull-up tube (MP2), and a pull-up control module. The first end of the first pull-up tube (MP1) is electrically connected to a first voltage terminal (VA), and the second end is electrically connected to the first end of the signal transmission tube (MN); the first end of the second pull-up tube (MP2) is electrically connected to a second voltage terminal (VB), and the second end is electrically connected to the second end of the signal transmission tube (MN); and a first signal input end of the pull-up control module is electrically connected to the first end of the signal transmission tube (MN), a second signal input end is electrically connected to the second end of the signal transmission tube (MN), and the output end is electrically connected to the gates of the first pull-up tube (MP1) and the second pull-up tube (MP2) to output a first level pulse when any one of the first and second ends of the signal transmission tube (MN) is converted from the first level to the second level. The two pull-up tubes are controlled by one single pull-up control module, so that not only can the number of modules be decreased and the design complexity be lowered, the chip area and the cost can also be reduced.

Description

Bidirectional level conversion circuit and bidirectional level conversion chip

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on February 14, 2019, the application number is CN201910115541.1, and the invention title is "a two-way level conversion circuit and a two-way level conversion chip", all of which The content is incorporated in this application by reference.

Technical field

The invention relates to the technical field of semiconductor integrated circuits, and more specifically to a bidirectional level conversion circuit and a bidirectional level conversion chip.

Background technique

Level conversion chips are one of the common chip types in integrated circuits, which are widely used in systems such as data transmission, logic control, and digital-to-analog conversion. The function of the level conversion chip is to transfer the logic level signal under the lower voltage domain at one end to the higher voltage domain at the other end, or to transfer the logic level signal under the higher voltage domain at one end to the higher voltage domain at the other end. In the low-voltage domain, and minimize the transmission delay during the transmission process, while maintaining the integrity of the signal.

In order to reduce the delay of level conversion, it is usually necessary to add a fast pull-up tube at the output end. In order to reduce the power consumption caused by the continuous conduction of the pull-up tube, a control module is usually used to control the conduction and shutdown of the pull-up tube. However, in the bidirectional level conversion chip, two pull-up tubes and two control modules need to be added, which not only increases the number of modules and design complexity, but also increases the chip area and cost.

Summary of the invention

In view of this, the present invention provides a bidirectional detection control circuit and a bidirectional level conversion chip to reduce the number of modules and design complexity, and reduce chip area and cost.

In order to achieve the above objectives, the present invention provides the following technical solutions:

A bidirectional level conversion circuit includes a signal transmission tube, a first pull-up tube, a second pull-up tube, and a pull-up control module;

The first end of the first pull-up tube is electrically connected with a first voltage terminal, the second end of the first pull-up tube is electrically connected with the first end of the signal transmission tube, and the second pull-up tube The first end of the second end is electrically connected to the second voltage end, and the second end of the second pull-up tube is electrically connected to the second end of the signal transmission tube;

The first signal input end of the pull-up control module is electrically connected to the first end of the signal transmission tube, and the second signal input end of the pull-up control module is electrically connected to the second end of the signal transmission tube, The output end of the pull-up control module is electrically connected to the grids of the first pull-up tube and the second pull-up tube;

The pull-up control module is used for outputting a first level pulse when any one of the first end and the second end of the signal transmission tube is inverted from the first level to the second level to control the first upper end The pull tube and the second upper pull tube are connected to pull the other end of the first end and the second end from the first level to the second level.

Optionally, the pull-up control module includes a first signal input terminal, a second signal input terminal, a port detection module, a bidirectional detection trigger module, and a single pulse generation module;

The port detection module is electrically connected to the first signal input terminal and the second signal input terminal, and is configured to output when the first signal input terminal and the second signal input terminal are both at the second level A first level, output a second level when at least one of the first signal input terminal and the second signal input terminal is at the first level;

The two-way detection trigger module is electrically connected to the first signal input terminal and the second signal input terminal, and is used for when both the first signal input terminal and the second signal input terminal are at the first level, Output a second level, and output the first level when at least one of the first signal input terminal and the second signal input terminal is at the second level;

The single pulse generation module is electrically connected to the port detection module and the bidirectional detection trigger module, and is configured to output a second level at the port detection module, and the output of the bidirectional detection trigger module is converted from the second level When it is the first level, the first level pulse is output, and the second level is output in other periods.

Optionally, the port detection module includes a NAND gate and a first inverter to a fourth inverter;

The input terminal of the first inverter is electrically connected to the first signal input terminal, the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the second inverter is electrically connected to the output terminal of the first inverter. The output terminal of the phase converter is electrically connected with an input terminal of the NAND gate;

The input terminal of the third inverter is electrically connected to the second signal input terminal, the input terminal of the fourth inverter is electrically connected to the output terminal of the third inverter, and the fourth inverter is electrically connected to the output terminal of the third inverter. The output terminal of the phase converter is electrically connected to the other input terminal of the NAND gate;

The output terminal of the NAND gate is electrically connected with the output terminal of the port detection module.

Optionally, the bidirectional detection trigger module includes an OR gate, a first transistor to a fifth transistor, a fifth inverter, and a sixth inverter;

One input terminal of the OR gate is electrically connected to the first signal input terminal, the other input terminal of the OR gate is electrically connected to the second signal input terminal, and the output terminal of the OR gate is electrically connected to the first signal input terminal. The gate of a transistor is electrically connected;

The first terminal of the first transistor is electrically connected to the second terminal of the second transistor, the first terminal of the second transistor is electrically connected to the power terminal, and the second terminal of the first transistor is electrically connected to the third transistor. The second terminal of the third transistor is electrically connected to the first signal input terminal, and the first terminal of the third transistor is electrically connected to the ground terminal;

The second end of the first transistor is electrically connected to the second end of the fourth transistor, and the second end of the fourth transistor is electrically connected to the gate of the fourth transistor through a fifth inverter. The gate of the four transistors is electrically connected to the gate of the second transistor through a sixth inverter;

The gate of the fifth transistor is electrically connected to the second signal input terminal, the first terminal of the fifth transistor is electrically connected to the ground terminal, and the second terminal of the fifth transistor is electrically connected to the fourth transistor. The second end is electrically connected;

The second terminal of the fourth transistor is electrically connected to the output terminal of the bidirectional detection trigger module.

Optionally, the first transistor, the second transistor, and the fourth transistor are PMOS transistors, and the third transistor and the fifth transistor are NMOS transistors.

Optionally, the single pulse generating module includes a sixth transistor to an eighth transistor, a first resistor, a second resistor, a seventh inverter, an eighth inverter, a ninth inverter, and a NOR gate;

The first terminal of the sixth transistor is electrically connected to the power terminal, the gate of the sixth transistor is electrically connected to the output terminal of the bidirectional detection trigger module, and the second terminal of the sixth transistor is electrically connected to the first terminal. One end of the resistor is electrically connected, the other end of the first resistor is electrically connected to one end of the second resistor, the other end of the second resistor is electrically connected to the first end of the seventh transistor, and the seventh The second terminal of the transistor is electrically connected to the ground terminal, and the gate of the seventh transistor is electrically connected to the output terminal of the bidirectional detection trigger module;

The gate of the eighth transistor is electrically connected to the output end of the port detection module, the first end of the eighth transistor is electrically connected to one end of the first resistor, and the second end of the eighth transistor is electrically connected to The other end of the first resistor is electrically connected;

The input end of the seventh inverter is electrically connected to the other end of the second resistor, the output end of the seventh inverter is electrically connected to the input end of the eighth inverter, and the eighth The output terminal of the inverter is electrically connected with one input terminal of the NOR gate, the output terminal of the bidirectional detection trigger module is electrically connected with the other input terminal of the NOR gate, and the output terminal of the NOR gate It is electrically connected to the input terminal of the ninth inverter, and the output terminal of the ninth inverter is electrically connected to the output terminal of the single pulse generation module.

Optionally, the sixth transistor and the eighth transistor are PMOS transistors, and the seventh transistor is an NMOS transistor.

Optionally, the first pull-up tube and the second pull-up tube are PMOS transistors; the first level is a low level, and the second level is a high level.

Optionally, it further includes a driving circuit;

The driving circuit is used for controlling the signal transmission tube to be turned on when both ends of the signal transmission tube are at the first level.

A bidirectional level conversion chip includes the bidirectional level conversion circuit as described above.

Compared with the prior art, the technical solution provided by the present invention has the following advantages:

In the bidirectional level conversion circuit and the bidirectional level conversion chip provided by the present invention, the pull-up control module outputs the first level when any one of the first end and the second end of the signal transmission tube is turned from the first level to the second level A level pulse controls the conduction of the first pull-up tube and the second pull-up tube, and pulls the other end of the first end and the second end from the first level to the second level, that is, in the present invention The first pull-up tube and the second pull-up tube are controlled by a pull-up control module, thereby not only reducing the number of modules and design complexity, but also reducing chip area and cost.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative work.

Fig. 1 is a schematic structural diagram of an existing bidirectional level conversion circuit;

2 is a schematic structural diagram of a bidirectional level conversion circuit provided by an embodiment of the present invention;

Figure 3 is a schematic structural diagram of a pull-up control module provided by an embodiment of the present invention;

Fig. 4 is a signal timing diagram of a pull-up control module provided by an embodiment of the present invention.

detailed description

As described in the background art, in the existing bidirectional level conversion chip, two pull-up tubes and two control modules need to be added. As shown in Figure 1, Figure 1 is a schematic structural diagram of an existing bidirectional level conversion chip. When the first end A of the signal transmission tube MN is turned from the first level to the second level, the second control module controls The second pull-up tube MP2 is turned on to pull the second terminal B of the signal transmission terminal MN from the first level to the second level; when the second terminal B of the signal transmission tube MN is switched from the first level to the second level At the level, the first control module controls the first pull-up tube MP1 to be turned on, and pulls the first end A of the signal transmission terminal MN from the first level to the second level. Since the two pull-up tubes in Fig. 1 are respectively controlled by the control module, this not only increases the number of modules and design complexity, but also increases the chip area and cost.

Based on this, the present invention provides a bidirectional level conversion circuit to overcome the above-mentioned problems in the prior art, including a signal transmission tube, a first pull-up tube, a second pull-up tube and a pull-up control module;

The first signal input terminal of the pull-up control module is electrically connected with the first end of the signal transmission tube, and the second signal input terminal of the pull-up control module is electrically connected with the second end of the signal transmission tube; The output terminal of the bidirectional detection control circuit is electrically connected to the grids of the first pull-up tube and the second pull-up tube;

In the bidirectional level conversion circuit provided by the present invention, the pull-up control module outputs a first level pulse to control the first level when either end of the first end and the second end of the signal transmission tube is switched from the first level to the second level. A pull-up tube and a second pull-up tube are turned on, and the other end of the first end and the second end is pulled from the first level to the second level. That is to say, the first pull-up tube and the second pull-up tube in the present invention Second, the pull-up tube is controlled by a pull-up control module, which not only reduces the number of modules and design complexity, but also reduces chip area and cost.

The above is the core idea of the present invention. In order to make the above objectives, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Description, obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

The embodiment of the present invention provides a bidirectional level conversion circuit, which can be applied to a level conversion chip, a logic control chip, a data transmission chip, etc., as shown in FIG. 2, the bidirectional level conversion circuit includes The signal transmission tube MN, the first pull-up tube MP1, the second pull-up tube MP2 and the pull-up control module.

The first end of the first pull-up tube MP1 is electrically connected to the first voltage terminal VA, the second end of the first pull-up tube MP1 is electrically connected to the first end A of the signal transmission tube MN, and the second pull-up tube MP2 The first end of is electrically connected to the second voltage terminal VB, and the second end of the second pull-up tube MP2 is electrically connected to the second end B of the signal transmission tube MN;

The first signal input end LA of the pull-up control module is electrically connected to the first end A of the signal transmission tube MN, and the second signal input end LB of the pull-up control module is electrically connected to the second end B of the signal transmission tube MN, and the pull-up The output terminal LOUT of the control module is electrically connected to the grids of the first pull-up tube MP1 and the second pull-up tube MP2;

The pull-up control module is used to output the first level pulse when either end of the first end A and the second end B of the signal transmission tube MN is switched from the first level to the second level, that is, the output duration is t The first level controls the conduction of the first pull-up tube MP1 and the second pull-up tube MP2, and pulls the other end of the first end A and the second end B from the first level to the second level.

That is to say, when the first terminal A changes from the first level to the second level, the pull-up control module outputs the first level of the first time period, and controls the first pull-up tube MP1 and the second pull-up tube MP2 Conduction. Since the second pull-up tube MP2 is turned on, the second terminal B can be pulled from the first level to the second level, which is equivalent to transmitting the second level signal of the first terminal A to the second terminal B.

When the second terminal B is switched from the first level to the second level, the pull-up control module outputs the first level of the first time period, and controls the first pull-up tube MP1 and the second pull-up tube MP2 to conduct. Since the first pull-up tube MP1 is turned on, the first terminal A can be pulled from the first level to the second level, which is equivalent to transmitting the second level signal of the second terminal B to the first terminal A.

Based on this, in the embodiment of the present invention, the bidirectional second-level transmission of the level conversion circuit can be realized through one pull-up control module, so that two pull-up control modules are not needed, and the number of modules and design complexity can be reduced. Small chip area and cost.

Among them, when the first pull-up tube MP1 and the second pull-up tube MP2 are PMOS transistors, the first level is low and the second level is high, or when the first pull-up tube MP1 and the second pull-up tube MP1 and the second When the pull-up tube MP2 is an NMOS transistor, the first level is a high level and the second level is a low level. In the embodiment of the present invention, only the first pull-up tube MP1 and the second pull-up tube MP2 are PMOS transistors, and the signal transmission tube MN is an NMOS transistor as an example for description.

It should be noted that, as shown in FIG. 2, the bidirectional level conversion circuit in the embodiment of the present invention further includes a driving circuit; the driving circuit is used to control the signal transmission tube when both ends of the signal transmission tube MN are at the first level MN is turned on. Specifically, when the signal transmission tube MN is an NMOS transistor, the driving circuit is used to control the signal transmission tube MN to be turned on when both ends of the signal transmission tube MN are low, and both ends of the signal transmission tube MN are high. At the level, the control signal transmission tube MN is disconnected.

In other words, in the bidirectional level conversion circuit in the embodiment of the present invention, when the first end A and the second end B are both low, the control signal transmission tube MN is turned on to realize the transmission of two voltage domain signals. When either of the first terminal A and the second terminal B is at a high level, the first pull-up tube MP1 or the second pull-up tube MP2 is controlled to be turned on, and the other end is pulled up to a high level, which is equivalent to achieving two voltages Domain signal transmission.

As shown in FIG. 3, the pull-up control module in the embodiment of the present invention includes a first signal input terminal LA, a second signal input terminal LB, a port detection module, a bidirectional detection trigger module, and a single pulse generation module.

Wherein, the port detection module is electrically connected to the first signal input terminal LA and the second signal input terminal LB, and is used to output the first level when the first signal input terminal LA and the second signal input terminal LB are both at the second level , When at least one of the first signal input terminal LA and the second signal input terminal LB is at the first level, the second level is output; optionally, the first level is low and the second level is high Level. The bidirectional detection trigger module is electrically connected to the first signal input terminal LA and the second signal input terminal LB, and is used to output the second level when the first signal input terminal LA and the second signal input terminal LB are both at the first level, When at least one of the first signal input terminal LA and the second signal input terminal LB is at the second level, the first level is output. The single pulse generation module is electrically connected to the port detection module and the bidirectional detection trigger module, and is used to output the first voltage when the port detection module outputs the second level and the output of the bidirectional detection trigger module is converted from the second level to the first level. Ping pulse, output the second level in other periods.

Optionally, as shown in FIG. 3, the port detection module includes a NAND gate NA and a first inverter NV1 to a fourth inverter NV4; the input terminal of the first inverter NV1 is electrically connected to the first signal input terminal LA. The input terminal of the second inverter NV2 is electrically connected with the output terminal of the first inverter NV1, and the output terminal of the second inverter NV2 is electrically connected with an input terminal of the NAND gate NA; the third inverter The input terminal of NV3 is electrically connected to the second signal input terminal LB, the input terminal of the fourth inverter NV4 is electrically connected to the output terminal of the third inverter NV3, and the output terminal of the fourth inverter NV4 is NAND gate NA The other input terminal is electrically connected; the output terminal of the NAND gate NA is electrically connected to the output terminal A1 of the port detection module.

As shown in FIG. 3, the bidirectional detection trigger module includes an OR gate, first transistor M1 to fifth transistor M5, a fifth inverter NV5, and a sixth inverter NV6; an input terminal of the OR gate and the first signal The input terminal LA is electrically connected, the other input terminal of the OR gate OR is electrically connected with the second signal input terminal LB, and the output terminal of the OR gate OR is electrically connected with the gate of the first transistor M1; the first terminal of the first transistor M1 is electrically connected with The second end of the second transistor M2 is electrically connected, the first end of the second transistor M2 is electrically connected to the power supply terminal VDD, the second end of the first transistor M1 is electrically connected to the second end of the third transistor M3, and the third transistor M3 The gate of the first transistor M3 is electrically connected to the first signal input terminal LA, the first terminal of the third transistor M3 is electrically connected to the ground terminal GND; the second terminal of the first transistor M1 is electrically connected to the second terminal of the fourth transistor M4, and the fourth The second end of the transistor M4 is electrically connected to the gate of the fourth transistor M4 through the fifth inverter NV5, and the gate of the fourth transistor M4 is electrically connected to the gate of the second transistor M2 through the sixth inverter NV6; The gate of the fifth transistor M5 is electrically connected to the second signal input terminal LB, the first end of the fifth transistor M5 is electrically connected to the ground terminal GND, and the second end of the fifth transistor M5 is electrically connected to the second end of the fourth transistor M4 ; The second end of the fourth transistor M4 is electrically connected to the output end A2 of the bidirectional detection trigger module.

As shown in Figure 3, the single pulse generation module includes a sixth transistor M6 to an eighth transistor M8, a first resistor R1, a second resistor R2, a seventh inverter NV7, an eighth inverter NV8, and a ninth inverter. NV9 and NOR gate; the first terminal of the sixth transistor M6 is electrically connected to the power supply terminal VDD, the gate of the sixth transistor M6 is electrically connected to the output terminal A2 of the bidirectional detection trigger module, and the second terminal of the sixth transistor M6 is electrically connected to One end of the first resistor R1 is electrically connected, the other end of the first resistor R1 is electrically connected to one end of the second resistor R2, and the other end of the second resistor R2 is electrically connected to the first end of the seventh transistor M7. The second terminal is electrically connected to the ground terminal GND, the gate of the seventh transistor M7 is electrically connected to the output terminal A2 of the bidirectional detection trigger module; the gate of the eighth transistor M8 is electrically connected to the output terminal A1 of the port detection module, and the eighth transistor The first end of M8 is electrically connected to one end of the first resistor R1, the second end of the eighth transistor M8 is electrically connected to the other end of the first resistor R1; the input end of the seventh inverter NV7 is electrically connected to the other end of the second resistor R2 One end is electrically connected, the output end of the seventh inverter NV7 is electrically connected to the input end of the eighth inverter NV8, the output end of the eighth inverter NV8 is electrically connected to an input end of the NOR gate, and the bidirectional detection trigger The output terminal A2 of the module is electrically connected with the other input terminal of the NOR gate, the output terminal of the NOR gate NOR is electrically connected with the input terminal of the ninth inverter NV9, and the output terminal of the ninth inverter NV9 is electrically connected with the single pulse The output terminal LOUT of the generating module is electrically connected.

Among them, the first transistor M1, the second transistor M2, and the fourth transistor M4 are PMOS transistors, the third transistor M3 and the fifth transistor M5 are NMOS transistors, the sixth transistor M6 and the eighth transistor M8 are PMOS transistors, and the seventh transistor M7 It is an NMOS transistor. Of course, the present invention is not limited to this. In other embodiments, the first transistor M1, the second transistor M2, and the fourth transistor M4 may also be NMOS transistors, and the third transistor M3 and the fifth transistor M5 may also be PMOS transistors. The sixth transistor M6 and the eighth transistor M8 may also be NMOS transistors, and the seventh transistor M7 may also be PMOS transistors.

4, the first level is low level, and the second level is high level. When the first terminal A and the second terminal B are low level, that is, the first signal input terminal LA and the second When the signal input terminal LB is low level, the output terminal A1 outputs high level. The OR gate OR outputs a low level, and the first transistor M1 is turned on. Since the first signal input terminal LA and the second signal input terminal LB are low level, the third transistor M3 and the fifth transistor M5 are disconnected, and the output terminal A2 outputs a high level, so that the fourth transistor M4 is turned on, and the output terminal A2 is weakly pulled up and locked. Since the output terminal A1 outputs a high level, the eighth transistor M8 is turned off. Since the output terminal A2 outputs a high level, the sixth transistor M6 is turned off and the seventh transistor M7 is turned on, pulling down one input terminal A3 of the NOR gate NOR to a low level. Since the NOR gate NOR has another input terminal connected to the output terminal A2, the NOR gate NOR outputs a low level, and the output terminal LOUT outputs a high level, which controls the first pull-up tube MP1 and the second pull-up tube MP2 to turn off open.

When either of the first terminal A and the second terminal B is turned from low to high, for example, when the first terminal A is turned from low to high, the first signal input terminal LA is turned from low to high At high level, the third transistor M3 is turned on and pulls down the output terminal A2 to low level. At this time, the node A4 will turn from low level to high level. However, at this time, the current will be caused by the first resistor R1 and The second resistor R2 is limited, causing the node A4 to have a delay, causing the node A3 to switch from low level to high level, and also causing delay. Therefore, the output terminal LOUT will output a low level for a certain period of time t, and control the first An upper pull tube MP1 and a second upper pull tube MP2 are turned on, and the second end B is pulled up from low level to high level. Among them, t=(R1+R2)*C, C is the parasitic capacitance of node A4. In addition, after time t, the node A3 flips to a high level, the output terminal LOUT outputs a high level, and the first pull-up tube MP1 and the second pull-up tube MP2 are controlled to be disconnected. In addition, when the second terminal B is pulled to a high level at t1, t1 is less than t, the output terminal A1 is inverted to a low level, the eighth transistor M8 is turned on, so that the current flowing through the sixth transistor M6 increases, Therefore, the output terminal LOUT can be flipped to a high level in advance, and the first pull-up tube MP1 and the second pull-up tube MP2 can be quickly disconnected after the second terminal B is pulled to a high level, thereby reducing the first The power consumption of the pull-up tube MP1 and the second pull-up tube MP2.

When both the first terminal A and the second terminal B are at high level, that is, when the first signal input terminal LA and the second signal input terminal LB are both at high level, the output terminal A1 is at high level and the output terminal A2 is at low level. At the same time, the second transistor M2 is turned on, the first transistor M1 is turned off, the eighth transistor M8 is turned on, the output terminal LOUT outputs a high level, and the first pull-up tube MP1 and the second pull-up tube MP2 are controlled to be turned off.

When either of the first terminal A and the second terminal B is turned from high to low, that is, when either of the first signal input terminal LA and the second signal input terminal LB is turned from high to low, The output terminal A1 outputs high level, the output terminal A2 is low level, the eighth transistor M8 is turned off, and the others keep the original state, the output terminal LOUT outputs high level, and controls the first pull-up tube MP1 and the second pull-up tube MP2 disconnect.

When both the first terminal A and the second terminal B are at low level, that is, when the first signal input terminal LA and the second signal input terminal LB are both at low level, the third transistor M3 and the fifth transistor M5 are disconnected, and the first Transistor M1 is turned on, the second transistor M2 is turned off after the output terminal A2 is pulled to high level, the nodes A3 and A4 are turned to low level, and the output terminal LOUT outputs high level. At this time, the pull-up control module is in the waiting state When any one of the first terminal A and the second terminal B turns from low level to high level, the pull-up control module outputs a low-level pulse to control the conduction of the first pull-up tube MP1 and the second pull-up tube MP2 .

The embodiment of the present invention also provides a bidirectional level conversion chip, which includes the bidirectional level conversion circuit provided in any of the foregoing embodiments.

In the bidirectional level conversion circuit and the bidirectional level conversion chip provided by the present invention, the pull-up control module outputs the first level when either end of the first end and the second end of the signal transmission tube is converted from the first level to the second level. The level pulse controls the conduction of the first pull-up tube and the second pull-up tube, and pulls the other end of the first end and the second end from the first level to the second level, that is, the first end of the present invention The first pull-up tube and the second pull-up tube are controlled by a pull-up control module, thereby not only reducing the number of modules and design complexity, but also reducing chip area and cost.

The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in this document, but should conform to the widest scope consistent with the principles and novel features disclosed in this document.

Claims

A bidirectional level conversion circuit, which is characterized by comprising a signal transmission tube, a first pull-up tube, a second pull-up tube and a pull-up control module;

The first end of the first pull-up tube is electrically connected with a first voltage terminal, the second end of the first pull-up tube is electrically connected with the first end of the signal transmission tube, and the second pull-up tube The first end of the second end is electrically connected to the second voltage end, and the second end of the second pull-up tube is electrically connected to the second end of the signal transmission tube;

The first signal input end of the pull-up control module is electrically connected to the first end of the signal transmission tube, and the second signal input end of the pull-up control module is electrically connected to the second end of the signal transmission tube, The output end of the pull-up control module is electrically connected to the grids of the first pull-up tube and the second pull-up tube;

The pull-up control module is used for outputting a first level pulse when any one of the first end and the second end of the signal transmission tube is inverted from the first level to the second level to control the first upper end The pull tube and the second upper pull tube are connected to pull the other end of the first end and the second end from the first level to the second level.
The circuit according to claim 1, wherein the pull-up control module comprises a first signal input terminal, a second signal input terminal, a port detection module, a bidirectional detection trigger module, and a single pulse generation module;

The port detection module is electrically connected to the first signal input terminal and the second signal input terminal, and is configured to output when the first signal input terminal and the second signal input terminal are both at the second level A first level, output a second level when at least one of the first signal input terminal and the second signal input terminal is at the first level;

The two-way detection trigger module is electrically connected to the first signal input terminal and the second signal input terminal, and is used for when both the first signal input terminal and the second signal input terminal are at the first level, Output a second level, and output the first level when at least one of the first signal input terminal and the second signal input terminal is at the second level;

The single pulse generation module is electrically connected to the port detection module and the bidirectional detection trigger module, and is configured to output a second level at the port detection module, and the output of the bidirectional detection trigger module is converted from the second level When it is the first level, the first level pulse is output, and the second level is output in other periods.
The circuit according to claim 2, wherein the port detection module comprises a NAND gate and a first inverter to a fourth inverter;

The input terminal of the first inverter is electrically connected to the first signal input terminal, the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the second inverter is electrically connected to the output terminal of the first inverter. The output terminal of the phase converter is electrically connected with an input terminal of the NAND gate;

The input terminal of the third inverter is electrically connected to the second signal input terminal, the input terminal of the fourth inverter is electrically connected to the output terminal of the third inverter, and the fourth inverter is electrically connected to the output terminal of the third inverter. The output terminal of the phase converter is electrically connected to the other input terminal of the NAND gate;

The output terminal of the NAND gate is electrically connected with the output terminal of the port detection module.
The circuit according to claim 3, wherein the bidirectional detection trigger module comprises an OR gate, a first transistor to a fifth transistor, a fifth inverter and a sixth inverter;

One input terminal of the OR gate is electrically connected to the first signal input terminal, the other input terminal of the OR gate is electrically connected to the second signal input terminal, and the output terminal of the OR gate is electrically connected to the first signal input terminal. The gate of a transistor is electrically connected;

The first terminal of the first transistor is electrically connected to the second terminal of the second transistor, the first terminal of the second transistor is electrically connected to the power terminal, and the second terminal of the first transistor is electrically connected to the third transistor. The second terminal of the third transistor is electrically connected to the first signal input terminal, and the first terminal of the third transistor is electrically connected to the ground terminal;

The second end of the first transistor is electrically connected to the second end of the fourth transistor, and the second end of the fourth transistor is electrically connected to the gate of the fourth transistor through a fifth inverter. The gate of the four transistors is electrically connected to the gate of the second transistor through a sixth inverter;

The gate of the fifth transistor is electrically connected to the second signal input terminal, the first terminal of the fifth transistor is electrically connected to the ground terminal, and the second terminal of the fifth transistor is electrically connected to the fourth transistor. The second end is electrically connected;

The second terminal of the fourth transistor is electrically connected to the output terminal of the bidirectional detection trigger module.
4. The circuit of claim 4, wherein the first transistor, the second transistor, and the fourth transistor are PMOS transistors, and the third transistor and the fifth transistor are NMOS transistors.
The circuit according to claim 4, wherein the single pulse generating module includes a sixth transistor to an eighth transistor, a first resistor, a second resistor, a seventh inverter, an eighth inverter, and a ninth transistor. Inverter and NOR gate;

The first terminal of the sixth transistor is electrically connected to the power terminal, the gate of the sixth transistor is electrically connected to the output terminal of the bidirectional detection trigger module, and the second terminal of the sixth transistor is electrically connected to the first terminal. One end of the resistor is electrically connected, the other end of the first resistor is electrically connected to one end of the second resistor, the other end of the second resistor is electrically connected to the first end of the seventh transistor, and the seventh The second terminal of the transistor is electrically connected to the ground terminal, and the gate of the seventh transistor is electrically connected to the output terminal of the bidirectional detection trigger module;

The gate of the eighth transistor is electrically connected to the output end of the port detection module, the first end of the eighth transistor is electrically connected to one end of the first resistor, and the second end of the eighth transistor is electrically connected to The other end of the first resistor is electrically connected;

The input end of the seventh inverter is electrically connected to the other end of the second resistor, the output end of the seventh inverter is electrically connected to the input end of the eighth inverter, and the eighth The output terminal of the inverter is electrically connected with one input terminal of the NOR gate, the output terminal of the bidirectional detection trigger module is electrically connected with the other input terminal of the NOR gate, and the output terminal of the NOR gate It is electrically connected to the input terminal of the ninth inverter, and the output terminal of the ninth inverter is electrically connected to the output terminal of the single pulse generation module.
7. The circuit of claim 6, wherein the sixth transistor and the eighth transistor are PMOS transistors, and the seventh transistor is an NMOS transistor.
The circuit according to any one of claims 1 to 7, wherein the first pull-up tube and the second pull-up tube are PMOS transistors; the first level is a low level, the The second level is a high level.
The circuit according to claim 1, further comprising a driving circuit;

The driving circuit is used for controlling the signal transmission tube to be turned on when both ends of the signal transmission tube are at the first level.
A bidirectional level conversion chip, characterized by comprising the bidirectional level conversion circuit according to any one of claims 1-9.