CN107437894A

CN107437894A - Overvoltage protection

Info

Publication number: CN107437894A
Application number: CN201610355692.0A
Authority: CN
Inventors: 郑景中; 林国凯
Original assignee: Ali Corp
Current assignee: Yangzhi Electronic Technology (Chengdu) Co.,Ltd.
Priority date: 2016-05-26
Filing date: 2016-05-26
Publication date: 2017-12-05
Anticipated expiration: 2036-05-26
Also published as: US10411458B2; US20170346273A1; CN107437894B

Abstract

The present invention provides a kind of overvoltage protection.This overvoltage protection includes output-stage circuit, first switch and the first load and provides circuit.Output-stage circuit possesses first input end to receive the first signal, and according to the first signal with the output end of output-stage circuit generation output signal.The first input end of the first end coupling output-stage circuit of first switch, the control terminal of first switch receive secondary signal.First signal is by the secondary signal postponed.First load provides the second end of circuit coupling first switch.First load provides circuit and provides impedance to first input end when first switch turns on.

Description

Overvoltage protection

Technical field

The invention relates to the over-voltage protection technology of a kind of electronic equipment, USB is particularly applicable to (Universal Serial Bus；USB) the overvoltage protection of interface.

Background technology

USB (Universal Serial Bus；USB) interface has the functions such as hot plug and plug and play. Since appearance, USB interface is widely applied to various electronic products, e.g. USB storage device, Mobile phone, printer, PC ... etc., become the main flow interface of data exchange between various devices.Particularly, USB storage device is almost everyone indispensable computer peripheral.

With the evolution growing day by day and technology of data volume, USB interface also continuous updating standard specification.For example, Current USB access voltages in the section of low-voltage be 0.0V between 0.3V, and USB access voltages are in high electricity The section of pressure is 2.8V between 3.6V.May however, being arranged on control chip among the storage device of USB interface It is by being made with 1.8V operating voltages come the manufacture of semiconductor that drives, but needs to export the high voltage beyond 1.8V It is worth (e.g., 2.8V to 3.6V), so that the overvoltage crowbar in storage device needs often to bear the feelings of overvoltage Shape.

Although this storage device remains to maintain normal operation under the design via integrated circuit, if long-term positioned at overvoltage In the case of, the life-span of overvoltage crowbar and reliability will be reduced significantly in storage device.In practical situation, If in storage device used by overvoltage crowbar metal-oxide semiconductor (MOS) (MOS) lock level-source voltage (Vgs) Less than negative value 2.05V when (such as Vgs is -2.145V), then storage device may possess about slightly 5 years and be averaged Service life and reliability.Relatively, if in overvoltage crowbar MOS Vgs be on the occasion of 2.145V when, Storage device may only possess average life and the reliability of about slightly 1.68.In addition to the situation of voltage range, The circuit of USB interface is with greater need for the specification for meeting voltage conversioning rate (Slew rate).Voltage conversioning rate is unit The rate of change of time voltage, if voltage conversioning rate is excessive, easily cause electromagnetic interference (Electromagnetic Interference；EMI).

Base this, in the case of how avoiding storage device and the electronic component from being chronically at overvoltage, but meet USB simultaneously The overvoltage crowbar of mouth can meet said circumstances, be one of important problem.

The content of the invention

In view of this, the present invention provides a kind of overvoltage protection, can avoid using the electronic installation of USB interface with And corresponding electronic element overvoltage, to extend the life-span of electronic installation and electronic component.

Overvoltage protection of the present invention includes output-stage circuit, first switch and the first load and provides circuit. Output-stage circuit possesses first input end to receive the first signal, and according to the first signal with the output of output-stage circuit End produces output signal.The first input end of the first end coupling output-stage circuit of first switch, the control of first switch End receives secondary signal.First signal is by the secondary signal postponed.First load provides circuit coupling first switch The second end.First load provides circuit and provides impedance to first input end when first switch turns on.

First switch and first negative is had additional before output-stage circuit based on above-mentioned, of the invention overvoltage protection Carry and circuit is provided.Thereby, when data-signal need to transmit by this overvoltage protection, data-signal can be postponed To produce the first signal, and first switch is turned on by the secondary signal related to data-signal, so that the first load The sending-end impedance of output-stage circuit can be increased when first switch turns on by providing circuit.Also, in sending-end impedance After lifting, the first signal of delay is transferred to the output end of output-stage circuit.Consequently, it is possible to data-signal can be made Delay its voltage fringe time when passing through output-stage circuit, with avoid voltage instantaneous increase and cause electronic installation and its The damage of internal electronic element.

For features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings It is described in detail below.

Brief description of the drawings

Fig. 1 is the block diagram according to the overvoltage protection depicted in first embodiment of the invention.

Fig. 2 is the circuit diagram according to the overvoltage protection depicted in first embodiment of the invention.

Fig. 3 is the circuit diagram of the buffer depicted according to first embodiment of the invention.

Fig. 4 is the signal timing diagram according to the overvoltage protection depicted in first embodiment of the invention.

Fig. 5 is a kind of circuit diagram of first switch according to first embodiment of the invention.

Fig. 6 is the block diagram according to the overvoltage protection depicted in second embodiment of the invention.

Fig. 7 is the circuit diagram according to the overvoltage protection depicted in second embodiment of the invention.

Fig. 8 is the signal timing diagram according to the overvoltage protection depicted in second embodiment of the invention.

Reference

100、200、500、600：Overvoltage protection

110：First switch

210a、210b、210c、210d、510a、510b、510c：The end points of first switch

650：Second switch

750a、750b、750c、750d：The end points of second switch

120、660：Load provides circuit

130：Output-stage circuit

140：First predrive circuit

670：Second predrive circuit

210、235、237：Nmos pass transistor

220、760：Capacitor

231、233：PMOS transistor

240、350：System voltage end

250：First bias terminal

262、264、300：Buffer

310：Input transistors pair

320：Bias control transistor pair

330：Resistance element pair

340：Output end pair

770：Single ended input amplifier circuit

SD、SD_P、SD_N、SD_2、S1、S2_P、S2_N、S3、Sout：Signal

T1~t6：Time point

Embodiment

Fig. 1 is the block diagram according to the overvoltage protection 100 depicted in first embodiment of the invention.Overvoltage is protected Protection unit 100 can be applied to the electronic installation of USB interface, for example, in the equipment such as USB storage device, mobile phone .... USB storage device can be flash memory (Flash drive), hard disk (Hard disk drive) etc., as long as can use The storage device of USB interface all can operate with this.Fig. 1 is refer to, the overvoltage protection 100 of the present embodiment is led If transmit signal between different voltage domains.In the present embodiment, the received data of overvoltage protection 100 Signal SD voltage level is located at 0V to the voltage domain between 1.8V, and overvoltage protection 100 is exported Output signal Sout voltage level is positioned at 0V to the voltage domain between 3.3V.Transmitting data-signal SD mistake Cheng Zhong, data-signal SD can boost via the first predrive circuit 140, to produce the letters of the first signal S1 and second Number S2；The output signal output Sout by reception the first signal S1 and secondary signal S2 of output-stage circuit 130.Its In, the first signal S1 and secondary signal S2 of the present embodiment voltage level system are located at 1.8V to the electricity between 3.3V Press domain.The voltage domain where signal can be adjusted according to its demand using the present embodiment person, use and avoid overvoltage protection from filling Put each element or the transistor overvoltage in 100.

In one embodiment, there is overvoltage protection 100 load of first switch 110, first to provide circuit 120 And output-stage circuit 130.First switch 110 has control terminal 110a, first end 110b and the second end 110c. First switch 110 is according to the secondary signal S2 that its control terminal 110a is received to control first end in first switch 110 The conducting and cut-off of circuit between 110b and the second end 110c.For example, when control terminal 110a receives enable During secondary signal S2, circuit turn-on between first end 110b and the second end 110c can be made, to form circuit loop；When When control terminal 110a receives the secondary signal S2 of forbidden energy, then make circuit between first end 110b and the second end 110c Cut-off.

First load provides the second end 110c that circuit 120 is coupled to first switch 110, dynamically to provide output stage The impedance value of the first input end 130a sides of circuit 130.Specifically, the first load provides whether circuit 120 connects First input end 130a systems to output-stage circuit 130 are controlled by first switch 110.When first switch 110 turns on, The first load can be made to provide the first input end 130a that circuit 120 is coupled directly to output-stage circuit 130.Now, by Circuit 120 is provided to increase the impedance value of the first input end 130a sides of output-stage circuit 130 by the first load, so as to So that the impedance value of the first input end 130a sides of output-stage circuit 130 temporarily rises, and then make the first signal S1 voltage transmission speed declines, and then delays to export electricity caused by the output end 130b from output-stage circuit 130 The voltage change of pressure.

Output-stage circuit 130 receives the first signal S1 from first input end 130a, and from the defeated of output-stage circuit 130 Go out to hold 130b to produce output signal Sout.The output end 130b of output-stage circuit 130 can be with usb connecting port (example Such as：USB slot of host computer etc.) it is attached, and carry out data exchange.

As depicted in Fig. 1, the embodiment of the present invention also optionally includes the first predrive circuit 140.First pre- drive Dynamic circuit 140 is coupled to the first input end 130a of the output-stage circuit 130 and control terminal 110a of first switch 110, Data-signal SD to be progressively converted to the signal of different voltage domains (e.g., the first signal S1 and secondary signal S2). The present embodiment system postpones secondary signal S2 to produce the first signal S1 using the first predrive circuit 140.However, In the other embodiment of the present invention, the secondary signal S2 simply entered enable pulse is not later than the first signal S1 and arrived at First switch 110.That is, secondary signal S2 enable pulse can arrive at the simultaneously with the first signal S1 In contrast one switch 110, or secondary signal S2 enable pulse slightly early arrive at first switch with the first signal S1 110, the present invention is not intended to limit the mode of its realization.Reason for this is that spirit of the embodiment of the present invention is desirable in the first signal S1 can increase the load of input in advance before or while arriving.Thereby, in transition moment, output-stage circuit 130 The changes of output signal Sout waveform that measure of output end 130b will smooth variation.In other words, this is met The section Example of spirit can be delayed data-signal SD (also referred to as the 3rd signal) by buffer Punching is and synchronous with secondary signal S2 in itself by data-signal SD with as the first signal S1, uses as realizing One of circuit structure for the effect of invention is to be reached.

Fig. 2 is the circuit diagram according to the overvoltage protection 200 depicted in first embodiment of the invention.Leading explanation , see Fig. 2, the first predrive circuit 140 of the present embodiment can be delayed by the first of double-width grinding and both-end output The second buffer 264 of device 262 and double-width grinding and Single-end output is rushed to form, therefore the first buffer in Fig. 2 262 need to be come as the first predrive circuit 140 with positive data signal SD_P and reverse negative data signal SD_N Input signal, the first buffer 262 also does by positive secondary signal S2_P and reverse negative secondary signal S2_N To export to the signal of the second buffer 264.For convenience's sake, will be represented just with data-signal in being described below Data-signal SD_P and negative data signal SD_N, and positive secondary signal S2_P and minus second are represented with secondary signal Signal S2_N.

Fig. 1 and Fig. 2 is please also refer to, one or more metal oxide semiconductcor field effects can be used in first switch 110 Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor；MOS) form, for example, N Type MOS and/or p-type MOS.In the circuit structure of the present embodiment, first switch 110 is by possessing four end points Switch realize.This switch is with control terminal 210a (the control terminal 110a as first switch 110), first end 210b (the first end 110b as first switch 110), the second end 210c (being connected to system voltage end) and Three end 210d (the second end 110c as first switch 110).

In one embodiment, the first load, which provides circuit 120, is realized by the first capacitor 220.First capacitor 220 have first end 220a and the second end 220b.The first end 220a of first capacitor 220 is coupled to first switch 110 the 3rd end 210d, the second end 220b of the first capacitor 220 are then coupled to the second end of second transistor 233 233c, that is, it is coupled to the output end 130b of output-stage circuit 130.

In addition, in other embodiments of the present invention, the second end 220b of the first capacitor 220 can also optionally not Be coupled to the output end 130b of output-stage circuit 130, and be coupled to the first transistor 231 the second end 231c or The first end 233b of second transistor 233.That is, as long as the coupling mode of the first capacitor 220 can reach Increase the purpose of the first input end 130a sides impedance value of output-stage circuit 130.Can be according to it using the present embodiment person Demand adjusts the coupling mode of capacitor, is not limited in coupling mode of the present invention.

The relation between the capacitor 220 of first switch 110 and first is described in detail here.When first switch 110 When control terminal 210a receives the negative secondary signal S2_N of enable, the first end 210b and the of first switch 110 will be made Three end 210d are electrically connected with each other so that the first end 220a of the first capacitor 220 is coupled directly to output-stage circuit 130 first input end 130a.Thereby, the first capacitor 220 can lift output stage electricity by capacitance coupling effect The first input end 130a on road 130 impedance.On the other hand, prohibit when the control terminal 210a of first switch 110 is received It is during the negative secondary signal S2_N of energy, the second end 210c and the 3rd end 210d of making first switch 110 is mutually electrical Connection, and disconnect the first end 210b and the 3rd end 210d of first switch 110.Due to the of the first capacitor 220 One end 220a is coupled directly to system voltage end through the second end 210c and the 3rd end 210d of first switch 110 240 so that the first capacitor 220 can store required electric charge.

Output-stage circuit 130 can be realized by the circuit structure that multiple transistors are contacted.The present embodiment is with the of concatenation One transistor 231, second transistor 233, third transistor 235 and the 4th transistor 237 of concatenation realize, but The present invention is not limited thereto.The first transistor 231 and second transistor 233 can be realized by p-type MOS；3rd The transistor 237 of transistor 235 and the 4th can be realized by N-type MOS.Contacted by multiple transistors defeated to realize The reasons why going out grade circuit 130 be, due in output-stage circuit 130 with single transistor come if realizing, transistor Itself it is likely difficult to bear its control terminal to its output end or its control terminal to the voltage difference between its system voltage, therefore It is to be connected using multiple transistors to realize output-stage circuit 130 in the present embodiment.

The detailed circuit structure being described herein in output-stage circuit 130.The first transistor 231 and second transistor 233 There is control terminal 231a, 233a, first end 231b, 233b and second end 231c, 233c, the first transistor respectively 231 first end 231b is connected with system voltage end 240.Second end 231c of the first transistor 231 and second is brilliant The first end 233b connections of body pipe 233.The control terminal 233a of second transistor 233 is connected with the first bias terminal 250 Connect.The control terminal 231a of the first transistor 231 is the input of output-stage circuit 130, and second transistor 233 Second end 233c is the output end of output-stage circuit.The control terminal 235a of third transistor 235 can be used as output stage electricity Another input on road 130 is to receive the 4th signal S3.The first end 235b coupling earth terminals of third transistor 235. The the second end 235c and the 4th transistor 237 of third transistor 235 first end 237b phases couple.4th transistor 237 control terminal 237a couples the second reference voltage, and the second end 237c of the 4th transistor 237 and the second crystal Second end 233c of pipe 233 is connected.

The first predrive circuit 140 of the present embodiment is realized by the first buffer 262 and the second buffer 264. In the present embodiment, the first buffer 262 receives the 3rd signal positioned at first voltage domain (e.g., 0V to 1.8V) (e.g., positive data signal SD_P and negative data signal SD_N), to produce, positioned at second voltage domain, (e.g., 1.8V is extremely Secondary signal (positive secondary signal S2_P and negative secondary signal S2_N) 3.3V).Second buffer 264 is connecing Receive and postpone secondary signal (positive secondary signal S2_P and negative secondary signal S2_N) to produce the first signal S1, and One signal S1 is located at second voltage domain (1.8V to 3.3V).The first buffer 262 and the second buffering in the present embodiment Device 264 will further disclose specific circuit structure in Fig. 3.Fig. 3 is according to depicted in first embodiment of the invention Buffer circuit diagram.The first buffer 262 and the second buffer 264 in fig. 2 can pass through depicted in Fig. 3 Differential amplifier 300 realize.However, can be with other kinds of buffer or related circuit using the present embodiment person To realize the buffer of the embodiment of the present invention, the buffer structure depicted in Fig. 3 is not limited to.Special instruction, Fig. 3 differential amplifier 300 is double-width grinding, the circuit structure of both-end output, therefore it is slow to be applied directly to first Rush device 262.Also can be by differential amplifier 300 and optionally only with one of output end using the present embodiment person To carry out signal output, use and apply to the second buffer 264.

Fig. 3 is refer to, specifically, differential amplifier 300 mainly has input transistors to 310, resistance element pair 330 and output end to 340.Input transistors connect to 310 with reference current source 305, and provide a pair of inputs, With receive differential wave to (such as：Data-signal SD_P, SD_N, or secondary signal S2_P, S2_N).Resistance Property element is respectively coupled to bias control transistor to 330 to 320 and system voltage end 350, to according to differential letter Number to producing single-ended or both-end output signal.In the present embodiment, resistance element is come with resistive element to 330 Realize.However, in other embodiments, MOS transistor implementation resistance element can also be used to 330.In other words Say, as long as the element with resistive can implementation into resistance element to 330, the present embodiment not limited to this.It is defeated It is to by signal output to 340 to go out end.Differential amplifier 300 also optionally sets bias control transistor To 320.Bias control transistor is respectively coupled to input transistors to 310 to each transistor in 320, and respectively at it Control terminal receives bias control voltage, uses and avoids circuit over-pressed.

When no signal is input to the input of differential amplifier 300, output end can be with system electricity to 340 voltage Pressure side 350 is identical, is, for example, 3.3V in the present embodiment.When input transistors receive signal input to 310, Output end can change output voltage to 340 because of the conducting of circuit, and now, output voltage is that system voltage subtracts electricity The product of stream and resistance, i.e. 3.3V-I × R.That is, by design of the resistance element to 330, thus it is possible to vary defeated The voltage domain gone out, and make voltage domain control in default scope.

Specifically, it is merely illustrative in the voltage domain of the number of buffers disclosed by the present embodiment, conversion, In actual application, the quantity of buffer can be it is multiple, the voltage domain of conversion also can because circuit design consideration without Together, the invention is not restricted to this.For example, refer to Fig. 2, the second buffer 264 produce the first signal S1 it Afterwards, the first signal S1 can be further inputted to another buffer, to increase negative secondary signal S2_N and first Time difference between signal S1.In other words, the present invention does not limit the quantity and conversion voltage domain of buffer, as long as Secondary signal S2_N can be made to input to the time of the first nmos pass transistor 210 to input to earlier than the first signal S1 The time of one transistor 231, and secondary signal S2_N, S2_P and the first signal S1 voltage domain meet output stage electricity The buffer circuits of the output specification on road 130, can be used in the present invention.

Go back to Fig. 2, in the present embodiment, if the control terminal 231a sides of the first transistor 231 impedance (or be, Load) it is relatively low if, receiving the first signal S1 moment, unit interval voltage will instantaneous variation, i.e. voltage Switching rate can be larger, so will likely result in the electromagnetic interference on the control terminal 231a side lines road of the first transistor 231 Problem.If however, if the load too high of the control terminal 231a sides of the first transistor 231, the signal that transmits it is non-thread Property part can increase, and cause signal quality to reduce.On the other hand, the overvoltage protection 200 of the present embodiment is first to be about to Data-signal SD_P, SD_N postpone the first signal S1 postponed to produce the and secondary signal S2 not postponed (e.g., bearing secondary signal S2_N).Whether first switch 110 dynamically turns on according to negative secondary signal S2 enable The first end 210b and the 3rd end 210d of first switch 110, use and buffered in the first signal S1 postponed from second Device 264 lifts the impedance of the control terminal 231a sides of the first transistor 231 (also before being sent to the first transistor 231 It is the first input end 130a of output-stage circuit 130 impedance).Consequently, it is possible to it can make relative with data-signal The the first signal S1 answered can effectively delay the first signal S1 voltage fringe time when by the first transistor 231, The problem of making electronic installation and its internal electronic element produce electromagnetic interference to avoid voltage instantaneous from changing.

Specifically, in one embodiment, whether the enable for bearing secondary signal S2_N is to utilize negative secondary signal S2_N Signal pulse be used as the control signal source that first end 210b turns on the 3rd end 210d in first switch 110. When the control terminal 210a of the first nmos pass transistor 210 receives the secondary signal S2_N of high phase place, first opens Closing 110 first end 210b and the 3rd end 210d will turn on, and make the first capacitor 220 and the first transistor 231 Control terminal 231a between the state in short circuit so that the first capacitor 220 is able to temporarily to increase output stage electricity The first input end 130a on road 130 impedance.Conversely, when the control terminal 210a of first switch 110 receives low phase During the secondary signal S2_N of position, the first end 210b and the 3rd end 210d of first switch 110 are in the state of open circuit, And the second end 210c of first switch 110 and the 3rd end 210d will short circuit.Can be according to its demand using the present embodiment person The practice is controlled herein slightly to adjust, for example, can be used as through positive secondary signal S2_P signal pulse The control signal source of conducting, but the corresponding end points and mode of braking of first switch 110 mutually may require that progress accordingly Adjustment.

Fig. 2 is continued referring to, it is assumed herein that the circuit of the control terminal 231a sides of the first transistor 231 has impedance in itself Value ZC1, the first capacitor 220 can carry when first switch 110 turns on its first end 210a and the 3rd end 210d The impedance value of confession is ZC2.Therefore, in the non-enables of negative secondary signal S2_N, the first end of the first capacitor 220 220a is coupled to system voltage end 240.Now, due to being opened between the first capacitor 220 and the first transistor 231 The state on road, the impedance of the first capacitor 220 can't be received for the control terminal 231a sides of the first transistor 231 Value, the impedance value of the control terminal 231a sides of the first transistor 231 is ZC1.Relatively, as negative secondary signal S2_N During enable, the first end 210b and the 3rd end 210d of first switch 110 will be turned on so that the first capacitor 220 First end 220 be coupled to the control terminal 231a of the first transistor 231.Now, the control terminal 231a of the first transistor 231 The load of side is ZC1+ α ZC2.By the load rise that the control terminal 231a sides of the first transistor 231 are received, Voltage fringe times of the first signal S1 by the first transistor 231 is delayed, effectively to avoid voltage instantaneous from changing Electronic installation and its internal electronic element is set to produce electromagnetic interference.

Fig. 4 is the signal timing diagram according to the overvoltage protection depicted in first embodiment of the invention, to illustrate to scheme The transmittance process of each signal in 2 overvoltage protections 200 illustrated.Referring to Fig. 2 and Fig. 4, Yu Shi Between point t1 when, voltage in data-signal SD_P, SD_N respectively reversely input to the first buffer 262.Especially say Bright, data-signal SD_P, SD_N signal phase are to be relative to each other and signal reverse each other.When first slow Rush after device 262 receives data-signal SD_P, the SD_N reversely inputted, just by data-signal SD_P, SD_N It is converted into time point t2 between 1.8V to secondary signal S2_P, S2_N between 3.3V, and with both-end output Mode adjusts or exported secondary signal S2_P, S2_N.

In time point t2, after the second buffer 264 receives adjusted secondary signal S2_P, S2_N, just when Between point t3 when change secondary signal S2_P, S2_N between the first signal S1, cause the first signal S1 from high levle Be converted to low level.Also, at time point 2, switch 210 arteries and veins according to the negative secondary signal S2_N of high phase place Rush and turn on its first end 210b and the 3rd end 210d.Due in time point t2, the first end of first switch 110 It is the state of conducting between 210b and the 3rd end 210d, therefore, in time point t2 between t3, the first transistor 231 Control terminal 231a impedance (or be, load) be gradually increasing.

In time point t3, the second buffer 264 the first signal of Single-end output S1 according to secondary signal S2_P, S2_N Pulse.The reason risen due to the control terminal 231a of the first transistor 231 load so that the first transistor 231 control terminal 231a will receive the first signal S1 slowly declined.Thereby, the knots modification of unit interval voltage Eased up with the first signal S1 of the reception of the first transistor 231 pulse, and then prevent that voltage conversioning rate is excessive. In addition, output signal Sout is also as the first signal S1 slowly rises.

When time point t4, secondary signal S2_N is converted to forbidden energy from enable.Therefore, in time point t4 to t5 Between, the first end 210b and the 3rd end 210d of first switch 110, which will be formed, to open a way.Now, the first transistor 231 The loads of control terminal 231a sides will taper into.When time point t5, due to the control of the first transistor 231 The load of end 231a sides has diminished, thus for the first transistor 231 control terminal 231a sides receive the One signal S1 will rapid increase, output signal Sout also with the first signal S1 and accordingly rapid increases.

It is noted that invention is not to be limited the time difference between time point t2 and time point t3, as long as the time Point t2 is not later than time point t3, that is, the first end that secondary signal S2_N can be made to turn on first switch 110 in time 210b and the 3rd end 210d.In addition, in other examples, as long as it is not later than the first signal S1 letter Number, can be as the signal source of conducting, however it is not limited to secondary signal S2_N.

In the section Example for meeting the present invention, first switch 110 is except can be by possessing the on-off circuit knot of four end points Structure beyond realizing, can also be realized by the switch for possessing three end points.Fig. 5 is refer to, Fig. 5 is according to the present invention A kind of circuit diagram of first switch 510 of first embodiment.Switch 510 has three end points, is respectively：Control terminal 510a (the control terminal 110a as first switch 110), the first end 510b (first ends as first switch 110 110b) and the second end 510c (the second end 110c as first switch).As the control terminal 510a of first switch 110 It is when receiving the secondary signal S2 of enable, the first end 510b and the second end 510c of making first switch 110 is mutually electrical Connection so that the first end 220a of the first capacitor 220 is coupled directly to the first input end of output-stage circuit 130 130a.Thereby, the first capacitor 220 can lift the first of output-stage circuit 130 the input by capacitance coupling effect Hold 130a impedance.On the other hand, when the control terminal 510a of first switch 110 receives the secondary signal S2 of forbidden energy, It will be switched off the first end 510b and the second end 510c of first switch 110.It can come using the present embodiment person according to its demand saturating A variety of switching circuit structures is crossed to realize first switch 110, is not limited in construction of switch of the present invention.Its Remaining technology contents can be by that can obtain enough teachings, suggestion with implementing explanation in Fig. 1 to Fig. 4 explanation.

Fig. 6 is the block diagram according to the overvoltage protection 500 depicted in second embodiment of the invention.Fig. 6 and figure The load of first switch 110, first in 1 provides circuit 120, the predrive circuit 140 of output-stage circuit 130 and first Possess identical function and same circuits structure, will not be described here.

The maximum difference of overvoltage protection that Fig. 6 and Fig. 1 are illustrated is that overvoltage protection 600 further includes the Two the 650, second loads of switch provide the predrive circuit 670 of circuit 660 and second.In the present embodiment, second open It is the similar switch of circuit structure, the second impedance circuit 660 and the first impedance circuit that 650, which are closed, with first switch 110 120 be also the similar impedance circuit of circuit structure.Second switch 650, the second impedance circuit 660 are from Fig. 1 explanation Enough teachings, suggestion can be obtained with implementing explanation, repeated no more herein.Second predrive circuit 670 is then To postpone the second data-signal SD_2 (here, also referred to as the 5th signal) to produce the 4th signal P3.

Please also refer to Fig. 6 and Fig. 7, Fig. 7 is according to the overvoltage protection depicted in second embodiment of the invention Circuit diagram.The circuit diagram illustrated similar in appearance to Fig. 2, in first embodiment and second embodiment, for data Signal SD_P, SD_N, secondary signal S2_P, S2_N and the first signal S1 signal transacting and the first NMOS Transistor 210, the first capacitor 220, the first transistor 231, second transistor 233, third transistor 235, The implementation of 4th transistor 237, the first buffer 262 and the second buffer 264 is identical.Using the present embodiment Person should can understand the embodiment of each element in Fig. 6 and Fig. 7 from Fig. 2 explanation.

In the circuit structure of the present embodiment, second switch 650 can be formed by one or more MOS transistors. In the figure 7, second switch 650 is realized by the switch for possessing four end points.Second switch 650 has control terminal 750a (control terminal as second switch 650), first end 750b (first end as second switch 650), the second end 750c and the 3rd end 750d (the second end as second switch 650).It is by that second load, which provides circuit 660, Two capacitors 760 are realized, and have first end 760a and the second end 760b.Wherein, second capacitor 760 First end 760a couples the 3rd end 750d of second switch 650, and the second end 760b couplings of the second capacitor 760 are defeated Go out the output end 130b of grade circuit 130.

It is noted that in other embodiments of the present invention, the second end 760b of the second capacitor 760 can not also Coupled with the output end 130b of output-stage circuit 130, and select to be coupled to the second end 235c of third transistor 235 Or the first end 237b of second transistor 237.That is, as long as the coupling mode of the second capacitor 760 can Reach another input side of increase output-stage circuit 130 (i.e.：The control terminal 235a of third transistor 235) impedance The purpose of value.The coupling mode of capacitor can be adjusted according to its demand using the present embodiment person, is not limited in this The described coupling mode of invention.

In the present embodiment, the second data-signal SD_2, the 4th signal S3 are in the second nmos pass transistor 750, Signal transfer mode between two capacitors 760, the transistor 237 of third transistor 235 and the 4th is similar in appearance in Fig. 2 Secondary signal S2_P, S2_N and the first signal S1 are in the first nmos pass transistor 210, the first capacitor 220, Signal transfer mode between one transistor 231 and second transistor 233.The present embodiment comes can be by with the second data Signal SD_2 carrys out the signal source of the first end 750b and the 3rd end 750d as conducting second switch 650.It is specific next Say, when the second non-enables of data-signal SD_2 (in the present embodiment, to receive the second data-signal SD_2 of high phase place) When, the first end 750b and the 3rd end 750d of second switch 650 are in open-circuit condition, and the of second switch 650 Two end 750c are then in short-circuit condition with the 3rd end 750d so that the first end 760a of second switch 650 is coupled to Earth terminal.However, when the second data-signal SD_2 enables are (in the present embodiment, to receive the second of low phase position the number It is believed that number SD_2) when, the second data-signal SD_2 of low phase position can turn on the first end 750b of second switch 650 With the 3rd end 750d, the first end 760a of the second capacitor 760 is set to couple the control terminal 235a of third transistor 235, So that the first capacitor 220 is able to temporarily increase the first input end 130a of output-stage circuit 130 impedance.Its Remaining technology contents are referred to above-described embodiment.

The second predrive circuit 670 that the present embodiment Fig. 7 is illustrated can be not required to adjust the voltage domain of signal.Specifically, Second predrive circuit 670 is realized with single ended input amplifier circuit 770, therefore the second predrive circuit 670 With input 770a and output end 770b.The input 770a of single ended input amplifier circuit 770 receives the second number It is believed that number SD_2, and the power end reception system voltage of single ended input amplifier circuit 770.Single ended input amplifier electricity Road 770 can postpone this second data-signal SD_2, and perform anti-lock computing (NOT to the second data-signal SD_2 GATE), to produce the 4th signal S3 and Single-end output this 4th signal S3.Now, the second data-signal SD_2 And the 4th signal S3 voltage domain be all clamped to 0V between 1.8V, single ended input amplifier circuit 770 can not The voltage domain of signal need to be adjusted.

Among a complete signal transduction process, Fig. 7 and Fig. 8 please also refer to.Fig. 8 is according to the present invention the The signal timing diagram of overvoltage protection depicted in two embodiments.Due to data-signal SD_P, SD_N and second Data-signal SD_2 processing is independent operating, therefore, data-signal SD_P, SD_N and the first signal S1, The sequential of secondary signal S2_P, S2_N is identical with Fig. 6.Mainly disclose second switch 650 herein, single ended input is put The operation of subelement in big device circuit 770 and output-stage circuit 130.

In time point t2, single ended input amplifier circuit 770 receives the second data-signal SD_2 reversely inputted. In time point t3, single ended input amplifier circuit 770 postpones the second data-signal SD_2, and the second data are believed Number SD_2 performs the computing of anti-lock (Not gate), to export the 4th reverse signal S3.In time point t4, Because the second data-signal SD_2 is located at low phase position, then the first end 750b and the 3rd end 750d of second switch 650 State in short circuit.Now, the load for the control terminal 237a sides of the 4th transistor 237 becomes big so that the Four signal S3 slowly rise among time point t4 and t5, and output signal Sout then slowly declines.

In summary, overvoltage protection of the invention is had additional before output-stage circuit for temporary increase resistance Anti- first switch and the first load provide circuit.Thereby, when data-signal (e.g., secondary signal) need to be by this mistake When voltage protection transmits, data-signal can be postponed to produce the first signal, and the is turned on by secondary signal One switch, so that the first load provides circuit can increase the sending-end impedance of output-stage circuit when first switch turns on. Also, after sending-end impedance lifting, the first signal of delay is transferred to the output end of output-stage circuit.Such one Come, data-signal can be made to delay its voltage fringe time when passing through output-stage circuit, to avoid asking for electromagnetic interference Topic.In addition, passing through the predrive circuit of the present invention, the voltage domain of signal also can be effectively adjusted, makes the voltage of output Meet the standard specification of USB interface.

Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, therefore Protection scope of the present invention is worked as to be defined depending on appended claims institute defender.

Claims

A kind of 1. overvoltage protection, it is characterised in that including：

Output-stage circuit, possesses first input end to receive the first signal, and according to first signal with the output stage The output end of circuit produces output signal；

First switch, its first end couple the first input end of the output-stage circuit, the control termination of the first switch Receive secondary signal, wherein the first input end receives time point of first signal and is not later than the control terminal of the first switch Receive the time point of the secondary signal；And

First load provides circuit, couples the second end of the first switch,

Wherein first load provides circuit and provides impedance to the first input end when the first switch turns on.
2. overvoltage protection as claimed in claim 1, it is characterised in that further include：

First predrive circuit, the first input end of the output-stage circuit and the control terminal of the first switch are coupled, To postpone the secondary signal to produce first signal.
3. overvoltage protection as claimed in claim 2, it is characterised in that the first predrive circuit includes：

First buffer, the 3rd signal positioned at first voltage domain is received, to produce the second letter positioned at second voltage domain Number；And

Second buffer, receive and postpone the secondary signal to produce first signal, wherein first signal, which is located at, is somebody's turn to do Second voltage domain.
4. overvoltage protection as claimed in claim 3, it is characterised in that first buffer and this second Buffer is all differential amplifier circuit,

Wherein the differential amplifier circuit includes：

Input transistors pair, reference current source is coupled, to provide a pair of inputs, to receive differential wave pair；

Bias control transistor pair, the input transistors pair are coupled, receive bias control voltage respectively；And

Resistance element pair, the bias control transistor pair and system voltage end are coupled, to according to the differential wave pair To produce single-ended or both-end output signal.
5. overvoltage protection as claimed in claim 1, it is characterised in that the output-stage circuit includes：

The first transistor, its control terminal be the output-stage circuit the first input end, the first end of the first transistor Coupling system voltage end；And

Second transistor, its first end couple the second end of the first transistor, the control terminal coupling of the second transistor First reference voltage, and the second end of the second transistor is the output end of the output-stage circuit.
6. overvoltage protection as claimed in claim 1, it is characterised in that first load, which provides circuit, to be included：

First capacitor, its first end couple second end of the first switch, the second end coupling of first capacitor The output end of the output-stage circuit.
7. overvoltage protection as claimed in claim 1, it is characterised in that when the non-enable of the secondary signal, The first end that first load provides circuit is coupled the system voltage end by the first switch,

When the secondary signal enable, the first end that first load provides circuit is coupled the output by the first switch The first input end of level circuit.
8. overvoltage protection as claimed in claim 1, it is characterised in that when the non-enable of the secondary signal, The first switch provides first load in the circuit between the first end of circuit and the first input end of the output-stage circuit Cut-off,

When the secondary signal enable, the first end that first load provides circuit is coupled the output by the first switch The first input end of level circuit.
9. overvoltage protection as claimed in claim 1, it is characterised in that the output-stage circuit further includes second Input to receive the 4th signal, also,

The overvoltage protection further includes：

Second switch, its first end couple second input of the output-stage circuit, the control termination of the second switch The 5th signal is received, wherein the 4th signal is by the 5th signal postponed；And

Second load provides circuit, couples the second end of the second switch,

Wherein second load provides circuit and provides impedance to second input when the second switch turns on.
10. overvoltage protection as claimed in claim 8, it is characterised in that further include：

Second predrive circuit, second input of the output-stage circuit and the control terminal of the second switch are coupled, To postpone the 5th signal to produce the 4th signal.
11. overvoltage protection as claimed in claim 9, it is characterised in that the second predrive circuit is Single ended input amplifier circuit,

The input of the wherein single ended input amplifier circuit receives the 5th signal, the single ended input amplifier circuit Power end reception system voltage, the output end of the single ended input amplifier circuit according to the 5th signal is single-ended should with output 4th signal.
12. overvoltage protection as claimed in claim 8, it is characterised in that the output-stage circuit further includes：

Third transistor, its control terminal be the output-stage circuit second input, the first end of the third transistor Couple earth terminal；And

4th transistor, its first end couple the second end of the third transistor, the control terminal coupling of the 4th transistor Second reference voltage, and the second end of the 4th transistor couples the output end of the output-stage circuit.
13. overvoltage protection as claimed in claim 8, it is characterised in that second load, which provides circuit, to be included：

Second capacitor, its first end couple second end of the second switch, the second end coupling of second capacitor The output end of the output-stage circuit.
14. overvoltage protection as claimed in claim 8, it is characterised in that when the 5th non-enable of signal When, the first end that second load provides circuit is coupled the earth terminal by the second switch,

When the 5th signal enable, the first end that second load provides circuit is coupled the output by the second switch Second input of level circuit.