CN104052454B - Level shifter for high density integrated circuits - Google Patents
Level shifter for high density integrated circuits Download PDFInfo
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- CN104052454B CN104052454B CN201410084380.1A CN201410084380A CN104052454B CN 104052454 B CN104052454 B CN 104052454B CN 201410084380 A CN201410084380 A CN 201410084380A CN 104052454 B CN104052454 B CN 104052454B
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Abstract
A level shifter for converting between voltages of a core voltage range to voltages within a larger I/O voltage range. The level shifter has interconnected transistors implemented as core devices operable within the core voltage range. The level shifter is connected to first and second power connections at the I/O voltage range. A voltage clamping element implemented as a core device has a threshold voltage greater than or equal to the difference between the I/O voltage range and the core voltage range and configured to prevent overstressing the transistors with voltages beyond the core voltage range. The input to the level shifter is within the core voltage range. The level shifter output signal has a high level at the high voltage of the I/O voltage range and a low level at approximately one threshold voltage above the low voltage level of the core voltage range.
Description
Cross-Reference to Related Applications
This application claims in the submission of on March 13rd, 2013 according to the 119th article of co-pending U.S. of United States Code No. 35
The priority of state's Provisional Patent Application No. the 61/778th, 479, entire contents are hereby expressly incorporated by reference.
Technical field
Present invention relates in general to circuit, integrated more particularly, to such as system level chip (" SOC ") and/or 3D
The level translator (level shifter) that the high density integrated circuit of circuit (" 3D IC ") is used.
Background technology
In various high density integrated circuit environment, some parts of such as analog circuit or radio frequency (" RF ") circuit do not have
On the main die (being denoted as SOC main dies sometimes) of integrated circuit.Generally, only high-speed digital circuit (such as standard list
Unit, SRAM, numeral PIL and high-speed memory input/output (" I/O ")) it is located on SOC main dies.Core devices are formed in
Device on this tube core to provide high-speed digital circuit, and their usual speeds of service it is very fast, using relatively low voltage, tool
There is higher integrated level, but be more vulnerable to the impact and damage of overvoltage.
The usual process integrated circuit lead of the I/O in system and with jumbo unit interface (such as with printing electricity
The associated unit interface such as road board trace, cable, compared with sending signal in integrated circuit lead, these interfaces need bigger
Driving power and voltage) between signal transmission.I/O devices are by very fast, the less signal transmission of main die to these its
The part of his larger capacity, and usual transmission signal under high pressure.
Semiconductor standard tissue JEDEC provide at least two with regard to 3D IC application I/O specifications, i.e. Wide I/O and
Wide I/O 2, they are referred to as in the text Wide I/O.Wide I/O specifications are for thousand of individual wide I/O passages
The wide I/O applications of SDRAM (monolithic density) device, wherein direct using chip-chip between memory device and control device
Method of attachment.In Wide I/O, the supply voltage for data input/output buffer is defined as 1.2V ± 5%.However,
Core devices on typical main die work at the lower voltage (such as 0.9V), and if are operated under I/O voltage levels
Then may overload.
In various environment, it is desirable to provide meet the I/O needs of the high density integrated circuit in SOC and 3D IC applications
Level translator.
The content of the invention
According to an aspect of the invention, there is provided a kind of voltage in the range of core voltage and more than core electricity
The level translator changed between voltage in the I/O voltage ranges of pressure scope, level translator includes：Multiple interconnection
Transistor, as the core devices operated with the voltage in the range of core voltage；Input interface, for multiple interconnection
Transistor applies the input signal with the voltage in the range of core voltage；Output interface, coupled to the transistor of multiple interconnection；
First power interface, first for the transistor of multiple interconnection to be connected to the high-voltage level in I/O voltage ranges is electric
Voltage source；Second source interface, for the transistor of multiple interconnection to be connected to the low voltage level in core voltage scope
Second voltage power supply；And voltage clamping element, as core devices and with more than or equal to I/O voltage ranges and core
The threshold voltage of the pressure reduction between voltage range, the transistor for connecting voltage clamping element to prevent multiple interconnection is subject to exceed core
The transistor of the overvoltage of heart voltage range, voltage clamping element and multiple interconnection is configured to provide height output letter to output interface
Number and to output interface provide low-output signal, wherein, high output signal for I/O voltage ranges high-voltage level, and
A low-output signal close threshold voltage bigger than the low voltage level of core voltage scope.
Preferably, voltage clamping element is in a pair of voltage clamping elements, and the transistor bag of multiple interconnection
Include：A pair of input transistors, are connected in cascaded fashion between second source interface and a pair of voltage clamping elements, and
Core devices phase inverter is connected between input interface and an input transistors；And the transistor of a pair of cross coupling, with
Cascade system is connected between voltage clamping element and the first power interface.
Preferably, a pair of input transistors are NMOS core devices, and the transistor of a pair of cross coupling is PMOS cores
Device.
Preferably, the transistor of multiple interconnection also includes remaining transistor AND gate first in the transistor of multiple interconnection is electric
The enable transistor of a connection in source interface and second source interface.
Preferably, it is that remaining transistor in the transistor of multiple interconnection is connected to into second source interface to enable transistor
NMOS core devices.
Preferably, voltage clamping element is diode.
Preferably, voltage clamping element is the MOS core devices that gate terminal and drain electrode end are shorted together.
Preferably, level translator is suitable for wide I/O applications.
According to a further aspect in the invention, there is provided a kind of system with integrated circuit silicon die, including：Non-core electrocardio
Road, outside integrated circuit silicon die and is suitable to be operated with I/O voltage ranges；Core circuit, positioned at integrated circuit
In silicon die and including the multiple core devices for being suitable to be operated with core voltage scope, core circuit is included for by core
Electrocardio road is connected to multiple level translators of non-core circuit, and using the core for being suitable to be operated with core voltage scope
Realizing core circuit, core voltage scope is less than I/O voltage ranges to device.At least one of multiple level translators level
Converter includes：The transistor of multiple interconnection, as core devices；Input interface, for providing to the transistor of multiple interconnection
Input signal with the voltage in the range of core voltage；Output interface, is connected to the transistor of multiple interconnection；First power supply connects
Mouthful, for the transistor of multiple interconnection to be connected to the first voltage power supply of the high-voltage level in I/O voltage ranges；Second
Power interface, for the transistor of multiple interconnection to be connected to the second voltage electricity of the low voltage level in core voltage scope
Source；And voltage clamping element, its threshold voltage more than or equal to pressure reduction between I/O voltage ranges and core voltage scope,
Connection voltage clamping element is subject to the overvoltage more than core voltage scope, voltage clamping element with the transistor for preventing multiple interconnection
It is configured to provide high output signal to output interface with the transistor of multiple interconnection and provides low output letter to output interface
Number, wherein, high output signal for I/O voltage ranges high-voltage level, and low-output signal is lower than core voltage scope
The big close threshold voltage of voltage level.
Preferably, voltage clamping element is in a pair of voltage clamping elements, and the transistor bag of multiple interconnection
Include：A pair of input transistors, are connected in cascaded fashion between second source interface and a pair of voltage clamping elements, and
Core devices phase inverter is connected between input interface and an input transistors；And the transistor of a pair of cross coupling, with
Cascade system is connected between voltage clamping element and the first power interface.
Preferably, a pair of input transistors are NMOS core devices, and the transistor of a pair of cross coupling is PMOS cores
Device.
Preferably, the transistor of multiple interconnection also includes remaining transistor AND gate first in the transistor of multiple interconnection is electric
The enable transistor of a connection in source interface and second source interface.
Preferably, it is that remaining transistor in the transistor of multiple interconnection is connected to into second source interface to enable transistor
NMOS core devices.
Preferably, voltage clamping element is diode.
Preferably, voltage clamping element is the MOS core devices that gate terminal and drain electrode end are shorted together.
Preferably, level translator is suitable to wide I/O applications.
According to another aspect of the invention, there is provided a kind of to operate for the voltage in the range of core voltage and more than core
The method of the level translator changed between the voltage in the I/O voltage ranges of heart voltage range, including：There is provided level to turn
Parallel operation, electric pressure converter includes the multiple interconnection for being used as to be suitable to the core devices that the voltage in the range of with core voltage is operated
Transistor, input interface, output interface, the first power interface, second source interface and voltage clamping element, voltage clamp bit
The threshold voltage of part more than or equal to pressure reduction between I/O voltage ranges and core voltage scope, connection voltage clamping element with
The transistor for preventing multiple interconnection is subject to exceed the overvoltage of core voltage scope；I/O voltage ranges are provided to the first power interface
High-voltage level；The low voltage level of core voltage scope is provided to second source interface；Apply input letter to input interface
Number, its high level is the high-voltage level of core voltage scope, and its low level is the low voltage level of core voltage scope；
Output signal is received from level translator, its high level is the high-voltage level of I/O voltage ranges, and its low level compares core
A big threshold voltage of the low voltage level of voltage range.
Preferably, the method also includes：Gone up by the way that input signal to be converted to the high-voltage level of core voltage scope
Draw output signal so that the step of output signal of level translator is converted to the high-voltage level of I/O voltage ranges.
Preferably, the method also includes：By input signal to be converted to the low voltage level of core voltage scope come under
Draw output signal so that the output signal of level translator is converted to and is larger about one than the low voltage level of core voltage scope
The step of threshold voltage.
Preferably, the method also includes：By the step for making level translator work to interface applying enable signal is enabled
Suddenly.
Description of the drawings
The element in accompanying drawing is shown below, they are for the purpose of illustration but are not necessarily to scale.
Fig. 1 is the diagram that level translator is realized using core devices MOSFET；
Fig. 2 is the diagram of the system for using the multiple level translators shown in Fig. 1；
Fig. 3 is the flow chart for illustrating level translator shown in operation Fig. 1；And
Fig. 4 shows the emulation of the work wave of level translator shown in Fig. 1.
Specific embodiment
The description of certain exemplary embodiments is intended to be read in conjunction with the accompanying drawings, and accompanying drawing can be considered the one of whole written explanation
Part.Unless otherwise being expressly recited, the otherwise term with regard to engagement, connection etc. and description (such as " connection " and " interconnection ")
Refer to that structure is indirectly fixed directly or by insert structure or is bonded to the relation of another structure, and both may move
Or rigid engagement or relation.Similarly, unless otherwise being expressly recited, otherwise with regard to the term that is electrically coupled etc. and description (such as
" coupling " " connection " and " interconnection ") refer to structure directly or by insert structure indirectly with the pass of another structured communication
System.Similarly, unless otherwise being expressly recited, otherwise with regard to the contact in circuit term and description (such as " pad ", " rail " or
" terminal ") electrical connection of form of ownership is should be read to include, but it is not limited to physically discernible pad, rail or terminal.
In various embodiments, core devices can be used as specified specific size and the manufacturing process of transistor density
The part of (foundry process) is realizing.For example, exist and be suitable for such as network, panel computer and mobile subscriber's product
The manufacture method of the high density integrated circuit of the application of product.
This manufacturing process has the core voltage (Vdd) different from typical case's I/O voltages (Vddq).For example, in some realities
In applying example, core voltage is about 0.85V, 0.9V, 1.0V, 1.05V etc., and typical case's I/O voltages are then higher.For example, at some
In embodiment, I/O voltages are 1.8V I/O and including drive lacking and overdrive change (under and over drive
Variation), such as 1.8V UD 1.2V, 1.8V UD 1.5V.In other embodiments, I/O voltages be 2.5V I/O and
Including drive lacking and overdrive change, such as 2.5V UD 1.8V, 2.5V OD 3.3V.In other embodiment, I/O voltages
It is 1.2V ± 5% for being suitable to Wide I/O or Wide I/O 2 specified by JEDEC.Core voltage mentioned in the present invention and
I/O voltages are actually exemplary, and are contemplated that within the scope of the invention using other voltages.
In certain embodiments, using high-voltage level Vdd be 0.9V ± 10% and low voltage level Vss be ground potential
The technique operated in the range of the core voltage that 0V specifies is realizing disclosed level translator and it is emulated.
Fig. 1 is the diagram of the level translator 100 realized according to the use core devices MOSFET of some embodiments.At this
In example, level translator 100 is designed to be operated with the Vss of core voltage Vdd of 0.9V ± 10% and ground potential 0V
Core devices.Level translator 100 is received from the first voltage by the power supply of 1.2V ± 5% by the first power interface
The electric power of source Vddq rail 101.Level translator 100 is connected to the second voltage source in ground potential 0V by second source interface
Vss rails 102.In other each embodiments, Vss and/or Vssq can be actual ground potential 0V, common reference voltage or not
Same reference voltage.
Fig. 3 discussed further below and Fig. 4 show voltage signal Vin 33, Ven 44, Vout 55, Voutb 99
With the example of Vnd 77.With reference to Fig. 1, Fig. 3 and Fig. 4, level translator 100 has：Input interface 103, it is defeated for receiving voltage
Enter signal Vin 33 (see Fig. 3,4)；Enable interface 104, for receiving signal Ven 44 is enabled (see Fig. 3, Fig. 4)；And output
Interface 105, for providing voltage output signal Vout 55 (see Fig. 3, Fig. 4).Level translator 100 have connecting node 106,
107th, 108 and 109.The voltage level signal for being denoted as Vnd 77 (see Fig. 4) is the voltage at connecting node 107.It is denoted as
The voltage level signal of Voutb 99 (see Fig. 4) is the voltage at connecting node 109.Output interface 105 is used as to provide I/O voltages
In the range of output voltage Vout 55 (see Fig. 3, Fig. 4) output interface.Based on the specification and drawings, people in the art
Member is it should be understood that it is symmetrical and complementary to indicate the part and voltage level of " b " and corresponding part or voltage level.
As shown in figure 1, level translator has the multiple MOS core devices connected between Vddq rails 101 and Vss rails 102
Part.In this example, I/O voltages are defined the low pressure of the high pressure with 1.2V ± 5% and ground potential.The I/O of 1.2V ± 5% is electric
Pressure if full 1.2V ± 5% is put in core devices transistor more than the core voltage scope for discussing before
Individual transistor two ends, then overload is reduced reliability by transistor, and is likely to result in operation failure and permanent damages.
In the embodiment shown, with three NMOS core devices 110,120 and 130 and four PMOS core devices
140th, 150,160 and 170.The connection of MOS core devices is as follows.
The gate terminal of NMOS core devices 110 (being also denoted as MNDB) is connected to the defeated of input interface 103 and phase inverter 180
Enter end, its drain electrode end is connected to the drain and gate of the PMOS core devices 150 at node 108, and its source terminal is connected to
The drain electrode end of the NMOS core devices 120 at node 106.Phase inverter 180 is used as core devices.
The gate terminal of NMOS core devices 120 (being also denoted as MNS) is connected to enable interface 104, and its drain electrode end is connected to
The source terminal of the NMOS core devices 110,130 at node 106, and its source terminal is connected to Vss rails 102.
The gate terminal of NMOS core devices 130 (being also denoted as MND) is connected to the output end of phase inverter 180, its source terminal
Node 106 is connected to, and its drain electrode end is connected to the grid and drain electrode end of the PMOS core devices 140 at node 107.
The gate terminal of PMOS core devices 140 (being also denoted as MPI) is shorted to its drain electrode end, and they are connected to node
The drain electrode end of the NMOS 130 at 107, its source terminal is connected to the PMOS core devices at the node with output interface 105
160 drain electrode end and the grid of PMOS core devices 170.
The gate terminal of PMOS core devices 150 (being also denoted as MPIB) is shorted to its drain electrode end, and they are connected to node
The drain electrode end of the NMOS core devices 110 at 108, its source terminal is connected to the drain electrode of the PMOS core devices 170 at node 109
End and the gate terminal of PMOS core devices 160.
The gate terminal of PMOS core devices 160 (being also denoted as MPU) is connected to the PMOS core devices 170 at node 109
Drain electrode end and PMOS core devices 150 source terminal, its drain electrode end is connected to the PMOS at the node with output interface 105
The gate terminal of core devices 170 and the source terminal of PMOS core devices 140, and its source terminal is connected to Vddq rails 101.
The gate terminal of PMOS core devices 170 (being also denoted as MPUB) is connected at the node with output interface 105
The drain electrode end of PMOS core devices 160 and the source terminal of PMOS core devices 140, its drain electrode end is connected at node 109
The gate terminal of PMOS core devices 160 and the source terminal of PMOS core devices 150, and its source terminal is connected to Vddq rails 101.
Level translator 100 is only realized using core devices, so as to by 33 turns of level Vin in the range of core voltage
It is right in I/O voltage ranges (it is predetermined threshold voltage levels (" Vth ") more than Vss that high level is Vddq and low level) to be changed to
Answer level Vout 55.
Level translator 100 has two cross-linked MOS core devices, is expressed as cross-linked PMOS cores device
Part 160,170, their source terminal is connected to Vddq rails 101.
Level translator 100 has two voltage clamping MOS devices, is expressed as two PMOS core devices 140,150, it
Gate terminal and drain electrode end short circuit so that they are used as diode and predetermined according to selected PMOS core devices 140,150
Threshold voltage (" Vth ") characteristic is providing corresponding voltage clamping function.Advantageously, Vth is selected with more than I/O voltage ranges
Voltage difference between the high level of high level and core voltage scope.The typical Vth values of SVT devices are 0.4V to 0.5V.At this
In embodiment, Vth deducts minimum desired value Vdd (that is, 0.9V-10% or 0.81V) more than 1.2V+5% (that is, 1.26V).Be given
The tolerance of Vddq and Vdd, selects PMOS core devices 140,150 to cause Vth characteristic values to be at least 0.45V.In this example,
Vth is 0.5V.The source terminal of these PMOS core devices is cascaded to the drain electrode end of cross-linked MOS core devices.
Level translator 100 has two input MOS core devices, is expressed as NMOS core devices 130,110, they
Grid is connected to the input interface 103 for receiving Vin 33, but in the grid supply Vin 33 to NMOS core devices 130
First with phase inverter 180 make the polarity inversion of Vin 33 before.The drain electrode end level of two input MOS core devices is coupled to voltage clamping
The drain electrode end of MOS core devices.
Level translator 100 also has an enable MOS core devices, is expressed as NMOS core devices 120, and its grid connects
It is connected to the enable interface 104 for receiving Ven 44.The source electrode of NMOS core devices 120 is connected to Vss and its drain electrode connection
To input MOS core devices, restriction is so defined to leakage current.
In the course of the work, Vin 33 (core operating voltage) is converted to (high level of Vout 55 by level translator 100
It is the I/O voltages between the Vth more than Vss for Vddq and low level).Ven 44 is set as high level so that NMOS core devices
120 conductings, due to being connected to Vss rails 102, so Vns 66 is about 0V.In enabled state, level translator 100 is described
For drop-down Vout 55, this is started by the way that Vin 33 is changed into into low level, will Vin 33 be converted to from high level Vdd it is low
Level 0V.For pull-up action, circuit is operated under symmetrical and complement mode, and this is understood by the description to drop-down action.
When Vin 33 is changed into low level, NMOS core devices 110 end, and the output of phase inverter 180 will be high electric
Pressure (Vdd) applies to the grid of NMOS core devices 130, switches it on and drives Vnd 77 due to being connected to Vss rails 102
To close 0V.When initial, Vout 55 is 1.2V, and the pressure reduction at the two ends of PMOS core devices 140 is about the magnitude of voltage.With
Vnd 77 is down to close 0V, and PMOS core devices 140 will be turned on, and be started Vout 55 is drop-down towards Vnd 77.However, because
It connects as diode, once so the pressure reduction between its source voltage (Vout 55) and its drain voltage (Vnd 77) is little
In or equal to its Vth, then PMOS core devices 140 will end.Thus, once Vout 55 is pulled down to Vth plus Vnd 77
When, PMOS core devices 140 will end, and Vout 55 will be restricted to voltages of the Vth plus Vnd 77.Because Vnd 77
For 0V or close 0V, so Vout is restricted to Vth.The pressure reduction at the two ends of PMOS core devices 160 under the state is Vddq
(1.2V ± 5%) deducts Vth.For example, when it is 0.4V that Vddq is 1.2V and Vth, PMOS core devices 160 are by the voltage for bearing
About 0.8Vds, this is not at overvoltage condition.
Fig. 2 is with integrated circuit silicon die 2001 and the non-core circuit being not in integrated circuit silicon die 2001
The diagram of 2003 electronic system 2000.In certain embodiments, electricity is connected using the method for the direct attachment of chip-chip
Road.Electronic system 2000 has the core circuit 2002 being arranged in integrated circuit silicon die 2001, and including with reference to Fig. 1 institutes
State the multiple core devices operated with core voltage Vdd and Vss.
Core devices include multiple level translators 2200,2300,2400.Such as the level translator discussed with reference to Fig. 1
100, level translator 2200 has input voltage interface 2203, enables interface 2204, output voltage interface 2205, and connects
To Vddq rails 2201 and Vss rails 2202.It should be understood that not needing physics pad at output interface 2205, but mark can be passed through
Line and other conventional methods of attachment are being attached.Level translator 2300 with 2400 have represented using similar reference number
Similar connection.Internal part in each level translator is all referring to shown in Fig. 1 and describing.Three level shown in Fig. 2 turn
Parallel operation is merely to illustrate.In fact, system 2000 has the array of substantial amounts of level translator, do not show for particular use
Go out.Core circuit 2002 is coupled to non-core circuit 2003 by level translator.Advantageously, as on 2 27th, 2013 submit to
U.S. Patent Application Serial Number is 13/778, (entire contents are hereby expressly incorporated by reference) disclosed in 380, and each level turns
The output of parallel operation can be applicable in rear core devices driver (core devices only post driver) or
Multiple input interfaces.In such some embodiment (not shown), rear core devices driver is arranged on integrated circuit silicon die
On 2001, and can be core circuit 2002 a part, they are located at level translator 2200,2300 and 2400 and non-core
Between electrocardio road 2003.
Fig. 3 is the flow chart of the operation for illustrating level translator 100 shown in Fig. 1.In step 3100, with reference to shown in Fig. 1
Level translator 100 is provided with description.In step 3125, to Vddq rails 101 high voltage 1.2V ± 5% is applied.In step
In 3150, to rail 102 low reference voltage is applied.
In step 3175, the enable signal Ven 44 for putting on enable interface 104 is arranged to high level, and it is Vdd.
When Ven 44 is arranged to low level, NMOS core devices are in cut-off region, and level translator 100 quits work.
In step 3200, to first interface 103 input voltage signal Vin 33 is applied, voltage signal has high level
Vdd and low level Vss.In operation, level translator 100 exports corresponding high level Vddq and low level Vth more than Vss
Vout 55.
Fig. 4 shows the simulation waveform of the operation of level translator 100.Waveform is shown as having as the time (to receive
Second be unit) function amplitude () in units of volt or millivolt (as shown in the figure).Fig. 4 to show and be set to high level in Ven 44
When level translator 100 simulation operations, and imitated under the conditions of typical process angle (adopt TT angles), 1 × Vdd and 25 DEG C
Very.Curve 4100 in Fig. 4 shows the input waveform of Vin 33.Curve 4200 shows the incoming wave by shown in curve 4100
Vout 55 and Voutb waveforms that shape is obtained.Curve 4300 shows the waveforms of Vout 55 and the voltage clamping waveform at node 107
The comparison of Vnd 77.Curve 4300 determines that the pressure reduction between Vout 55 and Vnd 77 is restricted to the threshold of PMOS core devices 140
Threshold voltage, shows to the description of circuit operation it is correct, even and if MOS core devices be operated between 0V rails and Vddq rails
Also it is in overvoltage condition without MOS core devices.
Without in the case of voltage clamping element 140,150, Vout can as little as 0V, bear PMOS core devices 160
Vds is the overvoltage of Vddq (1.2V ± 5%).Similarly, when Vout is Vddq, NMOS 130 will be made to bear Vds for full value
The overvoltage of Vddq.Complementary MOS device 170,110 under complementary state similar will be in overvoltage condition.Voltage clamping element 140,
150 advantageously prevent core devices from overvoltage occur.As shown in curve 4300, the simulation waveform of level translator 100 determines Vout
Scope between Vddq to Vth.So, the emulation shown in Fig. 4 shows that level translator 100 does not make during operation MOS
Core devices are subject to overvoltage, even if level translator uses more than the I/O voltages of the operating voltage range of core devices.
Applicant also calculates the working time of the voltage at each node and level translator 100 to determine emulation level
Converter does not make any one MOS core devices be subject to overvoltage and to protect during each process corner all hold sufficiently reliability.
The process corner being computed includes：A () standard angle (is defined as TT (typical typical)), be operated in 1 × Vdd and 25 DEG C；
B the low temperature angle (being defined as SS (slow slow)) under () worst condition, is operated in 0.9 × Vdd and -40 DEG C；And (c) is maximum
Reveal angle (being defined as FF (fast fast)), be operated in 1.1 × Vdd and 125 DEG C.
In an alternative embodiment, the MOS core devices with any threshold voltage can be adopted, it is suitable for according to this specification
Remaining part part.Similarly, the disclosed embodiments may be adapted to the maximum working voltage of any technique core devices, from threshold voltage
So that maximum working voltage adds upper threshold voltage to be more than I/O voltage ranges.In an alternative embodiment, voltage clamping element can be carried
Part for being similar to the such as diode or other compressor circuits of voltage clamping Vth is substituted.In certain embodiments, MOS cores
Device is with standard threshold voltage transistor (SVT) realization.According to purpose of design, usually leakage current and speed, other optional realities
Apply example use MOS core devices, its can using low threshold voltage transistor (LVT), high threshold voltage transistors (HVT), other
Available threshold level and combinations thereof are realizing.It should be appreciated by those skilled in the art that in addition to the mosfet its can be used
He implements other embodiment by transistor technology.Similarly, the complementary electrical shown in Fig. 1 can be realized using complementary voltage and component
Road.Vss rails described in text is connected to the earth terminal that current potential is 0V.Term " earth terminal " be used for include common reference voltage node,
But require no connection to real earth terminal.In an alternative embodiment, Vss and Vssq are connected to common electric voltage domain.Alternatively, exist
Vssq can be exchanged with Vss in some embodiments.In an alternative embodiment, the low electricity of I/O voltage ranges and/or core voltage scope
Voltage level can be some other reference voltage levels for including negative voltage.In an alternative embodiment, level translator 100 will be in
The input signal of I/O voltage ranges is down-converted to core operation voltage, and by the signal output in core voltage for
Other core devices are used.It should be appreciated by those skilled in the art that the concrete speed during design can be changed to meet given I/O problems
Degree, driving and reliability requirement, and specification or design parameter.
With can be compared with selecting technology, under each embodiment causes the I/O devices that SOC or 3D IC tube cores are used to have and reduce
The circuit area of line (tapeout) mask costs, manufacturing cycle and requirement.For example, using core devices rather than tradition I/O devices
The larger part outside tube core is located in part and saves the manufacturing cycle realizing level driver.The technique effect of acquirement is with each
I/O passages quantify for unit, and are multiplied by the number of level translator used in given system and obtain total amount.Some realities
Applying example can reduce by 4 to 5 times of offline mask costs.Each embodiment allows core devices level translator to be used for SOC or 3D IC
Tube core can so reduce required area and take into account without providing extra intermediate bias voltage in each I/O unit
Consideration in terms of power and stability.Because core devices generally than tube core outside I/O devices have and preferably reduce factor,
So equally increasing transplanting advantage during technogenic migration.
Some embodiments are advantageous in that static discharge (" the ESD ") protection device that need not be added.For example, if
New extra intermediate bias voltage is needed to carry out Implement Core device level converter, then additional ESD protection device needs to be interconnected in
Intermediate bias voltage and each exist Voltage rails Vdd, Vss, between Vddq and Vssq, therefore this will make ESD networks die down.
In some aspects with embodiment in, disclose a kind of level translator, using the system and level of level translator
The method of operating of converter.In the first aspect, a kind of level translator is disclosed, for the voltage in the range of core voltage
Changed and the voltage in the I/O voltage ranges bigger than core voltage scope between.The level translator has multiple interconnection
, the transistor used as core devices, they are suitable to the voltage in the range of with core voltage and are operated.Level translator
Input interface be used to provide the input signal with the voltage in the range of core voltage to the transistor of multiple interconnection.Output connects
Mouth is connected to the transistor of multiple interconnection.First power interface is used to that the transistor of multiple interconnection to be connected in I/O voltages
First supply voltage of the high-voltage level of scope, and second source interface be used for the transistor of multiple interconnection is connected to into work
For the second source voltage of the low voltage level of core voltage scope.The threshold value electricity of the voltage clamping element that level translator has
Pressure is more than or equal to the pressure reduction between I/O voltage ranges and core voltage scope.Connection voltage clamping element is multiple mutual to prevent
Transistor even is subject to the overvoltage outside core voltage scope.Voltage clamping element and the transistor of multiple interconnection are configured to defeated
Outgoing interface provides high output signal (high-voltage level in I/O voltage ranges) or provides low-output signal (ratio to output interface
Low voltage level in core voltage scope is larger about a threshold voltage).
In second aspect, a kind of system has at least one integrated circuit silicon die.The system has positioned at integrated electricity
Non-core circuit outside the silicon die of road and the core circuit in integrated circuit silicon die.Core circuit includes being suitable to core
Heart voltage range operates multiple core devices, including for core circuit to be connected to multiple level conversions of non-core circuit
Device.Level translator, wherein at least one level conversion are realized using the core devices for being suitable to be operated with core voltage scope
Device according to described in first aspect realizing.
In a third aspect, a kind of voltage being suitable in the range of core voltage and bigger than core voltage scope is disclosed
The method of operating of the level translator changed between the voltage in I/O voltage ranges.The method includes providing with multiple
The level translator of the transistor of interconnection, the transistor of multiple interconnection is grasped as the voltage being suitable in the range of with core voltage
The core devices of work.The level translator for being provided also has input interface, output interface, the first power interface, second source
Interface and voltage clamping element.The threshold voltage of voltage clamping element is more than or equal to I/O voltage ranges and core voltage scope
Between pressure reduction.Connection voltage clamping element is subject to the overvoltage outside core voltage scope with the transistor for preventing multiple interconnection.Should
Method also includes providing I/O voltages to the high voltage in the first power interface offer I/O voltage ranges and to second source interface
Low-voltage in scope.The method includes applying input signal to the first input interface, and its high level is core voltage scope
High-voltage level and low level for core voltage scope low voltage level.The height electricity of the output signal received from level translator
Put down the threshold value electricity that high-voltage level and low level for I/O voltage ranges are the low voltage level more than core voltage scope
Pressure.
In certain embodiments, voltage clamping element is in a pair of voltage clamping elements, and multiple interconnection
Transistor includes the transistor that a pair of input transistors and a pair of cross are coupled.A pair of input transistors connect in cascaded fashion respectively
It is connected between second source interface and a pair of voltage clamping elements, and core devices phase inverter is connected to the defeated of level translator
Between incoming interface and an input transistors.The transistor of a pair of cross coupling is connected in cascaded fashion respectively voltage clamp bit
Between part and the first power interface.In certain embodiments, a pair of input transistors are NMOS core devices, and a pair of cross coupling
The transistor of conjunction is PMOS core devices.
In certain embodiments, the transistor of multiple interconnection includes making the remaining transistor AND gate in the transistor of multiple interconnection
The enable transistor of a connection in the first and second power interfaces.In certain embodiments, enable transistor be will be multiple
Remaining transistor in the transistor of interconnection is connected to the NMOS core devices of second source interface.In certain embodiments, electricity
Pressing tongs bit unit is diode.In certain embodiments, voltage clamping element is that its gate terminal and drain electrode end are shorted together
MOS core devices.In certain embodiments, level translator is suitable to wide I/O applications.
In certain embodiments, level conversion is pulled up by the way that input signal to be converted to the high voltage of core voltage scope
The output signal of device so that the output signal of level translator is converted to the high voltage of I/O voltage ranges.In some embodiments
In, by the output signal that input signal is converted to the low-voltage of core voltage scope and drop-down level translator so that electricity
The output signal of flat turn parallel operation is changed into a close threshold voltage bigger than the low-voltage of core voltage scope.In some embodiments
In, apply to its enable interface to make level translator work by the way that signal will be enabled.
Although describing subject matter according to exemplary embodiment, this is not limited to that.Conversely, claims should
It is construed broadly other modifications and embodiment can carry out including those skilled in the art.
Claims (20)
1. a kind of voltage in the range of core voltage and more than the electricity in the I/O voltage ranges of the core voltage scope
The level translator changed between pressure, wherein, the core voltage scope is electricity from high core voltage levels to low core
Voltage level, and the I/O voltage ranges are the level translator bags from high I/O voltage levels to low I/O voltage levels
Include：
The transistor of multiple interconnection, as the core devices operated with the voltage in the range of the core voltage；
Input interface, for applying the input with the voltage in the range of the core voltage to the transistor of the plurality of interconnection
Signal；
Output interface, coupled to the transistor of the plurality of interconnection；
First power interface, for the transistor of the plurality of interconnection to be connected to first in the high I/O voltage levels
Voltage source；
Second source interface, for the transistor of the plurality of interconnection to be connected to second in the low core voltage levels
Voltage source；And
Voltage clamping element, as core devices and with more than or equal to the I/O voltage ranges and the core voltage model
The threshold voltage of the pressure reduction between enclosing, is connected the voltage clamping element and is exceeded with the transistor for preventing the plurality of interconnection
The transistor of the overvoltage of the core voltage scope, the voltage clamping element and the plurality of interconnection is configured to：When described
When input signal is the high core voltage levels, high output signal is provided and when the input signal to the output interface
For the low core voltage levels when, provide low-output signal to the output interface, wherein, the high output signal is for described
High I/O voltage levels, and a low-output signal close threshold voltage bigger than the low core voltage levels.
2. level translator according to claim 1, wherein, the voltage clamping element is in a pair of voltage clamping elements
One, and the transistor of the plurality of interconnection includes：
A pair of input transistors, are connected in cascaded fashion the second source interface and the pair of voltage clamping element
Between, and core devices phase inverter is connected between the input interface and an input transistors；And
The transistor of a pair of cross coupling, is connected in cascaded fashion the voltage clamping element and first power supply connects
Between mouthful.
3. level translator according to claim 2, wherein, the pair of input transistors are NMOS core devices, and
The pair of cross-linked transistor is PMOS core devices.
4. level translator according to claim 1, wherein, the transistor of the plurality of interconnection also includes will be the plurality of
A connection in first power interface and the second source interface described in remaining transistor AND gate in the transistor of interconnection
Enable transistor.
5. level translator according to claim 4, wherein, the enable transistor is by the crystal of the plurality of interconnection
Remaining transistor in pipe is connected to the NMOS core devices of the second source interface.
6. level translator according to claim 1, wherein, the voltage clamping element is diode.
7. level translator according to claim 1, wherein, the voltage clamping element is gate terminal and drain electrode end short circuit
MOS core devices together.
8. level translator according to claim 1, wherein, the level translator is suitable for wide I/O applications.
9. a kind of system with integrated circuit silicon die, the system includes：
Non-core circuit, outside the integrated circuit silicon die and is suitable to from high I/O voltage levels to low I/O voltages
The I/O voltage ranges of level are operated；
Core circuit, in the integrated circuit silicon die and including be suitable to from high core voltage levels to low core electricity
Multiple core devices that the core voltage scope of voltage level is operated, the core circuit is included for by the core circuit
Multiple level translators of the non-core circuit are connected to, and using the institute for being suitable to be operated with the core voltage scope
State core devices to realize the core circuit, the core voltage scope is less than the I/O voltage ranges, the plurality of level
At least one of converter level translator includes：
The transistor of multiple interconnection, as core devices；
Input interface, for providing the input with the voltage in the range of the core voltage to the transistor of the plurality of interconnection
Signal；
Output interface, is connected to the transistor of the plurality of interconnection；
First power interface, for the transistor of the plurality of interconnection to be connected to first in the high I/O voltage levels
Voltage source；
Second source interface, for the transistor of the plurality of interconnection to be connected to second in the low core voltage levels
Voltage source；And
Voltage clamping element, its threshold voltage is more than or equal between the I/O voltage ranges and the core voltage scope
Pressure reduction, the transistor for connecting the voltage clamping element to prevent the plurality of interconnection is subject to more than the core voltage scope
The transistor of overvoltage, the voltage clamping element and the plurality of interconnection is configured to：When the input signal is the high core
During electrocardio voltage level, high output signal is provided and when the input signal is the low core voltage electricity to the output interface
At ordinary times, low-output signal is provided to the output interface, wherein, the high output signal is the high I/O voltage levels, and
A low-output signal close threshold voltage bigger than the low core voltage levels.
10. the system with integrated circuit silicon die according to claim 9, the voltage clamping element is a pair of voltages
One in clamp members, and the transistor of the plurality of interconnection includes：
A pair of input transistors, are connected in cascaded fashion the second source interface and the pair of voltage clamping element
Between, and core devices phase inverter is connected between the input interface and an input transistors；And
The transistor of a pair of cross coupling, is connected in cascaded fashion the voltage clamping element and first power supply connects
Between mouthful.
11. systems with integrated circuit silicon die according to claim 10, wherein, the pair of input transistors are
NMOS core devices, and the pair of cross-linked transistor is PMOS core devices.
12. systems with integrated circuit silicon die according to claim 9, wherein, the transistor of the plurality of interconnection
Also include connecing the first power interface and the second source described in remaining transistor AND gate in the transistor of the plurality of interconnection
The enable transistor of a connection in mouthful.
13. systems with integrated circuit silicon die according to claim 12, wherein, the enable transistor is by institute
State the NMOS core devices that remaining transistor in the transistor of multiple interconnection is connected to the second source interface.
14. systems with integrated circuit silicon die according to claim 9, wherein, the voltage clamping element is two
Pole pipe.
15. systems with integrated circuit silicon die according to claim 9, wherein, the voltage clamping element is grid
The MOS core devices that extreme and drain electrode end is shorted together.
16. the system with integrated circuit silicon die according to claim 9, wherein, the level translator is suitable to width
I/O is applied.
17. a kind of operate for the voltage in the range of core voltage and the I/O voltage ranges more than the core voltage scope
The method of the level translator changed between interior voltage, wherein, the core voltage scope is from high core voltage electricity
Put down to low core voltage levels, and the I/O voltage ranges are from high I/O voltage levels to low I/O voltage levels, the side
Method includes：
The level translator is provided, the level translator includes being used as to be suitable to enter with the voltage in the range of the core voltage
The transistor of multiple interconnection of the core devices of row operation, input interface, output interface, the first power interface, second source connect
Mouth and voltage clamping element, the threshold voltage of the voltage clamping element is more than or equal to the I/O voltage ranges and the core
Pressure reduction between heart voltage range, the transistor for connecting the voltage clamping element to prevent the plurality of interconnection is subject to exceed institute
State the overvoltage of core voltage scope；
The high I/O voltage levels are provided to first power interface；
The low core voltage levels are provided to the second source interface；
The input signal in the range of the core voltage is applied to the input interface；
Output signal is received from the level translator, it is described defeated when the input signal is the high core voltage levels
It is the high I/O voltage levels to go out signal, and when the input signal is the low core voltage levels, the output letter
A number threshold voltage bigger than the low core voltage levels.
The method of 18. operation level converters according to claim 17, also includes：By the way that the input signal is changed
The output signal is pulled up to the high-voltage level of the core voltage scope so that the output of the level translator
The step of signal is converted to the high-voltage level of the I/O voltage ranges.
The method of 19. operation level converters according to claim 17, also includes：By the way that the input signal is changed
Low voltage level to the core voltage scope carrys out the drop-down output signal so that the output of the level translator
Signal is converted to the step of being larger about a threshold voltage than the low voltage level of the core voltage scope.
The method of 20. operation level converters according to claim 17, also includes：By applying to enable to enable interface
The step of signal is to make the level translator work.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361778479P | 2013-03-13 | 2013-03-13 | |
| US61/778,479 | 2013-03-13 | ||
| US13/833,975 | 2013-03-15 | ||
| US13/833,975 US9197199B2 (en) | 2013-03-13 | 2013-03-15 | Level shifter for high density integrated circuits |
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| CN104052454A CN104052454A (en) | 2014-09-17 |
| CN104052454B true CN104052454B (en) | 2017-04-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9490813B2 (en) * | 2014-11-06 | 2016-11-08 | Qualcomm Incorporated | High-speed level-shifting multiplexer |
| CN106301349B (en) * | 2015-05-14 | 2019-09-20 | 中芯国际集成电路制造(上海)有限公司 | High-voltage level conversion circuit |
| US9866205B2 (en) * | 2015-11-16 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Level conversion device and method |
| US9859893B1 (en) * | 2016-06-30 | 2018-01-02 | Qualcomm Incorporated | High speed voltage level shifter |
| CN110299909B (en) * | 2018-03-21 | 2023-05-16 | 联发科技股份有限公司 | Input interface circuit |
| CN108962309B (en) * | 2018-06-29 | 2021-12-28 | 西安交通大学 | Stacked SRAM array structure with high energy utilization rate and low power consumption |
| US10700683B1 (en) * | 2018-08-28 | 2020-06-30 | Qualcomm Incorporated | Dynamic power supply shifting |
| CN112491408B (en) * | 2019-09-11 | 2022-07-29 | 成都锐成芯微科技股份有限公司 | Level conversion circuit |
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