CN104852725A - Output driving resistor in interface circuit on chip - Google Patents
Output driving resistor in interface circuit on chip Download PDFInfo
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- CN104852725A CN104852725A CN201510241187.9A CN201510241187A CN104852725A CN 104852725 A CN104852725 A CN 104852725A CN 201510241187 A CN201510241187 A CN 201510241187A CN 104852725 A CN104852725 A CN 104852725A
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Abstract
The present invention provides an output driving resistor in the interface circuit on a chip. The output driving resistor comprises a plurality of resistor units, ad each resistor unit comprises a resistor which is connected in series between a power supply end and an output end or a grounding end and the output end and a plurality of MOS transistors which are connected in parallel. The gate of each MOS transistor is connected to a corresponding control signal, the turn-on and turn-off of the corresponding MOS transistor can be controlled through the corresponding control signal, and the number of turn-on MOS transistors in each resistor unit is adjusted through the control signal such that the resistance value of the resistor unit is a predetermined resistor value. Compared with the prior art, through the parallel connection of a plurality of CMOS tubes and then the series connection of the CMOS tubes and the resistor, a driving resistor unit is formed, the driving resistor unit is configured to be different output driving resistors according to the actual working needs, in this way, under the premise of ensuring output resistance magnitude requirement and resistance linearity requirement, the occupied chip area is greatly reduced, and the cost is saved.
Description
[technical field]
The present invention relates to Design Technique of Interface field, particularly a kind ofly output in interface circuit on the chip of saving chip area can drive resistance.
[background technology]
DDR (Double Data Rate, Double Data Rate) technology, namely all data are transmitted at the rising edge of clock and trailing edge, when keeping clock rate constant, data transfer rate can be doubled, therefore, ddr interface is widely used in the interconnection between chip, as ASIC (Application Specific IntegratedCircuit, application-specific integrated circuit (ASIC)) and SDRAM (Synchronous Dynamic Random AccessMemory, synchronous DRAM) between interface.
Along with the raising of operating rate, existing a lot of ddr interface (such as, DDR2/DDR3/LPDDR2/LPDDR3 interface etc.) not only drive the size of resistance to have requirement to exporting, and drive the linearity of resistance also to have stricter requirement to exporting, it requires that resistance remains within the specific limits (such as, +/-10%) from the change procedure of 0 to supply voltage at output voltage.
But due to the limitation of CMOS (Complementary Metal Oxide Semiconductor) pipe itself, usually CMOS tube series resistance is needed to make junior unit to improve the linearity of resistance, then the quantity by adjusting junior unit further reaches the size of required resistance, such as, small resistor unit is made by CMOS tube series resistance, junior unit adjusts the large resistance unit of 240 ohm according to the change of technique, temperature and voltage, large resistance unit needs to be configured to 34.4 according to real work, the different outputs such as 40,48 ohm drive resistance.So arrange and will cause junior unit One's name is legion, thus cause chip area shared by CMOS tube and resistance excessive, be unfavorable for that chip is miniaturized.
Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.
[summary of the invention]
The object of the present invention is to provide the output in the interface circuit on a kind of chip to drive resistance, it ensureing to export under the prerequisite driving resistance sizes requirement and resistance linearity, significantly can reduce shared chip area, saving cost.
In order to solve the problem, the output that the invention provides in the interface circuit on a kind of chip drives resistance, it comprises: several resistance units, each resistance unit comprises the MOS transistor being series at power end and output or a resistance between earth terminal and output and several parallel connections, the grid of each MOS transistor is connected with a corresponding control signal, conducting or the shutoff of corresponding MOS transistor can be controlled by the control signal of correspondence, the number of the MOS transistor of the conducting in each resistance unit is adjusted to make the resistance value of this resistance unit for predetermined resistance by described control signal.
Further, described MOS transistor is PMOS transistor, and the PMOS transistor of described resistance and some parallel connections is series between power end and output.
Further, the source electrode of each PMOS transistor is all connected with power end, and the drain electrode of each PMOS transistor is all connected with one end of described resistance, and the other end of described resistance is connected with output.
Further, the drain electrode of each PMOS transistor is all connected with output, and the source electrode of each PMOS transistor is all connected with one end of described resistance, and the other end of described resistance is connected with power end.
Further, described predetermined resistance is 240 ohm.
Further, described MOS transistor is nmos pass transistor, and the nmos pass transistor of described resistance and some parallel connections is series between earth terminal and output.
Further, the source electrode of each nmos pass transistor is all connected with earth terminal, and the drain electrode of each nmos pass transistor is all connected with one end of described resistance, and the other end of described resistance is connected with output VO.
Further, the drain electrode of each nmos pass transistor is all connected with output VO, and the source electrode of each nmos pass transistor is all connected with one end of described resistance, and the other end of described resistance is connected with earth terminal.
Further, described interface circuit is ddr interface.
Further, the resistance value of the described resistance unit resistance of metal-oxide-semiconductor that equals in parallel conducting and the resistance of described resistance with.
Compared with prior art, the present invention passes through in series with a resistor again after several CMOS tube parallel connections, resistance unit is driven to be formed, drive resistance unit to need to be configured to different output according to real work and drive resistance, like this, ensureing to export under the prerequisite driving resistance sizes requirement and resistance linearity, significantly can reduce the chip area shared by it, saving cost.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 a is that the present invention's pull-up in one embodiment exports the module diagram driving resistance;
Fig. 1 b is the present invention's drop-down module diagram exporting driving resistance in one embodiment;
Fig. 2 is pull-up resistor unit of the present invention circuit diagram in one embodiment;
Fig. 3 is pull-up resistor unit of the present invention circuit diagram in another embodiment;
Fig. 4 is pull down resistor unit of the present invention circuit diagram in one embodiment;
Fig. 5 is pull down resistor unit of the present invention circuit diagram in another embodiment.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
Please refer to shown in Fig. 1 a, it is that the present invention's pull-up in one embodiment exports the module diagram driving resistance 110.Please refer to shown in Fig. 1 b, it is the present invention's drop-down module diagram exporting driving resistance 120 in one embodiment.
As shown in Figure 1a, described pull-up exports and drives resistance 110 to be connected between power end VIN and output (or interface end) VO.As shown in Figure 1 b, described drop-down output drives resistance 120 to be connected between output VO and earth terminal GND.
First introduce pull-up and export the circuit structure driving resistance 110.
Described pull-up exports and drives resistance 110 to comprise some pull-up resistor unit (not shown), and the pull-up that can obtain needing by the described pull-up resistor unit of combination configuration exports and drives resistance.
Please refer to shown in Fig. 2, it is pull-up resistor unit of the present invention circuit diagram in one embodiment.This pull-up resistor unit comprises PMOS (the P-channel Metal Oxide Semiconductor) transistor of the first resistance R1 and M the parallel connection be series between power end VIN and output VO, the grid of each PMOS transistor is all connected with corresponding control signal CO1, can the conducting of a control M PMOS transistor or shutoff by the control signal CO1 of correspondence, wherein M be greater than 1 natural number.
In the embodiment shown in Figure 2, a described M PMOS transistor is respectively PMOS transistor MP
1, MP
2..., MP
m-1, MP
m.The source electrode of M PMOS transistor is all connected with power end VIN, and the drain electrode of M PMOS transistor is all connected with one end of described first resistance R1, and the other end of described first resistance R1 is connected with output VO.Suppose that the predetermined resistance of the pull-up resistor unit shown in Fig. 2 is 240 ohm, then the resistance of the first resistance R1 can be less than 240 ohm (being such as 120 ohm), adjusted the quantity of the PMOS transistor of the conducting in pull-up resistor unit by the control signal CO1 of correspondence, make the overall resistance of described pull-up resistor unit be 240 ohm; Then need the described pull-up resistor unit of combination configuration to obtain the pull-up output driving resistance that resistance is 34.4,40 or 48 according to real work.
Please refer to shown in Fig. 3, it is pull-up resistor unit of the present invention circuit diagram in another embodiment.The difference of Fig. 3 and Fig. 2 is, Fig. 3 has exchanged the annexation of the PMOS transistor of the first resistance R1 and M parallel connection in Fig. 2, in Fig. 3, the drain electrode of M PMOS transistor is all connected with output VO, the source electrode of M PMOS transistor is all connected with one end of described first resistance R1, and the other end of described first resistance R1 is connected with power end VIN.
Then, the drop-down circuit structure exporting driving resistance 120 shown in Fig. 1 b is introduced.
Described drop-down output drives resistance 120 to comprise some pull down resistor unit (not shown), and the drop-down output that can obtain needing by the described pull down resistor unit of combination configuration drives resistance.
Please refer to shown in Fig. 4, it is pull down resistor unit of the present invention circuit diagram in one embodiment.Each pull down resistor unit comprises the nmos pass transistor being series at the second resistance R2 between output VO and earth terminal GND and N number of parallel connection, the grid of each NMOS tube is all connected with another corresponding control signal CO2, conducting or the shutoff of N number of second NMOS tube can be controlled by the control signal CO2 of correspondence, wherein, N be greater than 1 natural number.
In the embodiment shown in fig. 4, described N number of nmos pass transistor, is respectively nmos pass transistor MN
1, MN
2..., MN
n-1, MN
n.The source electrode of N number of nmos pass transistor is all connected with earth terminal GND, and the drain electrode of N number of nmos pass transistor is all connected with one end of described second resistance R2, and the other end of described second resistance R2 is connected with output VO.Suppose that the predetermined resistance of the pull down resistor unit shown in Fig. 4 is 240 ohm, then the resistance of the second resistance R2 can be less than 240 ohm (being such as 120 ohm), the quantity of the nmos pass transistor of the conducting in adjustment pull down resistor unit, makes the overall resistance of described pull down resistor unit be 240 ohm; Then need the described pull down resistor unit of combination configuration to obtain the drop-down output driving resistance that resistance is 34.4,40 or 48 ohm according to real work.
Please refer to shown in Fig. 5, it is pull down resistor unit of the present invention circuit diagram in another embodiment.The difference of Fig. 5 and Fig. 4 is, Fig. 5 has exchanged the annexation of the nmos pass transistor of the second resistance R2 in Fig. 4 and N number of parallel connection, in Fig. 5, the drain electrode of N number of nmos pass transistor is all connected with output VO, the source electrode of N number of nmos pass transistor is all connected with one end of described second resistance R2, and the other end of described second resistance R2 is connected with earth terminal GND.
In sum, the present invention passes through in series with a resistor again after several CMOS tube parallel connections, resistance unit is driven to be formed, drive resistance unit to need combination to be configured to different output according to real work and drive resistance, like this, ensureing to export under the prerequisite driving resistance sizes requirement and resistance linearity, significantly series resistance quantity can be reduced, thus reduce the chip area of this output driving shared by resistance, save chip cost.
The output that pull-up output driving resistance 110 in the present invention and drop-down output driving resistance 120 can be used as in the interface circuit on chip drives resistance, and described interface circuit can be ddr interface.
Shown in complex chart 2-5, the invention provides a kind of output and drive resistance, it comprises: several resistance units, each resistance unit comprises the MOS transistor being series at power end and output or a resistance between earth terminal and output and several parallel connections, the grid of each MOS transistor is connected with a corresponding control signal, can be controlled conducting or the shutoff of corresponding MOS transistor by the control signal of correspondence.According to the change of technique, temperature and voltage, the number of the MOS transistor of conducting in each resistance unit is adjusted by described control signal, to make the resistance value of this resistance unit for predetermined resistance, can ensure like this to export and drive the linearity of resistance to meet the requirements, simultaneously owing to only needing in each resistance unit to arrange 1 resistance, very large chip area can be saved like this.
In the present invention, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (10)
1. the output in the interface circuit on chip drives a resistance, and it is characterized in that, it comprises:
Several resistance units, each resistance unit comprises the MOS transistor being series at power end and output or a resistance between earth terminal and output and several parallel connections, the grid of each MOS transistor is connected with a corresponding control signal, conducting or the shutoff of corresponding MOS transistor can be controlled by the control signal of correspondence
The number of the MOS transistor of the conducting in each resistance unit is adjusted to make the resistance value of this resistance unit for predetermined resistance by described control signal.
2. the output in the interface circuit on chip according to claim 1 drives resistance, it is characterized in that,
Described MOS transistor is PMOS transistor,
The PMOS transistor of described resistance and some parallel connections is series between power end and output.
3. the output in the interface circuit on chip according to claim 2 drives resistance, it is characterized in that,
The source electrode of each PMOS transistor is all connected with power end, and the drain electrode of each PMOS transistor is all connected with one end of described resistance, and the other end of described resistance is connected with output.
4. the output in the interface circuit on chip according to claim 2 drives resistance, it is characterized in that,
The drain electrode of each PMOS transistor is all connected with output, and the source electrode of each PMOS transistor is all connected with one end of described resistance, and the other end of described resistance is connected with power end.
5. the output in the interface circuit on chip according to claim 1 drives resistance, and it is characterized in that, described predetermined resistance is 240 ohm.
6. the output in the interface circuit on chip according to claim 1 drives resistance, and it is characterized in that, described MOS transistor is nmos pass transistor,
The nmos pass transistor of described resistance and some parallel connections is series between earth terminal and output.
7. the output in the interface circuit on chip according to claim 6 drives resistance, it is characterized in that,
The source electrode of each nmos pass transistor is all connected with earth terminal, and the drain electrode of each nmos pass transistor is all connected with one end of described resistance, and the other end of described resistance is connected with output VO.
8. the output in the interface circuit on chip according to claim 6 drives resistance, it is characterized in that,
The drain electrode of each nmos pass transistor is all connected with output VO, and the source electrode of each nmos pass transistor is all connected with one end of described resistance, and the other end of described resistance is connected with earth terminal.
9. the output in the interface circuit on chip according to claim 1 drives resistance, and it is characterized in that, described interface circuit is ddr interface.
10. the output in the interface circuit on chip according to claim 1 drives resistance, it is characterized in that,
The resistance of metal-oxide-semiconductor that the resistance value of described resistance unit equals conducting in parallel and the resistance of described resistance with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510241187.9A CN104852725A (en) | 2015-05-13 | 2015-05-13 | Output driving resistor in interface circuit on chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510241187.9A CN104852725A (en) | 2015-05-13 | 2015-05-13 | Output driving resistor in interface circuit on chip |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027012A (en) * | 2016-06-13 | 2016-10-12 | 成绎半导体技术（上海）有限公司 | Pull-down resistor switching circuit |
| CN109709862A (en) * | 2019-01-04 | 2019-05-03 | 华大半导体有限公司 | A kind of programmable variable resistance |
| CN109872746A (en) * | 2017-12-05 | 2019-06-11 | 长鑫存储技术有限公司 | A kind of driving resistance circuit |
| CN112737565A (en) * | 2021-04-02 | 2021-04-30 | 深圳市中科蓝讯科技股份有限公司 | Interface circuit and chip |
| CN113409844A (en) * | 2021-06-15 | 2021-09-17 | 上海威固信息技术股份有限公司 | Nonvolatile configurable pull-up resistor network based on bipolar RRAM |
| CN114756497A (en) * | 2022-04-24 | 2022-07-15 | 湖南国科微电子股份有限公司 | DDR (double data Rate) resistor configuration circuit, connection control method and electronic equipment |
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|---|---|---|---|---|
| US6316301B1 (en) * | 2000-03-08 | 2001-11-13 | Sun Microsystems, Inc. | Method for sizing PMOS pull-up devices |
| US7410293B1 (en) * | 2006-03-27 | 2008-08-12 | Altera Corporation | Techniques for sensing temperature and automatic calibration on integrated circuits |
| US20080297193A1 (en) * | 2006-08-22 | 2008-12-04 | Altera Corporation | Techniques for Providing Calibrated On-Chip Termination Impedance |
| CN104113498A (en) * | 2013-04-17 | 2014-10-22 | 爱思开海力士有限公司 | Equalizer circuit and receiver circuit including the same |
| CN204578512U (en) * | 2015-05-13 | 2015-08-19 | 灿芯半导体(上海)有限公司 | Output in interface circuit on chip drives resistance |
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2015
- 2015-05-13 CN CN201510241187.9A patent/CN104852725A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316301B1 (en) * | 2000-03-08 | 2001-11-13 | Sun Microsystems, Inc. | Method for sizing PMOS pull-up devices |
| US7410293B1 (en) * | 2006-03-27 | 2008-08-12 | Altera Corporation | Techniques for sensing temperature and automatic calibration on integrated circuits |
| US20080297193A1 (en) * | 2006-08-22 | 2008-12-04 | Altera Corporation | Techniques for Providing Calibrated On-Chip Termination Impedance |
| CN104113498A (en) * | 2013-04-17 | 2014-10-22 | 爱思开海力士有限公司 | Equalizer circuit and receiver circuit including the same |
| CN204578512U (en) * | 2015-05-13 | 2015-08-19 | 灿芯半导体(上海)有限公司 | Output in interface circuit on chip drives resistance |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027012A (en) * | 2016-06-13 | 2016-10-12 | 成绎半导体技术（上海）有限公司 | Pull-down resistor switching circuit |
| CN109872746A (en) * | 2017-12-05 | 2019-06-11 | 长鑫存储技术有限公司 | A kind of driving resistance circuit |
| CN109709862A (en) * | 2019-01-04 | 2019-05-03 | 华大半导体有限公司 | A kind of programmable variable resistance |
| CN112737565A (en) * | 2021-04-02 | 2021-04-30 | 深圳市中科蓝讯科技股份有限公司 | Interface circuit and chip |
| CN113409844A (en) * | 2021-06-15 | 2021-09-17 | 上海威固信息技术股份有限公司 | Nonvolatile configurable pull-up resistor network based on bipolar RRAM |
| CN114756497A (en) * | 2022-04-24 | 2022-07-15 | 湖南国科微电子股份有限公司 | DDR (double data Rate) resistor configuration circuit, connection control method and electronic equipment |
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Application publication date: 20150819 |