CN204633747U - Output circuit in interface circuit - Google Patents
Output circuit in interface circuit Download PDFInfo
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- CN204633747U CN204633747U CN201520455893.9U CN201520455893U CN204633747U CN 204633747 U CN204633747 U CN 204633747U CN 201520455893 U CN201520455893 U CN 201520455893U CN 204633747 U CN204633747 U CN 204633747U
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Abstract
The utility model provides the output circuit in a kind of interface circuit, and it comprises: the output driver module comprising multiple output driver elements of or parallel connection, and each output driver element comprises multiple output driving switch; Comprise multiple output control logic modules of multiple output control logic unit, the output of each output control logic unit is connected to the control end that corresponding of exporting the output driver element of driver module exports driving switch; Cooperation control logic module, it includes multiple cooperation control switch, arrange a cooperation control switch between the output of the corresponding output control logic unit in every two output control logic modules, the control end of this cooperation control switch receives its driver module enable signal received by two output control logic modules connected.Rising edge/the trailing edge of the control signal exported by cooperation control logic module alignment output control logic circuit, thus improve the output waveform eye pattern of the final output signal of output circuit.
Description
[technical field]
The utility model relates to Design Technique of Interface field, the output circuit particularly in a kind of interface circuit.
[background technology]
DDR (Double Data Rate, Double Data Rate) technology, namely all data are transmitted at the rising edge of clock and trailing edge, when keeping clock rate constant, data transfer rate can be doubled, therefore, ddr interface is widely used in the interconnection between chip, as ASIC (Application Specific Integrated Circuit, application-specific integrated circuit (ASIC)) and SDRAM (Synchronous Dynamic Random Access Memory, synchronous DRAM) between interface.
Along with the raising of operating rate, existing a lot of ddr interface (such as, DDR2/DDR3/LPDDR2/LPDDR3 interface etc.) not only drive the size of resistance to have requirement to exporting, and drive the linearity of resistance also to have stricter requirement to exporting, it requires that output voltage is remaining within the specific limits (such as, +/-10%) from the change procedure of 0 to supply voltage.
But due to the limitation of CMOS (Complementary Metal Oxide Semiconductor) pipe itself, usually CMOS tube series resistance is needed to make junior unit to improve the linearity of resistance, then the quantity by adjusting junior unit further reaches the size of required resistance, such as, small resistor unit is made by CMOS tube series resistance, junior unit adjusts the large resistance unit of 240 ohm according to the change of technique, temperature and voltage, large resistance unit needs to be configured to 34.4 according to real work, the different outputs such as 40,48 ohm drive resistance.So arrange and will cause junior unit One's name is legion, thus cause chip area shared by CMOS tube and resistance excessive, be unfavorable for that chip is miniaturized.
Each resistance unit needs a prime to drive logic, so that the resistance value of each resistance unit is adjusted to 240 ohm.But the prime of each resistance unit drives the rising edge of the control signal of logic or/and trailing edge cannot align, and affects final output waveform eye pattern.
Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.
[utility model content]
The purpose of this utility model is to provide the output circuit in a kind of interface circuit, can improve the output waveform eye pattern of final output signal.
In order to solve the problem, the utility model provides the output circuit in a kind of interface circuit, it comprises: multiple output driver module be connected between power end and drive output, each output driver module comprises the multiple output driver elements being connected between power end and drive output or parallel connection, each output driver element comprises the multiple output driving switchs be connected between power end and drive output, each output driving switch has the first link being connected to described power end, be connected to the second link and the control end of described drive output, the control end that correspondence in multiple output driver elements of the parallel connection in same output driver module exports driving switch is interconnected at together, the multiple output control logic modules corresponding with described output driver module, each output control logic module comprises multiple output control logic unit, the output of each output control logic unit is connected to the control end that corresponding of exporting in the output driver element of driver module exports driving switch, each output control logic unit in each output control logic module receives corresponding driver module enable signal, corresponding driving switch enable signal and input control signal, the output driver module wherein receiving the output control logic module controls of effective driver module enable signal corresponding is introduced into this output circuit, the output driver module receiving the output control logic module controls of invalid driver module enable signal corresponding is removed out this output circuit, the output driving switch receiving the output control logic unit controls of invalid driving switch enable signal corresponding is removed out this output circuit, the output driving switch receiving the output control logic unit controls of effective driving switch enable signal and effective driver module enable signal corresponding is introduced into this output circuit, cooperation control logic module, it includes multiple cooperation control switch, arrange a cooperation control switch between the output of the corresponding output control logic unit in every two output control logic modules, the control end of this cooperation control switch receives its driver module enable signal received by two output control logic modules connected.
Further, each output driver element comprises multiple output resistance, and each output resistance export driving switch corresponding to is connected between power end and drive output; Or each output driver element comprises an output resistance, each exports driving switch and is connected in parallel, and the output driving switch of described output resistance and each parallel connection is connected between power end and drive output.
Further, described output driving switch is PMOS transistor, the source electrode of PMOS transistor is the first link of described output driving switch, the drain electrode of PMOS transistor is the second link of described output driving switch, the grid of PMOS transistor is the control end of described output driving switch, and described power end is input supply terminal; Or described output driving switch is nmos pass transistor, the source electrode of nmos pass transistor is the first link of described output driving switch, the drain electrode of nmos pass transistor is the second link of described output driving switch, the grid of nmos pass transistor is the control end of described output driving switch, and described power end is earth terminal.
Further, each output control logic unit comprises the first gate and the second gate, the first input end of this first gate receives described input control signal, second input receives corresponding driving switch enable signal, the output of the first gate is connected with the first input end of the second gate, second input of the second gate receives corresponding driver module enable signal, the driver module enable signal that each output control logic unit in same output control logic module receives is same signal, the driving switch enable signal that each output control logic unit in same output control logic module receives is unlike signal, the driving switch enable signal that corresponding output control logic unit in different output control logic module receives is same signal.
Further, each cooperation control switch comprises the first cooperation control switch element and the second cooperation control switch element of series connection, and the control end of each cooperation control switch element receives the driver module enable signal received by two output control logic modules that this cooperation control switch connects respectively.
Further, when the driver module enable signal received by two output control logic modules that described cooperation control switch connects is all effective, described cooperation control switch conduction is to be communicated with the output of two output control logic unit of this cooperation control switch connection, otherwise, described cooperation control switch cut-off.
Further, output circuit in interface circuit also includes coordination logic module in multiple pieces that are connected with the output of corresponding output control logic module, in each piece, Coordination module comprises vernier control switch, in corresponding output control logic module every two output control logic unit output between a vernier control switch is set, the control end of this vernier control switch receives this driving switch enable signal received by two output control logic unit.
Further, each vernier control switch comprises the first inching switch unit and the second inching switch unit of series connection, and the control end of each inching switch unit receives the driving switch enable signal received by two output control logic unit that this inching switch connects respectively.
Further, when the driving switch enable signal received by two output control logic unit that described vernier control switch connects is all effective, described vernier control switch conduction is to be communicated with the output of two output control logic unit of this vernier control switch connection, otherwise, described vernier control switch cut-off.
Compared with prior art, the rising edge of the control signal that the utility model is exported by the described output control logic circuit of alignment and/trailing edge, thus improve the output waveform eye pattern of the final output signal of this output circuit.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the part of module schematic diagram of the utility model output circuit in one embodiment;
Fig. 2 is the output driving circuit module diagram in one embodiment in Fig. 1;
Fig. 3 is the output control logic circuit module diagram in one embodiment in Fig. 1;
Fig. 4 is the output driver element circuit diagram in a first embodiment in the utility model;
Fig. 5 is the output driver element circuit diagram in a second embodiment in the utility model;
Fig. 6 is the output driver element circuit diagram in the third embodiment in the utility model;
Fig. 7 a to Fig. 7 c is each output control logic unit circuit diagram in one embodiment in the utility model;
The waveform schematic diagram of each control signal that Fig. 8 exports for each output control logic module shown in Fig. 3;
Fig. 9 is cooperation control logic module of the present utility model structural representation in one embodiment;
Figure 10 is the cooperation control switch structural representation in one embodiment in Fig. 9;
Figure 11 is coordination logic module structural representation in one embodiment in the utility model block;
Figure 12 is the vernier control switch structural representation in one embodiment in Figure 11.
[embodiment]
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in further detail the utility model below in conjunction with the drawings and specific embodiments.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the utility model.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
Please refer to shown in Fig. 1, it is the part of module schematic diagram of the utility model output circuit 100 in one embodiment.Described output circuit 100 comprises output driving circuit 110 and output control logic circuit 120.
Described output driver module 110 is connected between input supply terminal VIN and drive output VO.Described output control logic circuit 120 receives the input control signal DIN of outside input, the driver module enable signal OEA-OEC of outside input, the driving switch enable signal OE1-OEn of outside input.
Those of ordinary skill in affiliated field is it is well known that an output circuit generally includes the pull-up control section circuit be connected between input supply terminal VIN and drive output VO and the drop-down control section circuit be connected between drive output VO and earth terminal GND.When input control signal DIN is high level, by the path between this pull-up control section circuit turn-on input supply terminal VIN and drive output VO to draw high the level of drive output VO, the path now between output VO and earth terminal GND normally ends; When input control signal DIN is low level, by the path between this drop-down control section circuit turn-on output VO and earth terminal GND to drag down the level of drive output VO, the path now between input supply terminal VIN and drive output VO normally ends.Because pull-up control section circuit is substantially identical with the principle of drop-down control section circuit, therefore conveniently, only introduce pull-up control section circuit in detail in this article, as the output driving circuit 110 in Fig. 1 and output control logic circuit 120 just belong to pull-up control section circuit.Be easy to it is envisioned that, described drop-down control section circuit can include and be connected to drop-down output driving circuit between drive output VO and earth terminal GND and drop-down output control logic circuit, their adopt and output driving circuit 110 and the similar structure of output control logic circuit 120, now output driving circuit 110 also can be called as pull-up output driving circuit 110, and output control logic circuit 120 also can be called as drop-down output control logic circuit 120.Power end herein can be united and be referred to input supply terminal VIN and earth terminal GND.
As shown in Figure 2, it illustrates output driving circuit 110 module diagram in one embodiment in the utility model.As shown in Figure 2, described output driving circuit 110 comprises the first output driver module 111, the second output driver module 112, the 3rd output driver module 113 that are connected between input supply terminal VIN and drive output VO.Illustrate in Fig. 2 that three export driver modules, but in other embodiments, also can configure 1,2 or more as required and export driver module.
Each output driver module comprises the multiple output driver elements being connected between input supply terminal VIN and drive output VO or parallel connection.The overall resistance of each output driver element can be adjusted to predetermined resistance, such as 240 ohm.Like this, by the parallel connection of multiple output driver element can be obtained 34.4,40,5 resistance values are such as that can to obtain resistance value be that the output of 48 ohm drives resistance for the output driver element parallel connection of 240 ohm by the different resistance values such as 48 ohm.In a preferred embodiment, in order to the resistance value of more combinations can be obtained, can design as follows, first exports driver module 111 includes an output driver element, second output driver module 112 includes two output driver elements in parallel, and the 3rd exports driver module 113 includes 4 output driver elements in parallel.If the resistance of each output driver element is adjusted to 240 ohm, the Selection effect that 1,2,3,4,5,6,7 exports driver element parallel connection can be obtained like this.
Fig. 4 is output driver element 400 circuit diagram in a first embodiment in the utility model.As shown in Figure 4, described output driver element 400 comprises the multiple PMOS transistor MP1 to MPn be connected between input supply terminal VIN and drive output VO and the resistance R1-Rn connected with each PMOS transistor respectively, wherein PMOS transistor MP1 and resistance R1 is connected between input supply terminal VIN and drive output VO, PMOS transistor MP2 and resistance R2 is connected between input supply terminal VIN and drive output VO,, PMOS transistor MPn and resistance Rn is connected between input supply terminal VIN and drive output VO.For each PMOS transistor, its source electrode meets input supply terminal VIN, and its drain electrode connects one end of corresponding resistance, another termination drive output VO of corresponding resistance.
By controlling the signal of the grid of PMOS transistor, thoroughly certain PMOS transistor of cut-off can change the resistance value of whole output driver element 400.According to the change of technique, temperature and voltage, being adjusted by the driving switch enable signal OE1-OEn adjusting outside input can the quantity of PMOS transistor of conducting, and then the resistance value of whole output driver element 400 can be made to be predetermined resistance.
Fig. 5 is the output driver element circuit diagram in a second embodiment in the utility model.With in Fig. 4 unlike, each PMOS transistor MP1 to MPn is connected in parallel, and PMOS transistor MP1 to a MPn and resistance R11 of these parallel connections is connected between input supply terminal VIN and drive output VO.The advantage done like this is: do not need each PMOS transistor to connect a resistance, whole output driver element only needs a resistance R11 being less than predetermined resistance, can the quantity of PMOS transistor of conducting the resistance value of whole output driver element can be made to be predetermined resistance by adjustment, can significantly reduce series resistance quantity like this, thus reduce the chip area of this output driving shared by resistance, save chip cost.
Fig. 6 is the output driver element circuit diagram in the third embodiment in the utility model.With in Fig. 5 unlike: each PMOS transistor MP1 to MPn in parallel and the series position of resistance R21 there occurs exchange, and one end of resistance R21 is connected with input supply terminal VIN, and the drain electrode of PMOS transistor MP1 to MPn meets described drive output VO.
For the drop-down control section circuit of output circuit, also the structure of the output driver element in Fig. 4-Fig. 6 can be adopted, now drop-down output driver element also can be connected between drive output VO and earth terminal, PMOS transistor in Fig. 4, Fig. 5 and Fig. 6 all needs to change to nmos pass transistor, the source electrode of nmos pass transistor is connected with earth terminal, the drain electrode of nmos pass transistor is connected with drive output VO, and its concrete principle is all same as above.
In view of the embodiment that Fig. 4, Fig. 5 and Fig. 6 provide, and nmos pass transistor is for exporting the embodiment in driver element, can find out, output driver element in the utility model comprises the multiple output driving switchs be connected between power end and drive output, each output driving switch has the first link being connected to described power end, is connected to the second link and the control end of described drive output.PMOS transistor and nmos pass transistor are exactly described output driving switch, the source electrode of nmos pass transistor and PMOS transistor is the first link of described output driving switch, the drain electrode of nmos pass transistor and PMOS transistor is the second link of described output driving switch, and the grid of nmos pass transistor and PMOS transistor is the control end of described output driving switch.
In the embodiment as shown in fig .4, each output driver element comprises multiple output resistance R1-Rn, and each output resistance export driving switch corresponding to is connected between power end and drive output.In embodiment as shown in Figure 5 and Figure 6, each output driver element comprises output resistance R11 or R21, each exports driving switch MP1-MPn and is connected in parallel, and the output driving switch of described output resistance and each parallel connection is connected between power end and drive output VO.
As described above, the output driver element of multiple parallel connection is included in some output driver modules.Incorporated by reference to referring to shown in Fig. 4,5,6, the control end of the PMOS transistor MP1 in multiple output driver elements of the parallel connection in same output driver module is interconnected at together, the control end of the PMOS transistor MP2 in multiple output driver elements of the parallel connection in same output driver module is interconnected at together,, the control end of the PMOS transistor MPn in multiple output driver elements of the parallel connection in same output driver module is interconnected at together.
Fig. 3 is output control logic circuit 120 module diagram in one embodiment in Fig. 1.Described output control logic circuit 120 includes the first output control logic module 121, second output control logic module 122 and the 3rd output control logic module 123.Illustrate in Fig. 3 that three export driver module, but in other embodiments, also can configure 1,2 or more as required and export driver module, the quantity wherein exporting driver module has the quantity exporting driver module to determine, corresponding one of each output driver module exports driver module.As shown in Figure 3, the output terminals A 1-An of the first output control logic module 121 exports n drived control switch of the output driver element in driver module 111 respectively control end with first is connected, the output terminals A 1-An of the second output control logic module 122 exports n drived control switch of the output driver element in driver module 112 respectively control end with second is connected, and the output terminals A 1-An of the 3rd output control logic module 121 exports n drived control switch of the output driver element in driver module 113 respectively control end with first is connected.
Each output control logic module comprises multiple output control logic unit.Fig. 7 a is the first output control logic unit 121 circuit diagram in one embodiment in the utility model, Fig. 7 b is the second output control logic unit 122 circuit diagram in one embodiment in the utility model, and Fig. 7 c is the 3rd output control logic unit 122 circuit diagram in one embodiment in the utility model.
The output of each output control logic unit is connected to the control end that corresponding of exporting in the output driver element of driver module exports driving switch, and each output control logic unit in each output control logic module receives corresponding driver module enable signal, corresponding driving switch enable signal and input control signal DIN.With reference to shown in figure 7a-7c and Fig. 4-6, the output terminals A 1-An of each output control logic unit of the first output control logic module 121 is connected to the grid of the PMOS transistor PM1-PMn in the first output driver module 111 respectively, the output B1-Bn of each output control logic unit of the second output control logic module 122 is connected to the grid of the PMOS transistor PM1-PMn in the second output driver module 112 respectively, the output B1-Bn of each output control logic unit of the 3rd output control logic module 123 is connected to the grid that the 3rd exports the PMOS transistor PM1-PMn in driver module 113 respectively.Each output control logic unit in first output control logic module 121 receives corresponding driver module enable signal OEA, corresponding driving switch enable signal OE1-OEn and input control signal DIN, each output control logic unit in second output control logic module 122 receives corresponding driver module enable signal OEB, corresponding driving switch enable signal OE1-OEn and input control signal DIN, each output control logic unit in 3rd output control logic module 123 receives corresponding driver module enable signal OEC, corresponding driving switch enable signal OE1-OEn and input control signal DIN.
The output driver module receiving the output control logic module controls of effective driver module enable signal corresponding is introduced into this output circuit, the output driver module receiving the output control logic module controls of invalid driver module enable signal corresponding is removed out this output circuit, the output driving switch receiving the output control logic unit controls of effective driving switch enable signal corresponding is introduced into this output circuit, and the output driving switch receiving the output control logic unit controls of invalid driving switch enable signal corresponding is removed out this output circuit.With reference to shown in figure 7a and Fig. 4-6, when driver module enable signal OEA is effective, now described first each PMOS transistor exporting driver module 111 is controlled by driving switch enable signal and input control signal DIN, first output control logic module 121 controls the first output driver module 111 and is introduced into this output circuit 100, when driver module enable signal OEA is invalid, now all PMOS transistor of described first output driver module 111 are all ended, first output control logic module 121 controls the first output driver module 111 and is removed out this output circuit 100.If when driving switch enable signal OE1 is invalid, so the output terminals A 1 of the first output control logic module 121 can make PMOS transistor MP1 end, thus it is removed from output circuit 100, if driver module enable signal OEA effectively and driving switch enable signal OE1 is effective time, the output terminals A 1 of the first output control logic module 121 is controlled by input control signal DIN.
As shown in Fig. 7 a-7c, each output control logic unit comprises the first gate and the second gate, the first input end of this first gate receives described input control signal DIN, second input receives corresponding driving switch enable signal OE1-OEn, the output of the first gate is connected with the first input end of the second gate, and the second input of the second gate receives corresponding driver module enable signal OEA-OECA.The driver module enable signal that each output control logic unit in same output control logic module receives is same signal, the driver module enable signal that each output control logic unit of such as the first output control logic module receives is all OEA, the driving switch enable signal that each output control logic unit in same output control logic module receives is unlike signal, such as OE1-OEn, the driving switch enable signal that the corresponding output control logic unit in different output control logic module receives is same signal.
In one embodiment, the first gate and the second gate are all and door, for each output control logic unit, if OE1 effectively and driver module enable signal OEA, OEB or OEC is effective time, its output signal is determined by input control signal DIN.
Because different output driver modules includes the output driver element of varying number, the rising edge between the control signal that each output control logic unit exports and trailing edge are not complete matchings.As shown in Figure 8, its each control signal A1-An exported for each output control logic module shown in Fig. 7 a-7c, the waveform schematic diagram of C1-Cn, wherein illustrate only control signal A1, A2, C1 and C2, the X place that the rising edge of each control signal cannot align, affects the final output waveform eye pattern of described output circuit 100.
In a preferred embodiment, as shown in Figure 9, the output control logic circuit 120 in the utility model also includes cooperation control logic module 900, and it includes multiple cooperation control switch 910.Arrange a cooperation control switch 910 between the output of the corresponding output control logic unit in every two output control logic modules, the control end of this cooperation control switch 910 receives its driver module enable signal received by two output control logic modules connected.
In fig .9, equal 5 be introduced for n, namely each output control logic module includes 5 output control logic unit.Between the output B1 of the output terminals A 1 of the output control logic unit of the first output control logic module 121 and the output control logic unit of the second output control logic module 122, a cooperation control switch 910 is set, between the output B5 that the output terminals A 5 of the output control logic unit of a cooperation control switch 910, first output control logic module 121 and the output control logic unit of the second output control logic module 122 be set between the output B2 of the output terminals A 2 of the output control logic unit of the first output control logic module 121 and the output control logic unit of the second output control logic module 122, a cooperation control switch 910 is set.Same, between the output C1-C5 that the output B1-B5 of the output control logic unit of a cooperation control switch 910, second output control logic module 122 and the output control logic unit of the 3rd output control logic module 123 be set between the output C1-C5 of the output terminals A 1-A5 of the output control logic unit of the first output control logic module 121 and the output control logic unit of the 3rd output control logic module 123 respectively, a cooperation control switch 910 is set respectively.As shown in Figure 9, the control end of the cooperation control switch 910 between A1 and B1 receives the first output control logic module 121 and driver module enable signal OEA and OEB received by the second output control logic module 122.The control end of the cooperation control switch 910 between A1 and C1 receives the first output control logic module 121 and driver module enable signal OEA and OEC received by the 3rd output control logic module 123.In other words, the control end of each cooperation control switch 910 receives its driver module enable signal received by two output control logic modules connected.
Figure 10 is cooperation control switch 910 structural representation in one embodiment in Fig. 9.Each cooperation control switch 910 comprises the first cooperation control switch element 911 and the second cooperation control switch element 912 of series connection, and the control end of each cooperation control switch element receives the driver module enable signal received by two output control logic modules that this cooperation control switch connects respectively.As shown in Figure 10, first cooperation control switch element 911 receives the driver module enable signal OEA received by the first output control logic module 121, second cooperation control switch element 912 receives the driver module enable signal OEC received by the 3rd output control logic module 123, and the cooperation control switch 910 shown in Figure 10 is between output terminals A 1-A5 and output C1-C5.When operating, when the driver module enable signal received by two output control logic modules that described cooperation control switch 910 connects is all effective, signal on two outputs, to be communicated with the output of two output control logic unit that this cooperation control switch 910 is connected, has compulsoryly like this been carried out average alignment by described cooperation control switch 910 just conducting (i.e. the second cooperation control switch element 912 and first cooperation control switch element 911 all conductings); Otherwise described cooperation control switch 910 ends the connection cut off between the output of two output control logic unit that this cooperation control switch 910 connects.
Like this, linked together by the compulsory output by the corresponding output control logic unit in each output control logic module of cooperation control switch 910, the control signal alignment they exported by force, can improve final waveform eye diagram quality like this.
In a preferred embodiment, described output control logic circuit 120 also includes the multiple cooperation control logic modules 800 be connected with the output of corresponding output control logic module.Figure 11 is coordination logic module 800 structural representation in one embodiment in the block that is connected with the output of the first output control logic module 121 of the utility model.
As shown in figure 11, in each piece, Coordination module 800 comprises multiple vernier control switch 810, in corresponding output control logic module every two output control logic unit output between a vernier control switch 810 is set, the control end of this vernier control switch receives this driving switch enable signal received by two output control logic unit.Such as be provided with vernier control switch 810 between output terminals A 1 and A2, between output terminals A 1 and A4, be provided with vernier control switch 810 etc.
As shown in figure 12, each vernier control switch 810 comprises the first inching switch unit 811 and the second inching switch unit 812 of series connection, and the control end of each inching switch unit receives the driving switch enable signal received by two output control logic unit that this inching switch connects respectively.
As shown in figure 12, the first inching switch unit 811 receives driving switch enable signal OE1, and the second inching switch unit 812 receives driving switch enable signal OE2, and the vernier control switch 810 shown in Figure 12 is between output terminals A 1-A2.When operating, when the driving switch enable signal OE1-OE5 received by two output control logic unit that described vernier control switch 810 connects is effective, signal on two outputs, to be communicated with the output of two output control logic unit that this vernier control switch 810 is connected, has compulsoryly like this been carried out average alignment by described vernier control switch 810 just conducting (i.e. the first vernier control switch element 811 and second vernier control switch element 812 all conductings); Otherwise described vernier control switch 810 ends the connection cut off between the output of two output control logic unit that this vernier control switch 810 connects.
It is understood that, in Figure 12, the first inching switch unit 811 and the second inching switch unit 812 are all transmission gates, each transmission gate comprises PMOS transistor in parallel and nmos pass transistor, the grid of nmos pass transistor connects described driving switch enable signal OE1 or OE2, and the grid of PMOS transistor connects enable inversion signal OE1b or OE2b of described driving switch.In Figure 10, the first coordination switch element 911 and the second coordination switch element 912 are all transmission gates, each transmission gate comprises PMOS transistor in parallel and nmos pass transistor, the grid of nmos pass transistor connects described driver module enable signal OEA or OEC, and the grid of PMOS transistor connects inversion signal OEAb or OECb of described driver module enable signal.
In the utility model, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection, such as through a logical circuit, such as buffer or inverter, for another example through a resistance etc.
It is pointed out that the scope be familiar with person skilled in art and any change that embodiment of the present utility model is done all do not departed to claims of the present utility model.Correspondingly, the scope of claim of the present utility model is also not limited only to previous embodiment.
Claims (9)
1. the output circuit in interface circuit, is characterized in that, it comprises:
Multiple output driver module be connected between power end and drive output, each output driver module comprises the multiple output driver elements being connected between power end and drive output or parallel connection, each output driver element comprises the multiple output driving switchs be connected between power end and drive output, each output driving switch has the first link being connected to described power end, be connected to the second link and the control end of described drive output, the control end that correspondence in multiple output driver elements of the parallel connection in same output driver module exports driving switch is interconnected at together,
The multiple output control logic modules corresponding with described output driver module, each output control logic module comprises multiple output control logic unit, the output of each output control logic unit is connected to the control end that corresponding of exporting in the output driver element of driver module exports driving switch, each output control logic unit in each output control logic module receives corresponding driver module enable signal, corresponding driving switch enable signal and input control signal, the output driver module wherein receiving the output control logic module controls of effective driver module enable signal corresponding is introduced into this output circuit, the output driver module receiving the output control logic module controls of invalid driver module enable signal corresponding is removed out this output circuit, the output driving switch receiving the output control logic unit controls of invalid driving switch enable signal corresponding is removed out this output circuit, the output driving switch receiving the output control logic unit controls of effective driving switch enable signal and effective driver module enable signal corresponding is introduced into this output circuit,
Cooperation control logic module, it includes multiple cooperation control switch, arrange a cooperation control switch between the output of the corresponding output control logic unit in every two output control logic modules, the control end of this cooperation control switch receives its driver module enable signal received by two output control logic modules connected.
2. the output circuit in interface circuit according to claim 1, is characterized in that, each output driver element comprises multiple output resistance, and each output resistance export driving switch corresponding to is connected between power end and drive output; Or
Each output driver element comprises an output resistance, and each exports driving switch and is connected in parallel, and the output driving switch of described output resistance and each parallel connection is connected between power end and drive output.
3. the output circuit in interface circuit according to claim 1, is characterized in that,
Described output driving switch is PMOS transistor, the source electrode of PMOS transistor is the first link of described output driving switch, the drain electrode of PMOS transistor is the second link of described output driving switch, the grid of PMOS transistor is the control end of described output driving switch, and described power end is input supply terminal; Or
Described output driving switch is nmos pass transistor, the source electrode of nmos pass transistor is the first link of described output driving switch, the drain electrode of nmos pass transistor is the second link of described output driving switch, the grid of nmos pass transistor is the control end of described output driving switch, and described power end is earth terminal.
4. the output circuit in interface circuit according to claim 1, it is characterized in that, each output control logic unit comprises the first gate and the second gate, the first input end of this first gate receives described input control signal, second input receives corresponding driving switch enable signal, the output of the first gate is connected with the first input end of the second gate, second input of the second gate receives corresponding driver module enable signal, the driver module enable signal that each output control logic unit in same output control logic module receives is same signal, the driving switch enable signal that each output control logic unit in same output control logic module receives is unlike signal, the driving switch enable signal that corresponding output control logic unit in different output control logic module receives is same signal.
5. the output circuit in interface circuit according to claim 1, it is characterized in that, each cooperation control switch comprises the first cooperation control switch element and the second cooperation control switch element of series connection, and the control end of each cooperation control switch element receives the driver module enable signal received by two output control logic modules that this cooperation control switch connects respectively.
6. the output circuit in interface circuit according to claim 5, it is characterized in that, when the driver module enable signal received by two output control logic modules that described cooperation control switch connects is all effective, described cooperation control switch conduction is to be communicated with the output of two output control logic unit of this cooperation control switch connection, otherwise, described cooperation control switch cut-off.
7. the output circuit in interface circuit according to claim 1, is characterized in that, it also includes coordination logic module in multiple pieces that are connected with the output of corresponding output control logic module,
In each piece, Coordination module comprises vernier control switch, in corresponding output control logic module every two output control logic unit output between a vernier control switch is set, the control end of this vernier control switch receives this driving switch enable signal received by two output control logic unit.
8. the output circuit in interface circuit according to claim 7, it is characterized in that, each vernier control switch comprises the first inching switch unit and the second inching switch unit of series connection, and the control end of each inching switch unit receives the driving switch enable signal received by two output control logic unit that this inching switch connects respectively.
9. the output circuit in interface circuit according to claim 8, it is characterized in that, when the driving switch enable signal received by two output control logic unit that described vernier control switch connects is all effective, described vernier control switch conduction is to be communicated with the output of two output control logic unit of this vernier control switch connection, otherwise, described vernier control switch cut-off.
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| CN201520455893.9U CN204633747U (en) | 2015-06-29 | 2015-06-29 | Output circuit in interface circuit |
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| CN201520455893.9U CN204633747U (en) | 2015-06-29 | 2015-06-29 | Output circuit in interface circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935326A (en) * | 2015-06-29 | 2015-09-23 | 灿芯半导体(上海)有限公司 | Output circuit in interface circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935326A (en) * | 2015-06-29 | 2015-09-23 | 灿芯半导体(上海)有限公司 | Output circuit in interface circuit |
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