CN207200682U - Bidirectional interface circuit - Google Patents
Bidirectional interface circuit Download PDFInfo
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- CN207200682U CN207200682U CN201720970658.4U CN201720970658U CN207200682U CN 207200682 U CN207200682 U CN 207200682U CN 201720970658 U CN201720970658 U CN 201720970658U CN 207200682 U CN207200682 U CN 207200682U
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Abstract
The utility model discloses a kind of bidirectional interface circuit, including the first transmission circuit, the second transmission circuit, the first drive circuit and the 3rd transmission circuit；When enable signal is the first level state, output secondary signal after the first signal delay of first transmission circuit to reception is anti-phase, the 3rd signal of output after first signal delay of second transmission circuit to reception is anti-phase, first drive circuit, the secondary signal and the 3rd signal are received, and the 4th signal is exported in bidirectional port based on the secondary signal and the 3rd signal；When enable signal is second electrical level state, the 3rd transmission circuit receives the 5th signal from the bidirectional port, and is based on the signal of the 5th signal output the 6th.
Description
Technical field
It the utility model is related to the data transmission technology in integrated circuit fields, more particularly to a kind of bidirectional interface circuit.
Background technology
Half-duplex transmission refers to receive shares a transmission channel with sending, but synchronization can only send or can only receive
The transmission means of data.On the other hand, full duplex transmission refers to while a kind of data transfer mode in the two directions occurs.Example
Such as：Intercom is exactly a kind of half-duplex apparatus, only allows a side to talk within the same time.On the contrary, telephone set is then a kind of complete
Duplex apparatus, its both call sides can engage in the dialogue simultaneously.
Half-duplex data transmission is carried out usually using bidirectional interface circuit in the design of chip, by input interface and defeated
Outgoing interface is time-multiplexed, and can efficiently reduce the quantity and printed circuit board (Printed of chip input/output port
Circuit Board, PCB) wiring complexity.
But common bidirectional interface circuit exist two it is big main the problem of, first, when circuit is exported, carry out
Leakage current of the transistor of output when state is overturn is very big；In addition, when the voltage of input/output port is higher than supply voltage,
Bidirectional interface circuit overvoltage and electric leakage can be caused.
Utility model content
In view of this, the utility model embodiment it is expected to provide a kind of bidirectional interface circuit, can be substantially reduced two-way connect
Mouthful circuit solves the electricity caused by the voltage of outside port input is higher than supply voltage in leakage current caused by state upset
Pass by pressure and electrical leakage problems.
To reach above-mentioned purpose, what the technical scheme of the utility model embodiment was realized in：
The utility model embodiment provides a kind of bidirectional interface circuit, including：First transmission circuit, the second transmission electricity
Road, the first drive circuit and the 3rd transmission circuit；
First transmission circuit, for when enable signal is the first level state, the first signal is received, to described the
The delay of one signal is anti-phase to be obtained secondary signal and exports；
Second transmission circuit, for when the enable signal is first level state, receiving described first
Signal, it is anti-phase to first signal delay to obtain the 3rd signal and export；
First drive circuit, it is connected with first transmission circuit and second transmission circuit, for described
When enable signal is first level state, the secondary signal is received from first transmission circuit, is passed from described second
Transmission of electricity road receives the 3rd signal；And the secondary signal and the 3rd signal are based on, in the bidirectional interface circuit
Bidirectional port exports the 4th signal；Wherein, when the secondary signal is converted to second electrical level state by first level state,
Lag behind the 3rd signal and the second electrical level state is converted to by first level state；3rd signal is by described
When second electrical level State Transferring is the first level state, it is institute to lag behind the secondary signal by the second electrical level State Transferring
State the first level state；
3rd transmission circuit, for when the enable signal is the second electrical level state, from the bidirectional end
Mouth receives the 5th signal, and based on the 5th signal output and the signal of the 5th signal level state identical the 6th.
In above-mentioned technical proposal, first transmission circuit, including：First phase inverter and the second phase inverter；Wherein,
First phase inverter, there is the first resistor being connected with ground terminal；
Second phase inverter, there is the second resistance being connected with power end；
First phase inverter and the second phase inverter, for being changed into first signal by the second electrical level state
During first level state, line delay is entered to first signal.
In above-mentioned technical proposal, first transmission circuit, in addition to：First protection sub-circuit；
The first protection sub-circuit, for when the enable signal is the second electrical level state, to described first
Transmission circuit carries out overvoltage protection；When the enable signal is first level state, by the secondary signal transmit to
First drive circuit.
In above-mentioned technical proposal, second transmission circuit, including：3rd phase inverter and the 4th phase inverter；Wherein,
3rd phase inverter, there is the 3rd resistor being connected with power supply；
4th phase inverter, there is the 4th resistance being connected with ground terminal；
3rd phase inverter and the 4th phase inverter, for being by first level state transition in first signal
During the second electrical level state, line delay is entered to first signal.
In above-mentioned technical proposal, first drive circuit, including：
Second drive sub-circuits and the second protection sub-circuit；Wherein,
Second drive sub-circuits, for when the enable signal is first level state, reception it is described
Secondary signal, when the secondary signal is the second electrical level state, export the 4th letter of first level state
Number.
The second protection sub-circuit, for when the enable signal is the second electrical level state, based on described the
Five signals carry out overvoltage protection to second drive sub-circuits.
In above-mentioned technical proposal, second drive sub-circuits, including：
First end, the second end and the 3rd end；Wherein,
The first end, for receiving the secondary signal of the first transmission circuit output；
Second end, for connecting the bidirectional port, export the 4th signal；
3rd end, for connecting the second protection sub-circuit.
In above-mentioned technical proposal, first drive circuit, in addition to：
3rd drive sub-circuits, for when the enable signal is first level state, the described 3rd of reception the
Signal；When the 3rd signal is first level state, the 4th signal of the second electrical level state is exported.
In above-mentioned technical proposal, the 3rd drive sub-circuits, including：The first transistor and second transistor；
The first transistor, for when the enable signal is the first level state, receiving the 3rd signal；When
When 3rd signal is the second electrical level state, the second transistor is set to export described the of the second electrical level state
Four signals；
The second transistor, connected with the first transistor, for being second electrical level state when the enable signal
When, the 5th signal is received, and partial pressure protection is carried out to the first transistor based on the 5th signal.
In above-mentioned technical proposal, first drive circuit, in addition to：
Third transistor, there is source electrode and drain electrode；
The source electrode is connected with the first end of first drive circuit；
The drain electrode is connected with the bidirectional port.
In above-mentioned technical proposal, the 3rd transmission circuit, including：3rd protection sub-circuit；
The 3rd protection sub-circuit, including input and output end, the input are connected with the bidirectional port, institute
The gate circuit that output end is stated with the 3rd transmission circuit is connected, for receiving the 5th signal from the bidirectional port, and
When the 5th signal is more than preset value, in output signal of the output end output less than the preset value.
The bidirectional interface circuit that the utility model embodiment is provided, pass through the first transmission circuit and the second transmission circuit pair
First signal enters line delay so that the secondary signal obtained based on first signal and the level state upset of the 3rd signal are existed
There is some difference in sequential, and secondary signal and the 3rd signal will not carry out level state conversion simultaneously so that receives described the
First drive circuit of binary signal and the 3rd signal will not form the leakage path to ground by power supply, solve prior art
The problem of leakage current be present when level state is overturn in middle bidirectional interface circuit.When enable signal is the first level state, institute
The first drive circuit is stated in bidirectional port output and the signal of the first signal level state identical the 4th；It is in enable signal
During second electrical level state, the 3rd transmission circuit is based on the 5th signal received in the bidirectional port, output and described the
The signal of five signal level state identical the 6th；Bidirectional port both can also be used as signal as the input port of signal
Output port, realize the half-duplex transmission of data, reduce the leakage current in bidirectional interface circuit, improve bidirectional interface electricity
The robustness on road.
Brief description of the drawings
Fig. 1 is the basic composition structural representation of the utility model embodiment bidirectional interface circuit；
Fig. 2 is the concrete composition electrical block diagram of the utility model embodiment bidirectional interface circuit.
Embodiment
In the utility model embodiment, bidirectional interface circuit includes the first transmission circuit, the second transmission circuit, the first driving
Circuit and the 3rd transmission circuit；When enable signal is the first level state, first transmission circuit and second transmission
Circuit enters line delay and anti-phase to the first signal of reception, exports the secondary signal obtained based on first signal and the 3rd letter
Number, the secondary signal lags behind the 3rd signal by first when being second electrical level state by the first level state transition
Level state transition is second electrical level state, the 3rd signal when being changed into the first level state by second electrical level state,
Lag behind the secondary signal and the first level state is changed into by second electrical level state.
First drive circuit receives the secondary signal and the 3rd signal, and is based on the secondary signal and institute
State the 3rd signal and export the 4th signal, the level state of the 4th signal and the level shape of first signal in bidirectional port
State is identical.
Now, the 3rd transmission circuit is off state, will not shadow in the 5th signal that the bidirectional port receives
Ring the 6th signal of the 3rd transmission circuit output.Here, the 6th signal is in second electrical level state.
When the enable signal is second electrical level state, the 3rd transmission circuit receives the 5th in the bidirectional port
Signal, and it is based on the signal of the 5th signal output the 6th.The level state of 6th signal and the electricity of the 5th signal
Level state is identical, and the now output of first drive circuit is in high-impedance state, the 5th signal that the bidirectional port receives
There is provided by external circuit.
Wherein, the bidirectional port, when the enable signal is the first level state, as the bidirectional interface circuit
Output port；When the enable signal is second electrical level state, the input port as the bidirectional interface circuit.
The level state, including the first level state and second electrical level state；First level state, it is high level
State, magnitude of voltage corresponding to the first level state can be arranged to 2.5V；The second electrical level state, it is low level state,
Magnitude of voltage corresponding to second electrical level state can be arranged to 0V；It should be noted that first level state and described
Magnitude of voltage corresponding to two level states can be set according to practical operation demand, merely just provide a specific embodiment
Operand value.
The high-impedance state, to be different from the output state of high level state and low level state, equivalent to cut-off state.
The enable signal, the first signal, secondary signal, the 3rd signal, the 4th signal, the 5th signal and the 6th signal are equal
With the first level state and second electrical level state.
The characteristics of in order to more fully hereinafter understand the utility model and technology contents, below in conjunction with the accompanying drawings to this practicality
New realization is described in detail.
In the utility model embodiment, the basic composition structure of bidirectional interface circuit as shown in figure 1, including：First transmission
Circuit 101, the second transmission circuit 102, the first drive circuit 103 and the 3rd transmission circuit 104；Wherein,
First transmission circuit 101, for when enable signal is the first level state, the first signal being received, to institute
The delay of the first signal is stated anti-phase to obtain secondary signal and export.
First transmission circuit 101 to first signal delay it is anti-phase obtain secondary signal and export can be：When
When first signal is changed into the first level state by the second electrical level state, first transmission circuit 101 is to described
First signal enters line delay, while by first signal inversion, obtains secondary signal.
Wherein, first signal can be as the input signal of the bidirectional interface circuit.
Specifically, second electrical level state is changed into the process that the first level state can be rising edge, the first level state
It is changed into the process that second electrical level state can be trailing edge；When the first signal is rising edge, the first transmission circuit 101 is to
It is reverse that one signal enters line delay, obtains secondary signal.Because secondary signal is that the first signal inversion obtains, using first signal as
Benchmark, the trailing edge of secondary signal lag behind the rising edge of the first signal.
Second transmission circuit 102, for when the enable signal is first level state, receive described the
One signal, it is anti-phase to first signal delay to obtain the 3rd signal and export.
Second transmission circuit 102 to first signal delay it is anti-phase obtain the 3rd signal and export can be：When
When first signal by first level state transition is second electrical level state, second transmission circuit 102 is to described
First signal enters line delay, and by first signal inversion, obtains the 3rd signal.
Specifically, when the first signal is trailing edge, it is reverse that the second transmission circuit 102 enters line delay to the first signal, obtains
To the 3rd signal.Because the 3rd signal is what the first signal inversion obtained, on the basis of the first signal, the rising edge of the 3rd signal
Lag behind the trailing edge of the first signal.
First drive circuit 103, it is connected, uses with first transmission circuit 101 and second transmission circuit 102
In when the enable signal is first level state, the secondary signal is received from first transmission circuit 101, from
Second transmission circuit 102 receives the 3rd signal；And the secondary signal and the 3rd signal are based on, described double
The 4th signal is exported to the bidirectional port of interface circuit；Wherein, the secondary signal is converted to the second electricity by the first level state
During level state, lag behind the 3rd signal and second electrical level state is converted to by the first level state；3rd signal is by
When two level states are converted to the first level state, it is the first level to lag behind the secondary signal by second electrical level State Transferring
State.
Further, first drive circuit 103 is additionally operable to：It is the second electrical level state in the enable signal
When, the secondary signal in the first level state is received from first transmission circuit 101, from second transmission circuit
102 receive the 3rd signal in second electrical level state.Now, the output of the bidirectional port is in high-impedance state.
Wherein, first drive circuit 103 has two receiving terminals, receives the secondary signal and the 3rd signal
It is different receiving terminals respectively；When enable signal is the first level state, the 4th signal have the first level state and
Second electrical level state, the level state of the 4th signal are identical with the level state of first signal；When enable signal is
During second electrical level state, the output of first drive circuit 103 is in high-impedance state；Now, the bidirectional port receives external electrical
The signal of road transmission, the external signal received by the 3rd transmission circuit 104 to the bidirectional port are transmitted.
3rd transmission circuit 104, for when the enable signal is the second electrical level state, from described two-way
Port receives the 5th signal, and based on the 5th signal output and the signal of the 5th signal level state identical the 6th.
Wherein, the 5th signal is the input signal from bidirectional port in the bidirectional interface circuit, has first
Level state and second electrical level state；6th signal is the output signal of the bidirectional interface circuit, has the first level
State and second electrical level state.
Further, the 3rd transmission circuit 104, it is first level state to be additionally operable in the enable signal
When, the 6th signal based on enable signal output second electrical level state.
Specifically, when enable signal is the first level state, the first signal that bidirectional interface circuit receives is as input
Signal, the bidirectional port of bidirectional interface circuit receive as output port, the first transmission circuit 101 and the second transmission circuit 102
First signal and enable signal.
When the first signal is second electrical level state by the first level state transition, the first transmission circuit 101 is not to first
Signal enters line delay, only exports the secondary signal opposite with the first signal level state, and secondary signal is become by second electrical level state
For the first level state；Now, reception is second electrical level state by the first level state transition by the second transmission circuit 102
First signal enters line delay, exports the 3rd signal relative to the transformation delay of the first signal level state, the 3rd signal is by second
Level state transition is the first level state, and it is second electrical level state to lag behind the first signal by the first level state transition；This
Sample, when being changed into the first level state by second electrical level state due to secondary signal, turned with the first signal by the first level state
It is changed into second electrical level state to be consistent in sequential, the 3rd signal is changed into the first level state by second electrical level state and lagged
By the first level state transition it is second electrical level state in the first signal, the rising edge of the 3rd signal lags behind the upper of secondary signal
Rise edge.
When the first signal is changed into the first level state from second electrical level state, the first transmission circuit 101 is by the of reception
One signal enters line delay, exports the secondary signal relative to the transformation delay of the first signal level state, secondary signal is by the first electricity
Level state is changed into second electrical level state, lags behind the first signal and is changed into the first level state by second electrical level state；Now,
Two transmission circuits 102 do not enter line delay to the first signal, only export threeth signal opposite with the first signal level state, and the 3rd
Signal is changed into second electrical level state from the first level state；So, due to the 3rd signal by the first level state transition be second
During level state, the first level state is changed into by second electrical level state with the first signal and is consistent in sequential, the second letter
Number by the first level state transition be second electrical level state hysteresis the first level is changed into by second electrical level state in the first signal
State, the trailing edge of secondary signal lag behind the trailing edge of the 3rd signal.
Wherein, the rising edge is changed into the first level state for the level state of signal from second electrical level state；Under described
Drop is changed into second electrical level state along for the level state of signal from the first level state.
The time-lag action of first transmission circuit and the second transmission circuit, the trailing edge of secondary signal can be made to lag behind the 3rd
The trailing edge of signal, the rising edge of the 3rd signal lag behind the rising edge of secondary signal.So, connect in the first drive circuit 103
The closing of transistor of the 3rd signal of reception can be lagged behind by receiving unlatchings of the transistor of secondary signal, in the first drive circuit 103
The closing for the transistor for receiving secondary signal, the first drive circuit 103 can be lagged behind by receiving the unlatching of the transistor of the 3rd signal
In transistor be not in situation about simultaneously turning on, avoid the leaky caused by transistor simultaneously turns on.
Now, the enable signal of the 3rd transmission circuit 104 based on first level state, in the described 3rd transmission
6th signal of the output end output second electrical level state of circuit 104.
When enable signal is second electrical level state, no matter the first signal is in the first level state or second electrical level shape
State, the first transmission circuit 101 export the secondary signal of the first level state, the second transmission circuit 102 output second electrical level state
The 3rd signal, the transistor in the first drive circuit 103 is in cut-off state, and the output of the first drive circuit 103 is in height
Resistance state.
Now, input of the bidirectional port as the bidirectional interface circuit, the 3rd transmission circuit 104 is in institute
State bidirectional port and receive the 5th signal, export the 6th signal.5th signal is input signal, and the 6th signal is output
Signal, the level state of the 6th signal are identical with the level state of the 5th signal.
In the utility model embodiment, the concrete composition structure of the bidirectional interface circuit is as shown in Figure 2.
First transmission circuit 210 includes the first phase inverter 211 and the second phase inverter 212.
Wherein, first phase inverter 211, there is the first resistor being connected with ground terminal；Second phase inverter 212, tool
There is the second resistance being connected with power end.The phase inverter 212 of first phase inverter 211 and second, in first signal
When being changed into the first level state by second electrical level state, line delay is entered to first signal.
Wherein, the first resistor can be expressed as R1, and the second resistance can be expressed as R2, and supply voltage can be with table
It is shown as VDD.
Specifically, first transmission circuit 210 includes the first NAND gate and the first phase inverter group.Wherein, described
One NAND gate receives enable signal and the first signal；The first phase inverter group is made up of even number of inverters, and described first is anti-
Phase device group includes the first phase inverter 211 and the second phase inverter 212, and the phase inverter 212 of the first phase inverter 211 and second docks
The signal of receipts plays a part of delay.The phase inverter with delay function could be arranged to multiple in the phase inverter group, specifically
It can be set according to actual conditions by technical staff.The first phase inverter group is by 4 phase inverters in the utility model embodiment
Composition, the phase inverter with delay function are 2, i.e. the first phase inverter 211 and the second phase inverter 212.
First NAND gate has two inputs and an output end, and first NAND gate receives institute in input
The first signal and the enable signal are stated, is connected in output end with the first phase inverter group, 4 in the first phase inverter group
Connected between individual phase inverter；First phase inverter 211 has the first resistor being connected to ground, when the first phase inverter 211 receives
The signal received is held to be changed into the first level state by second electrical level state, the output signal of the first phase inverter 211 is by the first electricity
When level state is changed into second electrical level state, because the first resistor being connected to ground, the first phase inverter be present in the first phase inverter 211
When 211 output signal by the first level state transition is second electrical level state, the input signal of the first phase inverter 211 is lagged behind
First level state is changed into by second electrical level state；Second phase inverter 212 has the second resistance being connected with power supply, when
The signal that second phase inverter 212 receives is second electrical level state by the first level state transition, and the output of the second phase inverter 212 is believed
When number being changed into the first level state by second electrical level state, due to the second phase inverter 212, to have be connected with power supply second electric
Resistance, when the output signal of the second phase inverter 212 is changed into the first level state by second electrical level state, lags behind the second phase inverter
212 input signal is second electrical level state by the first level state transition.
Further, first transmission circuit 210 also includes the first protection sub-circuit 213.
The first protection sub-circuit 213, for when the enable signal is the second electrical level state, to described the
Other circuits of one transmission circuit 210 carry out overvoltage protection；When the enable signal is first level state, by described in
Secondary signal is transmitted to first drive circuit 230.
Wherein, the first protection sub-circuit 213 includes two transistors, can be expressed as NM6 and PM6, the crystal
Pipe can be that transistor is Metal-oxide-semicondutor (metal-oxide-semiconductor, MOS) in the present embodiment
FET, according to conduction type, metal-oxide-semiconductor can be divided into electron type FET (N-MOS) and cavity type FET (P-
MOS)。
Further, the first protection sub-circuit 213 also includes transistor NM4, NM5, PM5, electric capacity and 3rd resistor
R5, the voltage of the bidirectional port voltage change is followed for being provided for PM6 grid.
Wherein, NM6 N-MOS, for when the input signal of the bidirectional port is higher than preset value, electricity to be transmitted to first
Overvoltage protection effect is played on road 210, and the overtension for avoiding the bidirectional port from inputting makes the circuit in the first transmission circuit 210
Device sustains damage.PM6 is P-MOS, for when the enable signal is first level state, by the secondary signal
Transmit to first drive circuit 230.
Specifically, NM6 grid is connected with power supply, source electrode and the first phase inverter group in first transmission circuit 210
Output end be connected, drain electrode be connected with first drive circuit 230.NM6 is by first drive circuit 230 and described first
Transmission circuit 210 is isolated, because NM6 grid is connected with power supply, when NM6 drain voltage exceedes supply voltage, and NM6 source
Pole tension is not more than supply voltage, protects first transmission circuit 210 to be worked in the case of less than or equal to supply voltage,
Avoid the overvoltage of the first transmission circuit 210.
PM6 grid is connected with the drain electrode of the PM5, and source electrode is connected with NM6 drain electrode, and drain electrode is connected with NM6 source electrode,
When the enable signal is the first level state, the signal that the first phase inverter group exports is transferred to described first by PM6
Drive circuit 230.The NM6 and PM6 is while protection first transmission circuit 210 will not be over-pressed, it is ensured that
The transmission of signal between first transmission circuit 210 and first drive circuit 230.
NM4 grid receives the enable signal, and drain electrode is connected with NM5 source electrode, source ground；NM5 grid connection
Power supply, drain electrode are connected with PM6 grid, and source electrode connects NM4 drain electrode；PM5 drain electrode is connected with NM5 drain electrode, source electrode and institute
State bidirectional port to be connected, grid is connected with one end of electric capacity；One end of electric capacity is connected with PM5 grid, another termination of electric capacity
Ground；R5 one end is connected with PM5 grid, and the R5 other end is connected with NM3 source electrode.In the first protection sub-circuit 213
PM5 drain voltage can follow the variation in voltage of bidirectional port, i.e. the voltage of PM5 drain voltage and bidirectional port is same phase
Signal, PM5 drain voltage are no more than supply voltage, it is ensured that the grid voltage of the PM6 in the first transmission circuit 210 does not surpass
Supply voltage is crossed, PM6 is avoided over-pressed damage.
Further, second transmission circuit 220 includes the 3rd phase inverter 221 and the 4th phase inverter 222.
Wherein, the 3rd phase inverter 221, there is the 3rd resistor being connected with power supply；4th phase inverter 222, tool
There is the 4th resistance being connected with ground terminal；3rd phase inverter 221 and the 4th phase inverter 222, for first signal by
When first level state transition is second electrical level state, line delay is entered to first signal.
Wherein, the 3rd resistor can be expressed as R3, and the 4th resistance can be expressed as R4.
Specifically, second transmission circuit 220 includes NOT gate, nor gate and the second phase inverter group；Wherein, it is described non-
Door connects the enable signal, for by the enable signal it is anti-phase after export to nor gate；The second phase inverter group is by idol
Several phase inverter compositions, the second phase inverter group include the 3rd phase inverter 221 and the 4th phase inverter 222, and the described 3rd is anti-
The phase inverter 222 of phase device 221 and the 4th plays a part of delay to the signal of reception.With delay function in the phase inverter group
Phase inverter could be arranged to multiple, can specifically be set according to actual conditions by technical staff.The utility model embodiment
In the second phase inverter group be made up of 4 phase inverters, have delay function phase inverter be 2, i.e. the 3rd phase inverter 221 and the 4th
Phase inverter 222.
Wherein, the nor gate has two inputs and an output end, described in the input of the nor gate receives
First signal and it is anti-phase after enable signal, the output end of the nor gate is connected with the second phase inverter group；Described second
4 inverter series in phase inverter group, the input of the second phase inverter group connect the output end of the nor gate, and described the
The output end of two phase inverter groups connects first drive circuit 230；
Wherein, the 3rd phase inverter 221 has the 3rd resistor being connected with power supply, when the receiving terminal of the 3rd phase inverter 221
The signal of reception is second electrical level state by the first level state transition, and the output signal of the 3rd phase inverter 221 is by second electrical level
When state is changed into the first level state, because the 3rd resistor being connected with power supply, the 3rd phase inverter be present in the 3rd phase inverter 221
When 221 output signal is changed into the first level state by second electrical level state, the input letter of the 3rd phase inverter 221 can be lagged behind
Number it is second electrical level state by the first level state transition；4th phase inverter 222 has the 4th resistance being connected to ground, when
The signal that 4th phase inverter 222 receives is changed into the first level state, the output letter of the 4th phase inverter 222 for second electrical level state
When number being second electrical level state by the first level state transition, because the 4th resistance being connected to ground be present in the 4th phase inverter 222,
When the output signal of 4th phase inverter 222 is by the first level state transition second electrical level state, the 4th phase inverter 222 can be lagged behind
Input signal the first level state is changed into by second electrical level state.
Further, first drive circuit 230 includes the second drive sub-circuits 231 and the second protection sub-circuit 232.
Second drive sub-circuits 231, for when the enable signal is first level state, described in reception
Secondary signal, output and the 4th signal described in the first signal level state identical；When the enable signal is described the
During two level states, the output of the second drive sub-circuits 231 is in high-impedance state.
Second drive sub-circuits 231 include：First end, the second end and the 3rd end.
Wherein, the first end of second drive sub-circuits 231, for receiving the output of the first transmission circuit 210
The secondary signal；Second end of second drive sub-circuits 231, for connecting the bidirectional port, output the described 4th
Signal；3rd end of second drive sub-circuits 231, for connecting the second protection sub-circuit 232.
Second drive sub-circuits 231 can be that transistor PM1, the transistor PM1 be P-MOS, PM1 grid pair
The first end of second drive sub-circuits 231 is answered, PM1 drain electrode corresponds to the second end of second drive sub-circuits 231,
PM1 substrate corresponds to the 3rd end of second drive sub-circuits 231；
PM1 grid is connected with the drain electrode of NM6 in first transmission circuit 210, receives first transmission circuit 210
The secondary signal of output；The source electrode of the PM1 is connected with power supply；The drain electrode of the PM1 is connected with the bidirectional port；Institute
The substrate for stating PM1 is connected with the described second protection sub-circuit 232.
Specifically, when enable signal is the first level state, PM1 receives the second letter of the first transmission circuit 210 output
Number, if secondary signal is the first level state, as high level, PM1 cut-offs；If the secondary signal received is the second electricity
During level state, i.e. low level, the PM1 conductings, in the signal of bidirectional port output high level, that is, first electricity is exported
The 4th signal of level state.
When enable signal is second electrical level state, PM1 receives the first level of the fixation of the first transmission circuit 210 output
The secondary signal of state, now PM1 cut-offs.
The second protection sub-circuit 232, for when the enable signal is the second electrical level state, based on described
5th signal carries out overvoltage protection to second drive sub-circuits 231.
Further, the second protection sub-circuit 232 includes first end, the second end, the 3rd end；Wherein, described second
The first end of protection sub-circuit 232 is connected with power supply, and the second end of the second protection sub-circuit 232 connects with the bidirectional port
Connect, the 3rd end of the second protection sub-circuit 232 is connected with the 3rd end of second drive sub-circuits 231.
Specifically, the second protection sub-circuit 232 can be transistor PM2 and transistor PM3.PM2 and PM3 is P-
MOS.Wherein, PM2 source electrode connection power supply, the first end of the corresponding second protection sub-circuit 232；PM2 grid connection is small
In the voltage Vx of supply voltage, drain electrode is connected with PM3 source electrode, and the of sub-circuit 232 is protected in PM2 drain electrode corresponding described second
Three ends；PM3 source electrode connection PM2 drain electrode, grid connection power supply, drain electrode are connected with the bidirectional port, and PM3 drain electrode is corresponding
Second end of the second protection sub-circuit 232.The drain electrode of PM3 source electrode and PM2 is also connected with PM1 substrate, when described double
When being more than the input signal of supply voltage to port input, PM3 and PM2 cause PM1 underlayer voltage stable in input signal electricity
Between pressure and supply voltage, the leakage current in PM1 can be reduced.
Specifically, PM1 substrate is connected with the source electrode of PM2 drain electrode and PM3, and PM1 underlayer voltage is in bidirectional port
Input voltage and supply voltage between, when the input voltage of bidirectional port exceedes preset value, PM1 source electrode, substrate and leakage
Pole can form positive-negative-positive structure.And in the prior art, PM1 substrate is directly connected with source electrode, when PM1 drain voltages exceed source electrode,
The PN junction conducting formed between PM1 drain electrode and substrate, can produce substantial amounts of leakage current, PM1 substrate is connected to PM2 leakage
Pole and PM3 source electrode, the positive-negative-positive structure that PM1 source electrode, substrate and drain electrode are formed can efficiently reduce leakage caused by PN junction conducting
Electric current.
Wherein, preset value is the voltage of circuit normal work, can be supply voltage, or by technical staff according to reality
Demand is set.
Further, first drive circuit 230 also includes third transistor 233.The third transistor 233 has
Source electrode and drain electrode；The source electrode is connected with the first end of first drive circuit；The drain electrode is connected with the bidirectional port.
The third transistor 233 can be transistor PM4, be P-MOS, for adjusting second drive sub-circuits
The voltage of 231 first end, avoid the 231 anti-phase conducting of the second drive sub-circuits.PM4 grid connection power supply, source
Pole is connected with PM1 grid, and drain electrode is connected with the bidirectional port, and PM4 substrate terminal is connected with PM2 drain electrode.Due to PM4's
Source electrode connects PM1 grid.When the input voltage of the bidirectional port is more than supply voltage, when PM4 is turned on, PM1 grid
Voltage will follow the voltage change of the bidirectional port, and for PM1 grid voltage also above supply voltage, such PM1 would not
Anti-phase conducting.
Specifically, PM4 is connected between PM1 grid and drain electrode, so, PM1 grid voltage can follow bidirectional port
Variation in voltage, when the voltage of bidirectional port exceedes preset value, the voltage of PM1 drain and gate is all the voltage of bidirectional port
Value, so, PM1 would not reverse-conducting.Conventionally, as PM1 grid voltage will not follow drain voltage change,
It is more than PM1 source voltage in PM1 drain voltage, and PM1 drain voltage and the difference of grid voltage are more than PMOS threshold values electricity
During pressure, PM1 drain electrode acts as source electrode, and source electrode acts as drain electrode, PM1 reverse-conductings, forms substantial amounts of leakage current, cause
Circuit component damage.
First drive circuit 230, in addition to the 3rd drive sub-circuits 234.
3rd drive sub-circuits 234 are used for when the enable signal is first level state, the institute of reception
State the 3rd signal；When the 3rd signal is first level state, the described 4th of the second electrical level state is exported
Signal.
3rd drive sub-circuits 234 include the first transistor and second transistor；Wherein, the first transistor,
For when the enable signal is the first level state, receiving the 3rd signal；When the 3rd signal is described first
During level state, the second transistor is set to export the 4th signal of the second electrical level state；The second transistor,
Connected with the first transistor, for when the enable signal is second electrical level state, receiving the 5th signal, and base
Partial pressure protection is carried out to the first transistor in the 5th signal, shares the bidirectional port to the portion voltage of ground terminal,
Avoid the first transistor excessive pressure damages.
Specifically, the first transistor can be transistor NM1, and the second transistor can be transistor NM2,
NM1 and NM2 is N-MOS；NM1 drain electrode is connected with NM2 source electrode, and NM1 grid reception second transmission circuit 220 is defeated
The 4th signal gone out, NM1 source ground；NM2 drain electrode is connected with the bidirectional port, NM2 grid connection power supply, NM2
Source electrode connection NM1 drain electrode.
When the 3rd signal is the first level state, NM1 conductings, NM2 exports second electrical level in the bidirectional port
The 4th signal of state；When the 3rd signal is second electrical level state, NM1 cut-offs.
The NM1 and NM2 series connection, when the voltage of bidirectional port input exceedes supply voltage, NM1 and NM2 can be with
The voltage of input is shared jointly, and NM1 will not be damaged due to overvoltage.
Further, when the enable signal is the first level state, the secondary signal and first signal
Level state is on the contrary, the 3rd signal is opposite with the level state of first signal；Second drive sub-circuits 231 with
3rd drive sub-circuits 234 export the institute with the first signal level state in-phase to the signal collective effect of reception
State the 4th signal.When the enable signal is second electrical level state, no matter first signal be in the first level state or
Person's second electrical level state, the secondary signal all in the first level state, the 3rd signal all in second electrical level state,
The output of second drive sub-circuits 231 and the 3rd drive sub-circuits 234 is in high-impedance state.Now bidirectional interface is as double
To the input port of interface circuit, in the state for receiving input signal.
3rd transmission circuit 240 includes the 3rd protection sub-circuit 241, the second NAND gate and the 5th phase inverter.
Wherein, the 3rd protection sub-circuit 241, for receiving the 5th signal from the bidirectional port, and in institute
When stating the 5th signal and being more than preset value, in output signal of the output end output less than the preset value.
Wherein, preset value is supply voltage or the signal value set by technical staff.
The 3rd protection sub-circuit 241 includes input and output end；Wherein, the input of the 3rd protection sub-circuit 241
End is connected with the bidirectional port；In output end and the 3rd transmission circuit 240 of 3rd protection sub-circuit 241 second with
NOT gate is connected.The 3rd protection sub-circuit 241 can be transistor NM3, and NM3 N-MOS, NM3 grid connect power supply, source
Pole is connected with the input of the NAND gate, and drain electrode is connected with the bidirectional port.Because NM3 grid is connected with power supply, when
When the input voltage of the bidirectional port is more than supply voltage, NM3 source voltage terminal is not over supply voltage, to the described 3rd
Transmission circuit 240 is protected.
Second NAND gate of the 3rd transmission circuit 240 has two inputs and an output end, the second NAND gate
An input receive the inversion signal of the enable signal, another input of the second NAND gate receives the described 3rd and protected
Protect the signal that sub-circuit 241 exports；The output end of second NAND gate connects the input of the 5th phase inverter in the 3rd transmission circuit 240
End, the 5th phase inverter export the 6th signal.
The inversion signal of the enable signal in the present embodiment, can be that one of second transmission circuit 220 is non-
Door enable signal is carried out it is anti-phase after output signal or an independence being connected to before second NAND gate
NOT gate carries out anti-phase output signal to enable signal, and the independent NOT gate is independently of second transmission circuit 220 and described
3rd transmission circuit 240
When a NOT gate in using second transmission circuit 220 carries out anti-phase to the enable signal, can subtract
Electronic component used in few whole bidirectional interface circuit, can simplify structure and reduce hardware cost.
3rd transmission circuit 240 in certain embodiments, it may also include an output end and second NAND gate
The NOT gate of connection, for the anti-phase enable signal.
In the utility model embodiment, the transistor can also be heterojunction bipolar transistor
(Heterojunction Bipolar Transistor, HBT), bipolar junction transistor (Bipolar Junction
Transistor, BJT) etc. circuit element.
It is described above, preferred embodiment only of the present utility model, it is not intended to limit protection of the present utility model
Scope.
Claims (10)
- A kind of 1. bidirectional interface circuit, it is characterised in that including：First transmission circuit, the second transmission circuit, the first drive circuit And the 3rd transmission circuit；First transmission circuit, for when enable signal is the first level state, receiving the first signal, believe described first Number delay anti-phase obtain secondary signal and exported；Second transmission circuit, for when the enable signal is first level state, receiving first signal, It is anti-phase to first signal delay to obtain the 3rd signal and export；First drive circuit, it is connected with first transmission circuit and second transmission circuit, for described enabled When signal is first level state, the secondary signal is received from first transmission circuit, from the described second transmission electricity Road receives the 3rd signal；And the secondary signal and the 3rd signal are based on, in the two-way of the bidirectional interface circuit Port exports the 4th signal；Wherein, when the secondary signal is converted to second electrical level state by first level state, hysteresis The second electrical level state is converted to by first level state in the 3rd signal；3rd signal is by described second When level state is converted to the first level state, it is described the to lag behind the secondary signal by the second electrical level State Transferring One level state；3rd transmission circuit, for when the enable signal is the second electrical level state, being connect from the bidirectional port The 5th signal is received, and based on the 5th signal output and the signal of the 5th signal level state identical the 6th.
- 2. circuit according to claim 1, it is characterised in that first transmission circuit, including：First phase inverter and Two phase inverters；Wherein,First phase inverter, there is the first resistor being connected with ground terminal；Second phase inverter, there is the second resistance being connected with power end；First phase inverter and the second phase inverter, it is described for being changed into first signal by the second electrical level state During the first level state, line delay is entered to first signal.
- 3. circuit according to claim 2, it is characterised in that first transmission circuit, in addition to：First protection son electricity Road；The first protection sub-circuit, for when the enable signal is the second electrical level state, being transmitted to described first Circuit carries out overvoltage protection；When the enable signal is first level state, the secondary signal is transmitted to described First drive circuit.
- 4. circuit according to claim 1, it is characterised in that second transmission circuit, including：3rd phase inverter and Four phase inverters；Wherein,3rd phase inverter, there is the 3rd resistor being connected with power supply；4th phase inverter, there is the 4th resistance being connected with ground terminal；3rd phase inverter and the 4th phase inverter, for by first level state transition being described in first signal During second electrical level state, line delay is entered to first signal.
- 5. circuit according to claim 1, it is characterised in that first drive circuit, including：Second drive sub-circuits and the second protection sub-circuit；Wherein,Second drive sub-circuits, for when the enable signal is first level state, described the second of reception Signal, when the secondary signal is the second electrical level state, export the 4th signal of first level state.The second protection sub-circuit, for when the enable signal is the second electrical level state, believing based on the described 5th Number to second drive sub-circuits carry out overvoltage protection.
- 6. circuit according to claim 5, it is characterised in that second drive sub-circuits, including：First end, the second end and the 3rd end；Wherein,The first end, for receiving the secondary signal of the first transmission circuit output；Second end, for connecting the bidirectional port, export the 4th signal；3rd end, for connecting the second protection sub-circuit.
- 7. circuit according to claim 6, it is characterised in that first drive circuit, in addition to：3rd drive sub-circuits, for when the enable signal is first level state, the 3rd signal of reception； When the 3rd signal is first level state, the 4th signal of the second electrical level state is exported.
- 8. circuit according to claim 7, it is characterised in that the 3rd drive sub-circuits, including：The first transistor and Second transistor；The first transistor, for when the enable signal is the first level state, receiving the 3rd signal；When described When 3rd signal is the second electrical level state, the second transistor is set to export the 4th letter of the second electrical level state Number；The second transistor, connected with the first transistor, for when the enable signal is second electrical level state, connecing The 5th signal is received, and partial pressure protection is carried out to the first transistor based on the 5th signal.
- 9. circuit according to claim 8, it is characterised in that first drive circuit, in addition to：Third transistor, there is source electrode and drain electrode；The source electrode is connected with the first end of first drive circuit；The drain electrode is connected with the bidirectional port.
- 10. circuit according to claim 1, it is characterised in that the 3rd transmission circuit, including：3rd protection son electricity Road；The 3rd protection sub-circuit, including input and output end, the input are connected with the bidirectional port, described defeated Go out end with the gate circuit of the 3rd transmission circuit to be connected, for receiving the 5th signal from the bidirectional port, and in institute When stating the 5th signal and being more than preset value, in output signal of the output end output less than the preset value.
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|---|---|---|---|
| CN201720970658.4U CN207200682U (en) | 2017-08-04 | 2017-08-04 | Bidirectional interface circuit |
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| CN201720970658.4U CN207200682U (en) | 2017-08-04 | 2017-08-04 | Bidirectional interface circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395192A (en) * | 2017-08-04 | 2017-11-24 | 尚睿微电子（上海）有限公司 | Bidirectional interface circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395192A (en) * | 2017-08-04 | 2017-11-24 | 尚睿微电子（上海）有限公司 | Bidirectional interface circuit |
| CN107395192B (en) * | 2017-08-04 | 2024-03-22 | 尚睿微电子（上海）有限公司 | Bidirectional interface circuit |
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