CN111653475A - 一种三维堆叠对准方法 - Google Patents
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Abstract
本发明公开了一种三维堆叠对准方法,具体包括如下步骤:101)基础芯片安置步骤、102)叠加芯片定位步骤、103)键合步骤;本发明提供避免了芯片键合过程中误差的一种三维堆叠对准方法。
Description
技术领域
本发明涉及半导体技术领域,更具体的说,它涉及一种三维堆叠对准方法。
背景技术
微波毫米波射频集成电路技术是现代国防武器装备和互联网产业的基础,随着智能通信、智能家居、智能物流、智能交通等“互联网+”经济的快速兴起,承担数据接入和传输功能的微波毫米波射频集成电路也存在巨大现实需求及潜在市场。
但是对于高频率的微系统,天线阵列的面积越来越小,且天线之间的距离要保持在某个特定范围,才能使整个模组具备优良的通信能力。但是对于射频芯片这种模拟器件芯片来讲,其面积不能像数字芯片一样成倍率的缩小,这样就会出现特高频率的射频微系统将没有足够的面积同时放置PA/LNA,需要把PA/LNA堆叠起来。
目前业内用于三维异构堆叠的工艺,基本都是光学对准,预先在晶圆表面设置对准mark,然后通过光学对准技术抓住mark点,通过马达和履带传输把芯片和芯片进行对准。在这一整套流程中,mark制作的位置往往跟最后的焊接不是一次作业完成,因此在套刻方面存在误差,同时光学抓mark点也存在误差,在履带推进方面上下芯片的传输同样存在误差,对于后面越来越高精度的模组来讲,这些误差可能会导致产品堆叠的失误,或者降低模组的可靠性。
发明内容
本发明克服了现有技术的不足,提供避免了芯片键合过程中误差的一种三维堆叠对准方法。
本发明的技术方案如下:
一种三维堆叠对准方法,具体包括如下步骤:
101)基础芯片安置步骤:在L型基座表面放置基础芯片,基座底部设置固定基础芯片的自动吸气装置;基础芯片放置在基座后,以基座的侧边进行初步对准;
把X射线镜头对基础芯片定位点进行扫描,位置归零后,输入待键合线条的方位坐标,把X射线镜头移动至待键合线条上;
102)叠加芯片定位步骤:手动放置或用相应吸气设备放置待键合的叠加芯片在基础芯片的上方,叠加芯片紧贴基座侧边,完成初步校准;
去除基座的侧边,在叠加芯片的侧边设置推力装置,推力装置均匀分布在叠加芯片的边上;X射线观察下,当两个芯片待键合区域重合后,撤走推力装置,完成定位;
103)键合步骤:在叠加芯片顶部施加压力,压力范围在10g到10kg之间,固定住需要键合的基础芯片和叠加芯片;L型基座底部加热,加热温度控制在150度到500度之间,完成芯片键合。
进一步的,基座厚度范围为200um到2000um之间,材质采用玻璃、石英、碳化硅、氧化铝等、环氧树脂、聚氨酯中的一种;基座提供支撑作用。
进一步的,推力装置采用可实现手动0.1微米精度的微调装置,实现对叠加芯片进行两个轴向的微小移动和旋转移动。
进一步的,推力装置设置四个或其倍数的数量。
本发明相比现有技术优点在于:本发明通过设置X射线装置,可以更直观的将上下芯片的待键合区域进行对准检查和微调,避免了芯片键合过程中的误差问题,增加了芯片键合的精度。
附图说明
图1为本发明的基座与基础芯片示意图;
图2为本发明的图1上设置叠加芯片示意图;
图3为本发明的推力装置调整示意图;
图4为本发明的键合的示意图。
图中标识:基座1、基础芯片2、叠加芯片3、推力装置4。
具体实施方式
下面详细描述本发明的实施方式,其中自始至终相同或类似的标号表示相同或类似的元件或类似功能的元件。下面通过参考附图描述的实施方式是示例性的,仅用于解释本发明而不能作为对本发明的限制。
本技术领域技术人员可以理解的是,除非另外定义,这里使用的所有术语(包括技术术语和科技术语)具有与本发明所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是,诸如通用字典中定义的那些术语应该被理解为具有与现有技术的上下文中的意义一致的意义,并且除非像这里一样的定义,不会用理想化或过于正式的含义来解释。
各实施方式中提到的有关于步骤的标号,仅仅是为了描述的方便,而没有实质上先后顺序的联系。各具体实施方式中的不同步骤,可以进行不同先后顺序的组合,实现本发明的发明目的。
下面结合附图和具体实施方式对本发明进一步说明。
实施例1:
如图1至图4所示,一种三维堆叠对准方法,具体包括如下步骤:
101)基础芯片2安置步骤:在L型基座1表面放置基础芯片2,基座1底部设置固定基础芯片2的自动吸气装置;基础芯片2放置在基座1后,以基座1的侧边进行初步对准。
把X射线镜头对基础芯片2定位点进行扫描,位置归零后,输入待键合线条的方位坐标,把X射线镜头移动至待键合线条上。完成基础芯片2的定位,和后续的校准做准备。
其中,基座1厚度范围为200um到2000um之间,材质包括硅、玻璃、石英、碳化硅、氧化铝等无机材料,也可以是环氧树脂,聚氨酯等有机材料,其主要功能是提供支撑作用。
102)叠加芯片3定位步骤:手动放置或用相应吸气设备放置待键合的叠加芯片3在基础芯片2的上方,叠加芯片3紧贴基座1侧边,完成初步校准;
去除基座1的侧边,在叠加芯片3的侧边设置推力装置4,推力装置4均匀分布在叠加芯片3的边上;X射线观察下,当两个芯片待键合区域重合后,撤走推力装置4,完成定位。推力装置4采用可实现手动0.1微米精度的微调装置,实现对叠加芯片3进行两个轴向的微小移动和旋转移动。推力装置4设置四个或其倍数的数量,因为叠加芯片3多为矩形,每边设置一个或多个推力装置4,一般每边不会超过四个推力装置4。
103)键合步骤:在叠加芯片3顶部施加压力,压力范围在10g到10kg之间,固定住需要键合的基础芯片2和叠加芯片3;L型基座1底部加热,加热温度控制在150度到500度之间,完成芯片键合。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明构思的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明保护范围内。
Claims (4)
1.一种三维堆叠对准方法,其特征在于:具体包括如下步骤:
101)基础芯片安置步骤:在L型基座表面放置基础芯片,基座底部设置固定基础芯片的自动吸气装置;基础芯片放置在基座后,以基座的侧边进行初步对准;
把X射线镜头对基础芯片定位点进行扫描,位置归零后,输入待键合线条的方位坐标,把X射线镜头移动至待键合线条上;
102)叠加芯片定位步骤:手动放置或用相应吸气设备放置待键合的叠加芯片在基础芯片的上方,叠加芯片紧贴基座侧边,完成初步校准;
去除基座的侧边,在叠加芯片的侧边设置推力装置,推力装置均匀分布在叠加芯片的边上;X射线观察下,当两个芯片待键合区域重合后,撤走推力装置,完成定位;
103)键合步骤:在叠加芯片顶部施加压力,压力范围在10g到10kg之间,固定住需要键合的基础芯片和叠加芯片;L型基座底部加热,加热温度控制在150度到500度之间,完成芯片键合。
2.根据权利要求1所述的一种三维堆叠对准方法,其特征在于:基座厚度范围为200um到2000um之间,材质采用玻璃、石英、碳化硅、氧化铝等、环氧树脂、聚氨酯中的一种;基座提供支撑作用。
3.根据权利要求1所述的一种三维堆叠对准方法,其特征在于:推力装置采用可实现手动0.1微米精度的微调装置,实现对叠加芯片进行两个轴向的微小移动和旋转移动。
4.根据权利要求1所述的一种三维堆叠对准方法,其特征在于:推力装置设置四个或其倍数的数量。
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KR20020079209A (ko) * | 2001-04-13 | 2002-10-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 |
CN1649116A (zh) * | 2003-11-11 | 2005-08-03 | 优利讯国际贸易有限责任公司 | 贴装半导体芯片的设备 |
US20060110906A1 (en) * | 2004-11-23 | 2006-05-25 | Magnachip Semiconductor, Ltd. | Wafer alignment method |
JP2007158103A (ja) * | 2005-12-06 | 2007-06-21 | Shibuya Kogyo Co Ltd | チップ突き上げ装置 |
JP2013026544A (ja) * | 2011-07-25 | 2013-02-04 | Disco Abrasive Syst Ltd | ウェーハ拡張装置 |
CN108206142A (zh) * | 2016-12-20 | 2018-06-26 | 中芯国际集成电路制造(上海)有限公司 | 一种键合对准精度的检测方法和半导体器件 |
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KR20020079209A (ko) * | 2001-04-13 | 2002-10-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 |
CN1649116A (zh) * | 2003-11-11 | 2005-08-03 | 优利讯国际贸易有限责任公司 | 贴装半导体芯片的设备 |
US20060110906A1 (en) * | 2004-11-23 | 2006-05-25 | Magnachip Semiconductor, Ltd. | Wafer alignment method |
JP2007158103A (ja) * | 2005-12-06 | 2007-06-21 | Shibuya Kogyo Co Ltd | チップ突き上げ装置 |
JP2013026544A (ja) * | 2011-07-25 | 2013-02-04 | Disco Abrasive Syst Ltd | ウェーハ拡張装置 |
CN108206142A (zh) * | 2016-12-20 | 2018-06-26 | 中芯国际集成电路制造(上海)有限公司 | 一种键合对准精度的检测方法和半导体器件 |
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