CN111640683B - Method for preparing lug on driving chip - Google Patents
Method for preparing lug on driving chip Download PDFInfo
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- CN111640683B CN111640683B CN202010514199.5A CN202010514199A CN111640683B CN 111640683 B CN111640683 B CN 111640683B CN 202010514199 A CN202010514199 A CN 202010514199A CN 111640683 B CN111640683 B CN 111640683B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
Abstract
The application discloses a method for preparing a convex block on a driving chip, which comprises the following steps: forming a removable protective layer on the surface of a groove circuit area on the functional surface of the driving chip, wherein at least one pad around the groove circuit area is exposed out of the protective layer, and the orthographic projection of the protective layer on the functional surface is larger than that of one end of the protective layer, which is in contact with the functional surface, on the functional surface; forming metal layers on the functional surface and one side of the protective layer far away from the functional surface, wherein a gap is formed between the metal layer on the functional surface and one end of the protective layer; respectively forming a metal bump at each bonding pad position; removing the protective layer and the metal layer on the surface of the protective layer; and removing the metal layer which is not covered by the metal bump around the metal bump. In this way, this application can make on the driver chip functional surface in the slot circuit district no metal remain, avoids leading to the driver chip short circuit because of slot circuit district is connected with remaining metal electricity, improves driver chip's reliability.
Description
Technical Field
The application relates to the technical field of driving chips, in particular to a method for preparing a convex block on a driving chip.
Background
The driving chip integrates at least two functions, such as a Touch and Display Driver Integration (TDDI) chip, the Touch chip and the Display chip are integrated into a single chip, and the circuit area of the driving chip is complex to design for integrating at least two chips, so that the functional surface of the driving chip usually has grooves arranged in an array to accommodate the complex circuit area.
In the prior art, when a metal bump is formed on a functional surface of a chip, a metal layer is usually formed on the functional surface of the chip, but after the metal layer is formed on the functional surface of a driver chip, the metal layer is also formed in a groove on the functional surface, and it is difficult to completely remove the metal in the groove when the metal in the groove is removed by a subsequent etching process, so that the metal is remained in the groove to increase the probability of short circuit of the driver chip, and the reliability of the driver chip is reduced.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a method for preparing a bump on a driver chip, which can enable no metal residue in a groove circuit area on a functional surface of the driver chip, avoid the short circuit of the driver chip caused by the electric connection of the groove circuit area and the residual metal, and improve the reliability of the driver chip.
In order to solve the technical problem, the application adopts a technical scheme that: a method for preparing a bump on a driving chip comprises the following steps:
forming a removable protective layer on the surface of a groove circuit area on a functional surface of a driving chip, wherein at least one pad around the groove circuit area is exposed out of the protective layer, and the orthographic projection of the protective layer on the functional surface is larger than that of one end of the protective layer, which is in contact with the functional surface, on the functional surface; forming metal layers on the functional surface and one side, far away from the functional surface, of the protective layer, wherein a gap is formed between the metal layer on the functional surface and the one end of the protective layer; respectively forming a metal bump at each bonding pad position; removing the protective layer and the metal layer on the surface of the protective layer; and removing the metal layer which is not covered by the metal bump around the metal bump.
And the size of one end of the protective layer close to the functional surface is gradually reduced along the direction close to the functional surface.
Wherein, the vertical section of the protective layer is in an inverted trapezoid shape.
Wherein, form removable protective layer on the functional surface of driver chip's slot circuit district surface, include: forming a first photoresist on one side of the functional surface of the driving chip; and removing part of the first photoresist, and only remaining the first photoresist at the position corresponding to the groove circuit area so as to form the protective layer at the position corresponding to the groove circuit area.
Wherein the forming a metal bump at each of the pad locations, respectively, comprises: forming a second photoresist on one side of the metal layer, wherein the second photoresist covers one side of the protective layer far away from the functional surface and the side surface of the protective layer; forming a first opening on the second photoresist corresponding to the position of the bonding pad; the second photoresist reserved on two sides of the first opening covers two sides of the protective layer and the metal layer on the surface of the protective layer; and forming the metal bump in the first opening by electroplating, wherein the metal bump is electrically connected with the bonding pad.
Wherein the first photoresist and the second photoresist are both negative photoresist, and after the metal bump is formed in the first opening, the method further includes: and removing the second photoresist on two sides of the metal bump by using a photoresist remover, and removing the protective layer wrapped by the second photoresist and the metal layer covered on the protective layer together with the second photoresist.
Wherein, the metal bump is formed in the first opening by electroplating, and then, the method further comprises: and forming a metal planarization layer on the surface of the metal bump, which is far away from the pad, wherein the surface of one side of the metal planarization layer, which is far away from the pad, is smooth.
Wherein, it keeps away from functional face one side at functional face and protective layer forms the metal level, includes: forming a first sub-metal layer on the functional surface and on one side of the protective layer far away from the functional surface, wherein a gap is formed between the first sub-metal layer on the functional surface and the one end of the protective layer; and forming a second sub-metal layer on the first sub-metal layer.
The first sub-metal layer and the second sub-metal layer are made of different materials, and the hardness of the first sub-metal layer is greater than that of the second sub-metal layer.
The material of the second sub-metal layer is the same as that of the metal bump.
The beneficial effect of this application is: according to the method, the protective layer is arranged in the groove circuit area on one side of the functional surface of the driving chip, so that when a metal layer and a metal bump are formed in the subsequent process, no metal is remained in the groove circuit area, the driving chip is prevented from being short-circuited due to the fact that the groove circuit area is electrically connected with the residual metal, and the reliability of the driving chip is improved; and because the orthographic projection of protective layer on the functional surface is greater than its orthographic projection on the functional surface with the one end of functional surface contact, this mode can be so that when functional surface and protective layer keep away from functional surface one side formation metal level, lie in and have the interval between the one end of metal level on the functional surface and protective layer, follow-up can get rid of the metal level of protective layer and top comparatively easily, and can not influence the metal level on the functional surface.
And then follow-up when getting rid of the protective layer, wrap up the protective layer completely, because the protective layer is kept away from one side width of functional surface and is greater than the one side with the contact of functional surface, and then the combination of protective layer and parcel layer is inseparabler, can peel off the protective layer from the functional surface when getting rid of the parcel layer, make the protective layer more simple and convenient and can not destroy driver chip's functional surface when getting rid of.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart illustrating one embodiment of a method for fabricating bumps on a driver chip according to the present disclosure;
FIG. 2 is a schematic cross-sectional view of an embodiment corresponding to step S101 in FIG. 1;
FIG. 3 is a schematic flowchart of an embodiment corresponding to step S101 in FIG. 1;
FIG. 4a is a schematic cross-sectional view of an embodiment corresponding to step S201 in FIG. 3;
FIG. 4b is a schematic cross-sectional view of an embodiment corresponding to step S202 in FIG. 3;
FIG. 5 is a schematic cross-sectional view of an embodiment corresponding to step S102 in FIG. 1;
FIG. 6 is a schematic flowchart of an embodiment corresponding to step S103 in FIG. 1;
FIG. 7a is a schematic cross-sectional view of an embodiment corresponding to step S301 in FIG. 6;
FIG. 7b is a schematic cross-sectional view of an embodiment corresponding to step S302 in FIG. 6;
FIG. 7c is a schematic cross-sectional view of an embodiment corresponding to step S303 in FIG. 6;
FIG. 7d is a schematic cross-sectional view of one embodiment after step S303 in FIG. 6;
FIG. 8 is a schematic cross-sectional view of an embodiment corresponding to step S104 in FIG. 1;
fig. 9 is a schematic cross-sectional structural diagram of an embodiment corresponding to step S105 in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a method for manufacturing bumps on a driving chip, the method including:
step S101: a removable protective layer is formed on the surface of the groove circuit area on the functional surface of the driving chip, at least one pad around the groove circuit area is exposed out of the protective layer, and the orthographic projection of the protective layer on the functional surface is larger than that of one end of the protective layer, which is in contact with the functional surface, on the functional surface.
Specifically, referring to fig. 2, fig. 2 is a schematic cross-sectional view of an embodiment corresponding to step S101 in fig. 1, a side of the driving chip 12 contacting the pad 120 is a functional surface (not shown) of the driving chip 12, and the protective layer 16 is formed on the trench circuit region 14 on the functional surface of the driving chip 12. The trench circuit region 14 may be located between adjacent pads 120, and may include a plurality of spaced grooves. The protective layer 16 covers the trench circuit region 14 to prevent metal from remaining in the trench circuit region 14, and the width of the protective layer 16 away from the functional surface is larger than that of the protective layer close to the functional surface, which facilitates the subsequent removal of the protective layer 16. The pad 120 on the functional surface is not covered by the protective layer 16, the pad 120 is exposed from the surface of the functional surface, and if the passivation layer 13 is included on the functional surface side of the driving chip 12, the pad 120 is exposed from the passivation layer 13; the protective layer 16 may be located over the passivation layer 13.
In a specific application scenario, the end of the protective layer 16 near the functional surface gradually decreases in size in the direction near the functional surface. The size of the protective layer 16 decreases stepwise from the end away from the functional surface to the end close to the functional surface, but the shape of the protective layer 16 on the side away from the functional surface is not particularly limited in the present application. The end of the protective layer 16 near the functional surface is gradually reduced in size in the direction near the functional surface, so that a structure with a wide top and a narrow bottom exists on the protective layer 16.
In another specific application scenario, the vertical cross-section of the protective layer 16 is an inverted trapezoid, and the structure of the protective layer 16 gradually increases in width from the functional surface toward a direction away from the functional surface.
In an application manner, please refer to fig. 3, where fig. 3 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 1, where the step S101 specifically includes:
step S201: and forming a first photoresist on one side of the functional surface of the driving chip.
Specifically, referring to fig. 4a, fig. 4a is a schematic cross-sectional structural view of an embodiment corresponding to step S201 in fig. 3, a first photoresist 20 is coated on one side of the functional surface of the driver chip 12, the first photoresist 20 covers one side of the functional surface, and the pad 120 and the trench circuit region 14 on one side of the functional surface are both covered by the first photoresist 20, wherein the first photoresist 20 is a negative photoresist.
Step S202: and removing part of the first photoresist, and only remaining the first photoresist at the position corresponding to the groove circuit area so as to form a protective layer at the position corresponding to the groove circuit area.
Specifically, referring to fig. 4b, fig. 4b is a schematic cross-sectional structure diagram of an embodiment corresponding to step S202 in fig. 3, a first light shielding plate 22 is disposed on a side of the first photoresist 20 away from the functional surface of the driving chip 12, when the first photoresist 20 is a negative photoresist, a position on the first light shielding plate 22 corresponding to the trench circuit area 14 is light-permeable, and other positions are light-impermeable, the light intensity and the light time are controlled, the first photoresist 20 is exposed, the first photoresist 20 outside the trench circuit area 14 is removed, the exposed first photoresist 20 is disposed in a developing solution, and the remaining photoresist is developed to form the protection layer 16 shown in fig. 2.
Step S102: and a metal layer is formed on one side of the functional surface and the protective layer, which is far away from the functional surface, and a gap is formed between the metal layer positioned on the functional surface and one end of the protective layer.
Specifically, referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of an embodiment corresponding to step S102 in fig. 1, wherein the metal layer 30 includes a first sub-metal layer 300 and a second sub-metal layer 302. The first sub-metal layer 300 is formed on the functional surface and the side of the protection layer 16 away from the functional surface, and a gap 304 is formed between the first sub-metal layer 300 on the functional surface and one end of the protection layer 16. The first sub-metal layer 300 is electrically connected to the pad 120. Since the protection layer 16 covers the trench circuit region 14 and protrudes from the surface of the functional surface of the driving chip 12, when the first sub-metal layer 300 is deposited on the functional surface, there is a gap 304 between the first sub-metal layer 300 on the functional surface and the first sub-metal layer 300 on the protection layer 16 due to the obstruction of the protection layer 16, and there is no coverage of the first sub-metal layer 300 on the functional surface around the trench circuit region 14.
Further, a second sub-metal layer 302 is formed on the first sub-metal layer 300. And depositing or electroplating a second sub-metal layer 302 on the first sub-metal layer 300, wherein the second sub-metal layer 302 covers the surface of the first sub-metal layer 300, and a space 304 is formed between the metal layer 30 on the functional surface and one end of the protective layer 16. The first sub-metal layer 300 and the second sub-metal layer 302 are made of different materials, and the hardness of the first sub-metal layer 300 is greater than that of the second sub-metal layer 302. The first sub-metal layer 300 is deposited on the functional surface and the surface of the protection layer 16, so as to facilitate the subsequent deposition or electroplating of the second sub-metal layer 302, and the hardness of the first sub-metal layer 300 is greater, so that the first sub-metal layer is more stable and less prone to deformation on the pad 120.
Specifically, the material of the first sub-metal layer 300 may be titanium-tungsten alloy, and the material of the second sub-metal layer 302 may be gold or copper.
Step S103: a metal bump is formed at each pad location, respectively.
In an application manner, please refer to fig. 6, where fig. 6 is a flowchart illustrating an embodiment corresponding to step S103 in fig. 1, where the step S103 specifically includes:
step S301: and forming a second photoresist on one side of the metal layer, wherein the second photoresist covers one side of the protective layer far away from the functional surface and the side surface of the protective layer.
Specifically, referring to fig. 7a, fig. 7a is a schematic cross-sectional structure view of an embodiment corresponding to step S301 in fig. 6, a second photoresist 40 is coated on a side of the metal layer 30 away from the functional surface of the driver chip 12, the second photoresist 40 completely covers the protective layer 16 of the metal layer 30 and the area of the trench circuit region 14 not covered by the metal layer 30, wherein the protective layer 16 is embedded in the second photoresist 40, and the second photoresist 40 is a negative photoresist.
Step S302: forming a first opening on the second photoresist at a position corresponding to the bonding pad; and the two sides of the protective layer and the metal layer on the surface of the protective layer are covered by the reserved second photoresist on the two sides of the first opening.
Specifically, referring to fig. 7b, fig. 7b is a schematic cross-sectional structural view of an embodiment corresponding to step S302 in fig. 6, a second light shielding plate 42 is disposed on one side of the second photoresist 40 away from the functional surface of the driving chip 12, when the second photoresist 40 is a negative photoresist, the position on the second light shielding plate 42 corresponding to the pad 120 is made opaque, and the other positions are made transparent, so as to control the illumination intensity and the illumination time, expose the second photoresist 40, remove the second photoresist 40 at the position corresponding to the pad 120, form a first opening (not shown) on the second photoresist 40, and the second photoresist 40 retained at two sides of the first opening still completely wraps and covers the protective layer 16 and the metal layer 30 on the surface of the protective layer 16.
Step S303: and forming a metal bump in the first opening by electroplating, wherein the metal bump is electrically connected with the bonding pad.
Specifically, referring to fig. 7c, fig. 7c is a schematic cross-sectional structure diagram of an embodiment corresponding to step S303 in fig. 6, a metal bump 50 is formed in the first opening of the second photoresist 40 by electroplating, the metal bump 50 is electrically connected to the metal layer 30 and further electrically connected to the pad 120, and when electroplating is performed, the height of the metal bump 50 formed by electroplating is controlled to be lower than the depth of the first opening, so as to prevent metal from attaching to a side surface of the second photoresist 40 away from the driving chip 12.
Further, the material of the second sub-metal layer 302 is the same as the material of the metal bump 50. The second sub-metal layer 302 and the metal bump 50 are made of the same material, so as to improve the bonding force between the metal bump 50 and the metal layer 30, and to make the connection between the metal bump 50 and the metal layer 30 more reliable. When the metal bump 50 is a gold bump, the material of the second sub-metal layer 302 is gold, and when the metal bump 50 is a copper bump, the material of the second sub-metal layer 302 is copper.
Because the electroplating is performed in a uniform electroplating manner, when the metal layer 30 has a small gap at a position corresponding to the pad 120, the metal bump 50 also has a small gap at a position corresponding to the pad 120. Further, after step S303, the method further includes: and forming a metal planarization layer 52 on the surface of the metal bump 50 away from the pad 120, wherein the surface of the metal planarization layer 52 away from the pad 120 is flat.
Specifically, referring to fig. 7d, fig. 7d is a schematic cross-sectional structure view of an embodiment corresponding to the step S303 in fig. 6, a surface of the metal bump 50 away from the pad 120 is further plated to form a metal planarization layer 52, so that the metal bump 50 can be electrically connected to other electrical elements, thereby improving the stability of the packaged driver chip 12.
In other embodiments, the second photoresist 40 may be removed first, and then the surface of the metal bump 50 away from the pad 120 is polished, and a planarization process is performed on the surface of the metal bump 50 to form the metal planarization layer 52, which is not limited in this application.
Step S104: and removing the protective layer and the metal layer on the surface of the protective layer.
Specifically, please refer to fig. 8, wherein fig. 8 is a schematic cross-sectional structure diagram of an embodiment corresponding to step S104 in fig. 1, and refer to fig. 7c in combination. Wherein, the first photoresist 20 and the second photoresist 40 are both negative photoresist, and after the metal bump 50 is formed in the first opening, the method further includes: the second photoresist 40 on both sides of the metal bump 50 is removed by using a photoresist remover, and the passivation layer 16 wrapped by the second photoresist 40 and the metal layer 30 covering the passivation layer 16 are removed together with the second photoresist 40.
Specifically, when the second photoresist 40 is removed by using the photoresist remover, the protective layer 16 is completely wrapped by the second photoresist 40, and the properties of the first photoresist 20 and the second photoresist 40 forming the protective layer 16 are the same, the same photoresist remover can remove the second photoresist 40 and the protective layer 16 together, the metal layer 30 on the protective layer 16 is interposed between the protective layer 16 and the second photoresist 40, when the protective layer 16 and the second photoresist 40 are peeled off from the side away from the functional surface of the driver chip 12, the metal layer 30 on the protective layer 16 is removed together in the second photoresist 40, no metal residue is left in the trench circuit region 14, and only the metal bump 50 and the metal layer 30 at the position corresponding to the pad 120 at the two sides of the metal bump 50 are remained.
Further, the orthographic projection of the protective layer 16 on the functional surface is larger than that of the end thereof in contact with the functional surface.
In a specific application scenario, when the size of the end of the protective layer 16 close to the functional surface is gradually reduced along the direction close to the functional surface, a structure with a wide top and a narrow bottom exists on the protective layer 16. After the protective layer 16 is wrapped by the second photoresist 40, the protective layer 16 is bonded to the second photoresist 40 more tightly along the direction from the functional surface of the driver chip 12 to the direction away from the functional surface, and the protective layer 16 is more easily peeled off from the functional surface of the driver chip 12 together when the second photoresist 40 is removed.
In another specific application scenario, when the vertical cross section of the protection layer 16 is an inverted trapezoid, the width of the structure of the protection layer 16 gradually increases from the functional surface to the direction away from the functional surface, so that the protection layer 16 is embedded in the second photoresist 40 and tightly bonded to the second photoresist 40, when the second photoresist 40 is removed by using the photoresist remover, the second photoresist 40 on both sides of one end of the protection layer 16 close to the functional surface holds the protection layer 16, and further when the second photoresist 40 is removed, the protection layer 16 is peeled off from the functional surface by the second photoresist 40.
Step S105: and removing the metal layer which is not covered by the metal bump around the metal bump.
Specifically, referring to fig. 9, fig. 9 is a schematic cross-sectional structure diagram of an embodiment corresponding to step S105 in fig. 1, and referring to fig. 8, the second sub-metal layer 302 and the first sub-metal layer 300, which are not covered by the metal bump 50, around the metal bump 50 are etched respectively, only the metal layer 30 on the side of the metal bump 50 close to the functional surface of the driver chip 12 is remained, so as to reduce metal residue on the functional surface of the driver chip 12, further reduce the probability of short circuit of the circuit on the driver chip 12, and improve the reliability of the driver chip 12. The pad 120 is electrically connected to the metal bump 50 through the metal layer 30, and the metal bump 50 can be electrically connected to other electrical components, thereby increasing the area of the pad 120 electrically connected to other electrical components.
It should be noted that all the drawings in the present application are only illustrated by one driver chip 12, and in practical applications, the metal bump 50 may be formed on a wafer according to the above method, where the wafer includes a plurality of driver chips 12, and the metal bumps 50 corresponding to the bonding pads 120 are formed on all the driver chips 12 on the wafer, so as to improve the efficiency of forming the metal bumps 50 and save the cost.
In summary, the protection layer 16 is disposed in the trench circuit area 14 on one side of the functional surface of the driving chip 12, and then when the metal layer 30 and the metal bump 50 are formed subsequently, no metal remains in the trench circuit area 14, thereby avoiding a short circuit of the driving chip 12 caused by the electrical connection between the trench circuit area 14 and the remaining metal, and improving the reliability of the driving chip 12, and the orthographic projection of the protection layer 16 on the functional surface is larger than the orthographic projection of the end of the protection layer 16 contacting the functional surface on the functional surface, which can make the metal layer 30 formed on one side of the functional surface and the protection layer 16 away from the functional surface have the gap 304 between the metal layer 30 on the functional surface and the end of the protection layer 16, and the protection layer 16 and the metal layer 30 above can be removed more easily subsequently, without affecting the metal layer 30 on the functional surface. Moreover, when the protective layer 16 is subsequently removed, the second photoresist 40 completely wraps the protective layer 16, and since the width of the side of the protective layer 16 away from the functional surface is larger than the side contacting with the functional surface, the protective layer 16 and the second photoresist 40 are combined more tightly, the protective layer 16 can be stripped from the functional surface when the second photoresist 40 is removed, so that the protective layer 16 is more convenient to remove, and the functional surface of the driving chip 12 cannot be damaged.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method for preparing a bump on a driving chip is characterized by comprising the following steps:
forming a removable protective layer on the surface of a groove circuit area on a functional surface of a driving chip, wherein at least one pad around the groove circuit area is exposed out of the protective layer, and the orthographic projection of the protective layer on the functional surface is larger than that of one end of the protective layer, which is in contact with the functional surface, on the functional surface;
forming metal layers on the functional surface and one side, far away from the functional surface, of the protective layer, wherein a gap is formed between the metal layer on the functional surface and the metal layer on the protective layer;
respectively forming a metal bump at each bonding pad position;
removing the protective layer and the metal layer on the surface of the protective layer;
and removing the metal layer which is not covered by the metal bump around the metal bump.
2. The production method according to claim 1,
the size of one end of the protective layer close to the functional surface is gradually reduced along the direction close to the functional surface.
3. The production method according to claim 2,
the vertical section of the protective layer is in an inverted trapezoid shape.
4. The method according to claim 1, wherein forming a removable protective layer on the surface of the trench circuit region on the functional surface of the driver chip comprises:
forming a first photoresist on one side of the functional surface of the driving chip;
and removing part of the first photoresist, and only remaining the first photoresist at the position corresponding to the groove circuit area so as to form the protective layer at the position corresponding to the groove circuit area.
5. The method of claim 4, wherein the forming a metal bump at each of the pad locations respectively comprises:
forming a second photoresist on one side of the metal layer, wherein the second photoresist covers one side of the protective layer far away from the functional surface and the side surface of the protective layer;
forming a first opening on the second photoresist corresponding to the position of the bonding pad; the second photoresist reserved on two sides of the first opening covers two sides of the protective layer and the metal layer on the surface of the protective layer;
and forming the metal bump in the first opening by electroplating, wherein the metal bump is electrically connected with the bonding pad.
6. The production method according to claim 5,
the first photoresist and the second photoresist are both negative photoresist, and after the metal bump is formed in the first opening, the method further includes:
and removing the second photoresist on two sides of the metal bump by using a photoresist remover, and removing the protective layer wrapped by the second photoresist and the metal layer covered on the protective layer together with the second photoresist.
7. The method as claimed in claim 5, wherein the step of forming the metal bump in the first opening by electroplating further comprises:
and forming a metal planarization layer on the surface of the metal bump, which is far away from the pad, wherein the surface of one side of the metal planarization layer, which is far away from the pad, is smooth.
8. The method according to claim 1, wherein the forming of the metal layer on the functional surface and the side of the protective layer away from the functional surface comprises:
forming a first sub-metal layer on the functional surface and on one side, far away from the functional surface, of the protective layer, and a gap is formed between the first sub-metal layer on the functional surface and the first sub-metal layer on the protective layer;
and forming a second sub-metal layer on the first sub-metal layer.
9. The method according to claim 8,
the first sub-metal layer and the second sub-metal layer are made of different materials, and the hardness of the first sub-metal layer is larger than that of the second sub-metal layer.
10. The method according to claim 8,
the material of the second sub-metal layer is the same as that of the metal bump.
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| CN202010514199.5A CN111640683B (en) | 2020-06-08 | 2020-06-08 | Method for preparing lug on driving chip |
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| CN202010514199.5A CN111640683B (en) | 2020-06-08 | 2020-06-08 | Method for preparing lug on driving chip |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS63177540A (en) * | 1987-01-19 | 1988-07-21 | Nec Corp | Manufacture of semiconductor device |
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| JP4074721B2 (en) * | 1999-02-23 | 2008-04-09 | ローム株式会社 | Semiconductor chip and method for manufacturing semiconductor chip |
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