CN100580914C - Packaging conductive structure and its forming method - Google Patents
Packaging conductive structure and its forming method Download PDFInfo
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- CN100580914C CN100580914C CN200710084092A CN200710084092A CN100580914C CN 100580914 C CN100580914 C CN 100580914C CN 200710084092 A CN200710084092 A CN 200710084092A CN 200710084092 A CN200710084092 A CN 200710084092A CN 100580914 C CN100580914 C CN 100580914C
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- layer
- projection
- accommodation space
- conductive structure
- packaging
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 title claims description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 230000004308 accommodation Effects 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 151
- 239000011241 protective layer Substances 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- 229910001080 W alloy Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 6
- 230000003028 elevating effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to an encapsulated conducting structure for a semiconductor substrate and the forming method thereof. The dielectric layer of the encapsulated conducting structure is locally covered with the metal layer of the semiconductor substrate, and defines an accommodation space with an elevating layer and a conducting layer inside, the conducting layer stretches to connect with a bump, and the elevating layer is connected with a dielectric layer , so that the deposition of the edge of the dielectric layer is stabilized, and thus improving the reliability of the encapsulated conducting structure.
Description
Technical field
The invention relates to a kind of packaging conductive structure that is used for semiconductor substrate; Particularly a kind of packaging conductive structure with redistribution layer.
Background technology
In the electronic product now, having semiconductor chip usually provides control or logical operation function, because the continuous progress of technology, semiconductor chip is miniaturization day by day, and package dimension also dwindles gradually.
Tradition engages (Wire Bonding) mode with routing, with the Electronic Packaging technology that semiconductor chip engages with other elements, does not apply demand already, the substitute is the chip bonding technology that engages with other elements as chip with projection (Bumps).In other words, be provided with a plurality of projections on semiconductor chip surface, itself and internal structure electrically conduct, and in order to engage with other elements, can save traditional bonding wire and occupy the larger area shortcoming, are applicable to advanced technology.
In addition, existing encapsulation technology also adopts and has redistribution layer (redistribution layer, design RDL).Because it is to be formed at the integrated circuit outside that the liner on the chip distributes, be its restriction, projection is if directly be formed on the liner, and the projection number that then can hold is limited, and the spacing between the projection also can be limited, easily causes defectives such as the joint of projection is bad when reality is used.Redistribution layer adopts a mode that electrically connects indirectly, connects chip pad and projection by conductive layer, so the position of projection can be according to the demand setting, and then reconfigures, need not be confined to existing pad position, can increase the elasticity in the use.
Specifically, existing encapsulating structure with redistribution layer as shown in Figure 1, semiconductor chip 10 is included in has metal level 111 on the base material 11, be liner (pad), as internal semiconductor structure and the extraneous contact that electrically conducts.Have dielectric layer 13 on the base material 11, the periphery of covered with metal layer 111, and part metals layer 111 is come out.Subsequently, form redistribution layer 15, it comprises depositing conducting layer 151 and protective layer 153; and on the position of desire formation projection, form guide hole; (under bumpmetallization UBM) after 17, forms projection 19 at last again to form the projection lower metal layer in the guide hole.Wherein, the projection lower metal layer is the multiple layer metal film that utilizes titanium, chromium, copper, gold etc., and major function provides when electrically conducting, and also takes into account the lifting of projection adhesive force, guarantees projection 19 and conductive layer 151 stable engagement.By said structure, projection 19 can with metal level 111 conductings of base material 11, and locational skew can be arranged, more flexible application when reaching chip bonding.
Yet, in forming the process of conductive layer 151,, therefore on the sidewall locations of dielectric layer 13, form the conductive layer of adequate thickness because conductive layer deposition is to be unidirectional deposition, truly have difficulty, have and cause the risk that opens circuit easily.Shown in the dotted line position of Fig. 1, near the partially conductive layer 151 the sidewall of dielectric layer 13 because of comparatively difficult on the deposition, in case improper process control very likely can cause opening circuit, causes semiconductor chip failure.
In view of this, in the semiconductor structure with redistribution layer, providing one can guarantee the packaging conductive structure that electrically conducts, is an industry problem demanding prompt solution for this reason.
Summary of the invention
A purpose of the present invention is to provide a kind of packaging conductive structure that is used for semiconductor substrate, especially be applied to have redistribution layer (redistribution layer, RDL) encapsulating structure, extension design by conductive layer, bump position can be reconfigured according to demand, promote the elasticity of semiconductor chip when covering crystalline substance.
Another object of the present invention is to provide a kind of packaging conductive structure, the design that has the bed hedgehopping layer in the packaging conductive structure, make it when depositing conducting layer, be easier to form, especially can improve on the deposition effect on the dielectric layer sidewall, avoid formation to open circuit and cause losing efficacy, and then promote the encapsulation reliability of semiconductor chip.
Another purpose of the present invention is to provide a kind of packaging conductive structure, and the metal layer contacting conducting of its conductive layer bottom surface and semiconductor substrate, and the design of bed hedgehopping layer make that conductive layer is easier to form at least on a direction, guarantee and projection between electrically conduct.
For reaching above-mentioned purpose, the present invention discloses a kind of packaging conductive structure that is used for semiconductor substrate, has a metal level on the semiconductor substrate, and this packaging conductive structure forms a dielectric layer on semiconductor substrate, cover this metal level with the part, and define an accommodation space; This packaging conductive structure also comprises a bed hedgehopping layer and a conductive layer in accommodation space, the bed hedgehopping layer segment is connected in dielectric layer, and the metal level of conductive layer and semiconductor substrate is electric connection, and the local at least edge that covers dielectric layer.
The present invention also discloses a kind of method that forms above-mentioned packaging conductive structure, comprises the following step: (a) form local this metal level that covers of dielectric layer on semiconductor substrate, to define an accommodation space; (b) form a bed hedgehopping layer in accommodation space, with this metal level of cover part, and part is connected in this dielectric layer; Reach and (c) in this accommodation space, form a conductive layer, can pass through this accommodation space, be electric connection with this metal level so that this conductive layer is suitable.
For above-mentioned purpose of the present invention, technical characterictic and advantage can be become apparent, will be elaborated with the preferred embodiment conjunction with figs. below.
Description of drawings
Fig. 1 is the schematic diagram of existing packaging conductive structure;
Fig. 2 A is in the packaging conductive structure of the present invention, forms the schematic diagram of accommodation space;
Fig. 2 B is in the packaging conductive structure of the present invention, forms the schematic diagram of bed hedgehopping layer;
Fig. 2 C is the top view of packaging conductive structure of the present invention;
Fig. 2 D is in the packaging conductive structure of the present invention, forms the schematic diagram of bed hedgehopping layer;
Fig. 2 E is in the packaging conductive structure of the present invention, forms the schematic diagram of bed hedgehopping layer;
Fig. 3 A is in the packaging conductive structure of the present invention, forms the schematic diagram of conductive layer;
Fig. 3 B is in the packaging conductive structure of the present invention, the end view of bed hedgehopping layer and conductive layer; And
Fig. 4 is the schematic diagram of packaging conductive structure of the present invention.
Embodiment
Please consult Fig. 2 A earlier, packaging conductive structure 30 of the present invention is applied to semiconductor substrate 20, and semiconductor substrate 20 has metal level 21 usually, is liner (pad), with the contact as electric connection.Generally speaking, metal level 21 is made by aluminium usually, after packaging conductive structure 30 of the present invention combines, just can carry out follow-up electrical the joint with outside other elements.
At first, on semiconductor substrate 20, form a dielectric layer 31, its local covering metal level 21, and define an accommodation space, metal level 21 can partly be come out.More clearly say, can form a dielectric material earlier in large area, part forms a photoresist layer (not shown) thereon again, then carries out an etching work procedure and not removed by the part dielectric layer of photoresist layer covering, just can form this accommodation space.
Next see also Fig. 2 B, prior to forming bed hedgehopping layer 51 in the accommodation space, this bed hedgehopping layer 51 can by polyimides (Polyimide, PI) or oxide made, its production method can adopt the technology of exposure imaging, utilizes light shield 41 that photoresistance is patterned in the accommodation space.Top view is shown in Fig. 2 C, can more clearly show the corresponding relation of bed hedgehopping layer 51 in accommodation space, the invention is characterized in, the metal level 21 of bed hedgehopping layer 51 cover part, and have two opposite end portions, part is connected in the sidewall of dielectric layer 31, and two opposite side faces of bed hedgehopping layer 51 and dielectric layer 31 intervals.
What must illustrate is, the size and the quantity of bed hedgehopping layer 51 do not limit at this, for example, suppose that accommodation space has the first longitudinal size D (being the degree of depth of accommodation space), the bed hedgehopping layer has the second longitudinal size H (being the height of bed hedgehopping layer 51), in a preferred embodiment, the second longitudinal size H is at least half of the first longitudinal size D; Perhaps, the second longitudinal size H equates (being the deep equality of the height and the accommodation space of bed hedgehopping layer 51) with the first longitudinal size D, bed hedgehopping layer 51 size between this scope, all can reach the present invention significantly the effect desiring to reach.
Next can form re-distribution layer, see also Fig. 3 A (being depicted as the schematic diagram of Fig. 2 C), at first form a conductive layer 33 on aforesaid structure, electrically connect to form with the part metals layer 21 that is not subjected to 51 covering of bed hedgehopping layer along hatching 3A-3A ' direction.Can consult Fig. 3 B in the lump, it is that significantly, the top of bed hedgehopping layer 51 is shorter apart from the edge of dielectric layer 31, helps the formation of conductive layer 33 along the end view (being the schematic diagram of Fig. 2 C along hatching 3B-3B ' direction) of the longitudinal direction of bed hedgehopping layer 51.
More particularly, can further define conductive layer 33 and have a middle section 331 and a peripheral edge margin 333.Wherein, middle section 331 is meant the partially conductive layer 33 that is formed in the accommodation space, and it covers bed hedgehopping layer 51, and is electric connection with the metal level 21 that partly exposes; The then local at least edge that is covered in dielectric layer 31 of peripheral edge margin 333.
Setting by bed hedgehopping layer 51, the distance on dielectric layer 31 sidewall edge and bed hedgehopping layer 51 top, distance compared to dielectric layer 31 sidewall edge and metal level 21 furthers many, efficiently solve the difficulty of depositing conducting layer 33 on dielectric layer 31 sidewall edge positions, guarantee that conductive layer 33 does not open circuit along not forming on the longitudinal direction of bed hedgehopping layer 51, to promote the reliability of its packaging conductive structure.
As shown in Figure 4, can form a protective layer 35 then, be covered on the conductive layer 33.Next, in the appropriate location of conductive layer 33 peripheral edge margin, and on protective layer 35, can form a projection accommodation space, with expose portion conductive layer 33.In this projection accommodation space, at first form projection lower metal layer 37, electrically connect with conductive layer 33, projection lower metal layer 37 is made by titanium/tungsten alloy usually, can provide a preferable adhesion effect when having conducting function.Preferably can on projection lower metal layer 37, form a projection conductive layer 38 again, for example be made of gold, to promote its electric conductivity.At last, on aforementioned structure, form projection 39 again, projection 39 suitable can electric connections with conductive layer 33 by projection lower metal layer 37 and the projection conductive layer 38 in the projection accommodation space.
Projection lower metal layer 37 and projection conductive layer 38 by 33 of projection 39 and conductive layers, projection 39 can be smoothly and conductive layer 33 (especially middle section 331) electrically connect, and then with metal level 21 conductings of semiconductor substrate 20, and have stronger adhesion effect.
By above-mentioned announcement, packaging conductive structure 30 of the present invention utilizes the design of bed hedgehopping layer 51, makes conductive layer 33 comparatively stable in the deposition of the sidewall edge position of dielectric layer 31, and then improves the reliability of packaging conductive structure 30.
The above embodiments only are used for exemplifying enforcement aspect of the present invention, and explain technical characterictic of the present invention, are not to be used for limiting protection category of the present invention.Any be familiar with this operator can unlabored change or the arrangement of the isotropism scope that all belongs to the present invention and advocated, the scope of the present invention should be as the criterion with the application's claim scope.
Claims (21)
1. a packaging conductive structure that is used for semiconductor substrate comprises a metal level on this semiconductor substrate, and this packaging conductive structure comprises:
One dielectric layer is formed on this semiconductor substrate, and local this metal level that covers of this dielectric layer is to define an accommodation space;
One bed hedgehopping layer is formed in this accommodation space, and wherein this bed hedgehopping layer is connected in this dielectric layer with two opposite end portions, and two opposite side faces of this bed hedgehopping layer and this dielectric layer interval; And
One conductive layer has a middle section and a peripheral edge margin; It is characterized in that this middle section is formed in this accommodation space, be electric connection, the local at least edge that covers this dielectric layer of this peripheral edge margin with this metal level.
2. packaging conductive structure as claimed in claim 1 is characterized in that also comprising a projection, and the middle section with this conductive layer is electrical connected at least.
3. packaging conductive structure as claimed in claim 1 is characterized in that also comprising a projection and a protective layer, is covered on the peripheral edge margin of this conductive layer, defines a projection accommodation space in this protective layer; Wherein this projection electrically connects by this projection accommodation space and this conductive layer.
4. packaging conductive structure as claimed in claim 3 is characterized in that also comprising a projection lower metal layer and is formed between this projection and this conductive layer.
5. packaging conductive structure as claimed in claim 4 is characterized in that this projection lower metal layer is made by titanium/tungsten alloy.
6. packaging conductive structure as claimed in claim 4 is characterized in that also comprising a projection conductive layer, is formed between this projection and this projection lower metal layer.
7. packaging conductive structure as claimed in claim 6 is characterized in that this projection conductive layer is made by gold.
8. packaging conductive structure as claimed in claim 1 is characterized in that this bed hedgehopping layer is made by polyimides or oxide.
9. packaging conductive structure as claimed in claim 1 is characterized in that this metal level is made of aluminum.
10. packaging conductive structure as claimed in claim 1 is characterized in that this accommodation space has one first longitudinal size, and this bed hedgehopping layer has one second longitudinal size, and this second longitudinal size is at least half of this first longitudinal size.
11. packaging conductive structure as claimed in claim 10 is characterized in that this first longitudinal size equates with this second longitudinal size.
12. a method that forms packaging conductive structure on the semiconductor base material, this semiconductor substrate comprises a metal level, and this method comprises the following step:
(a) form a dielectric layer on this semiconductor substrate, local this metal level that covers is to define an accommodation space;
(b) form a bed hedgehopping layer in this accommodation space, with this metal level of cover part, wherein this bed hedgehopping layer is connected in this dielectric layer with two opposite end portions, and two opposite side faces of this bed hedgehopping layer and this dielectric layer interval; And
(c) form a conductive layer in this accommodation space, can pass through this accommodation space, be electric connection with this metal level so that this conductive layer is suitable.
13. method as claimed in claim 12 is characterized in that this step (a) comprises:
Form a photoresist layer; And
Carry out an etching work procedure.
14. method as claimed in claim 12 is characterized in that this step (b) comprises:
Carry out an exposure process, with local this bed hedgehopping layer that forms on this metal level; And
Carry out a heating process at this bed hedgehopping layer, this bed hedgehopping layer is solidified.
15. method as claimed in claim 14 is characterized in that also comprising and carries out a plasma treatment process, to remove the residue in this accommodation space.
16. method as claimed in claim 12 is characterized in that also comprising:
Form a protective layer, be covered on this conductive layer.
17. method as claimed in claim 16 is characterized in that also comprising the following step:
On this protective layer, form a projection accommodation space, with this conductive layer of expose portion; And
In this projection accommodation space, form a projection, can electrically connect by this projection accommodation space and this conductive layer so that this projection is suitable.
18. method as claimed in claim 17 before it is characterized in that forming this projection step and implementing, also comprises:
In this projection accommodation space, form a projection lower metal layer, can electrically connect by this projection lower metal layer and this conductive layer so that this projection is suitable.
19. method as claimed in claim 18 is characterized in that this projection lower metal layer is made by titanium/tungsten alloy.
20. method as claimed in claim 18, it is characterized in that forming after the step of this projection lower metal layer, also comprise formation one projection conductive layer on this projection lower metal layer, can be so that this projection is suitable by this projection conductive layer and this projection lower metal layer and the electric connection of this conductive layer.
21. method as claimed in claim 20 is characterized in that this projection conductive layer is to be made of gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710084092A CN100580914C (en) | 2007-02-16 | 2007-02-16 | Packaging conductive structure and its forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710084092A CN100580914C (en) | 2007-02-16 | 2007-02-16 | Packaging conductive structure and its forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101246864A CN101246864A (en) | 2008-08-20 |
| CN100580914C true CN100580914C (en) | 2010-01-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710084092A Active CN100580914C (en) | 2007-02-16 | 2007-02-16 | Packaging conductive structure and its forming method |
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| Country | Link |
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| CN (1) | CN100580914C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10464836B2 (en) | 2013-10-10 | 2019-11-05 | Medtronic, Inc. | Hermetic conductive feedthroughs for a semiconductor wafer |
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- 2007-02-16 CN CN200710084092A patent/CN100580914C/en active Active
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| Publication number | Publication date |
|---|---|
| CN101246864A (en) | 2008-08-20 |
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