CN111625075A - Software configurable reset device and method - Google Patents
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Abstract
The embodiment of the application discloses a software configurable reset device and a software configurable reset method, which are used for resetting a chip. The reset device comprises a configurable reset state machine and a configurable reset condition register, wherein the reset state machine is configured to perform state skipping according to the sequence specified by the configurable reset condition register, and when the reset condition is met, the reset device generates reset output in the corresponding state according to the state skipping sequence and controls modules in the chip to complete reset operation in sequence. The present disclosure can implement different reset sequences and functions by configuring the reset device. The reset device has the characteristics of configurability, expandability and adjustability, and overcomes the defect that in the chip reset design, the conditions of reset source, reset state and reset state switching can only be designed specifically and cannot be suitable for flexible configuration of software as required.
Description
Technical Field
The present disclosure relates to the field of digital integrated circuit technologies, and in particular, to a software configurable reset apparatus and method.
Background
The reset module is used as the main part of the chip and is mainly used for generating the reset required by different logics of the whole chip. The reset operation ensures normal power-on initialization of the chip, and can restore the chip or a module inside the chip to an initial state when the chip or the module inside the chip is abnormal, so as to ensure that the chip or a functional module inside the chip is in a determined state.
The main functions of reset include:
1. state initialization
The state initialization of the whole chip is carried out when the chip is powered on through resetting, wherein the state initialization comprises the steps that each time sequence logic and a state machine are placed in a determined state, and all registers are placed in default values.
2. Recovery from failure or abnormality
The recovery processing when the chip or the internal module is in failure or abnormal is completed by resetting and reinitializing the whole chip or the failed module to recover the error state.
3. Meet the specific protocol requirements in the chip
The protocol implemented in the chip requires that a corresponding reset operation be triggered.
4. Necessary operation of mode switching
When the mode switching needs to be performed in the chip, a reset needs to be performed to validate the parameter switching.
5. Auxiliary means for debugging
In the debugging process of the chip, the aim of positioning faults and the like is fulfilled through the reset part module.
Referring to fig. 1, in a conventional full-chip reset design, a common method is to design a global reset module and a reset logic in a chip internal function module by using a two-stage reset structure. According to design intention, the chip global reset or the chip internal module logic independent reset can be completed. The reset logic in the internal module is matched with the global reset module to realize the special reset requirement required in the design. The chip will operate according to the principle of resetting simultaneously and releasing in sequence, namely: all modules in the chip are reset simultaneously and enter a reset state, and then reset release is carried out in sequence according to time sequence, so that all the modules enter a normal operation state in sequence according to the sequence of reset release.
In the conventional reset design, the reset releases of different functional modules in the chip have an interdependent sequence relationship. The reset signal output of different modules and the order relation with other reset signals need to design a specific reset sequence, and the specific reset signal is processed, so that the reset sequence and the reset output signal solidification can not be adjusted after the reset design is finished, and the method is not suitable for the development trend of current reuse design concept and agile development.
A conventional reset process is shown in fig. 2, and according to design requirements, the reset of the module 1, the module 2, and the module 3 is output by global reset; the module 1 and the module 2 are designed to have respective reset processing inside so as to reset and output respective sub-modules. After the whole reset flow design is completed, circulation is carried out according to the sequence, and the reset sequence among the modules is strictly executed according to the whole design scheme. This requires that the inter-module reset sequence must be clearly defined at the beginning of the overall design, otherwise, the reset output sequence is not matched with the inter-module reset requirement, and the entire design is abnormal and cannot enter a definite working state. In addition, when the requirement of adjusting the reset sequence among the modules occurs after the traditional reset design is finished, the reset needs to be redesigned, so that the development progress returns; the design adjustment of resetting can involve the design adjustment of many modules, in case design intention interactive deviation appears, will lead to the design of resetting to mismatch with the demand, the unable normal work of chip appears, leads to the design failure.
Disclosure of Invention
An object of the disclosed embodiment is to provide a software configurable reset device, which is used for solving the problem that the reset design solidification can not be adjusted in the prior art. It is also an object of embodiments of the present disclosure to provide a corresponding software configurable reset method.
The technical scheme adopted by the disclosed embodiment to achieve the purpose is as follows.
In a first aspect, a software configurable reset device is provided, configured to reset a chip, where the reset device includes a reset state machine and a configurable reset condition register, where the reset state machine is configured to perform state skipping according to an order specified by the configurable reset condition register, and when a reset condition is met, the reset device generates a reset output in a corresponding state according to the state skipping order, and controls modules inside the chip to complete reset operations in order.
In some embodiments, the reset state machine has at least two states, each state correspondingly controls at least one path of reset output signal, and the reset output signal is used for controlling the reset operation of at least one module in the chip; the reset device further comprises a configuration interface, the configuration interface is used for configuring the value of the configurable reset condition register, and the configuration value of the configurable reset condition register is used for indicating the state jump condition of the reset state machine, so that the reset state machine performs state jump according to a specified order; the reset state machine is used for reading the configuration value of the configurable reset condition register, starting when the reset condition is judged to be met, outputting at least two paths of reset output signals, performing state skipping according to the sequence specified by the configuration value, sequentially releasing the at least two paths of reset output signals according to the state skipping sequence, and controlling the modules in the chip to complete reset operation according to the sequence.
As described above, the configuration interface may be configured to configure a reset state jump condition, where the reset state jump condition is used to indicate a jump state order of the reset state machine, and complete an operation of changing a flow order of the state machine. Further, the configuration interface is also used for configuring the output signal state of the reset device. Furthermore, the configuration interface can also simultaneously configure the conversion between the number of the reset output signals and the high and low output levels.
In some embodiments, the configurable reset condition register comprises an enable register and a plurality of condition registers; and the reset state machine is specifically configured to: in the initial state, judging whether to start according to the configuration value of the start register; starting the system, switching to a first state, and judging whether to jump to another state in the first state according to the configuration value of the corresponding condition register; if the jump is to the other state, judging whether to continue the jump or not in the other state according to the value of the corresponding condition register; when the previous state jumps to the next state, the reset output signal corresponding to the previous state is released, so that the corresponding module completes the reset operation.
In some embodiments, the chip is an Application Specific Integrated Circuit (ASIC) chip or a Field Programmable Gate Array (FPGA) chip.
In a second aspect, a software configurable reset method is provided, which is applied to a reset device to reset a chip, where the reset device includes a reset state machine and a configurable reset condition register, and the method includes:
step S1: a reset state machine of the reset device is configured to perform state jumps in an order specified by the configurable reset condition register configuration values;
step S2: when the reset condition is met, the reset device generates reset output in the corresponding state according to the state jump sequence, for example, generates reset output in the corresponding state according to the configuration content of a reset output state register, and controls the modules in the chip to complete the reset operation in sequence.
In some embodiments, the reset state machine has at least two states, each state correspondingly controls at least one path of reset output signal, and the reset output signal is used for controlling the reset operation of at least one module in the chip; the reset device further comprises a configuration interface; step S1 specifically includes: the configuration interface configures the value of the configurable reset condition register, and the configured value of the configurable reset condition register is used for indicating the state jump condition of the reset state machine, so that the reset state machine performs state jump according to a specified sequence; step S2 specifically includes: and the reset state machine reads the configuration value of the configurable reset condition register, starts when the reset condition is judged to be met, outputs at least two paths of reset output signals, performs state skipping according to the sequence specified by the configuration value, sequentially releases the at least two paths of reset output signals according to the state skipping sequence, and controls the modules in the chip to complete reset operation in sequence.
In some embodiments, the configurable reset condition register comprises a start register and a plurality of condition registers, the plurality of registers corresponding to a plurality of states of the reset state machine, respectively; step S2 specifically includes: the reset state machine judges whether to start or not according to the configuration value of the starting register in an initial state; starting the system, switching to a first state, and judging whether to jump to another state in the first state according to the configuration value of the corresponding condition register; if the jump is to the other state, judging whether the jump is continued in the other state according to the value of the corresponding condition register until the jump of all the states is completed; when the previous state jumps to the next state, the reset output signal corresponding to the previous state is released, so that the corresponding module completes the reset operation.
In some embodiments, the chip is an Application Specific Integrated Circuit (ASIC) chip or a Field Programmable Gate Array (FPGA) chip.
According to the technical scheme, the embodiment of the disclosure achieves the following technical effects:
the software configurable reset device disclosed by the invention is a general module based on a state machine, comprises a reset state machine and a configurable reset condition register, and can realize different reset functions through software configuration, so that the reset device controls the reset sequence of the internal modules of the chip according to the configured sequence. The reset device has the characteristics of configurable, expandable and adjustable mechanism, and overcomes the defect that in the chip reset design, the conditions of reset source, reset state and reset state switching can only be designed specifically and cannot be suitable for flexible configuration of software according to the requirement.
In the implementation manner of the embodiment of the present disclosure, the conventional reset flow is changed into a Finite State Machine (FSM) that can be configured by software, and the jump condition, the jump state, and the jump result in the conventional reset flow are implemented by using configurable registers, respectively. Therefore, the problems of reset sequence adjustment, reset output control and reset debugging are fundamentally solved, the reset design becomes a reusable design, software configuration can be carried out according to different use requirements, the design period is further saved, and the gap between the design intention and the realization is shortened.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the embodiments and the drawings used in the description of the prior art.
FIG. 1 is a schematic diagram of a two-stage reset architecture employed by a conventional reset module design;
FIG. 2 is a schematic diagram of a conventional reset procedure;
FIG. 3 is a schematic structural diagram of a software configurable reset device according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a reset state machine in one embodiment of the present disclosure;
FIG. 5 is a jump flow diagram of a reset state machine in one embodiment of the present disclosure;
FIG. 6 is a jump flow diagram of a reset state machine in an example first of the present disclosure;
FIG. 7 is a jump flow diagram of a reset state machine in example two of the present disclosure;
fig. 8 is a flowchart illustrating a software configurable reset method according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present disclosure better understood by those skilled in the art, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
The terms "first," "second," "third," and the like in the description and claims of the present disclosure and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
The following will explain details by way of specific examples.
Referring to fig. 3, in one embodiment of the present disclosure, a software configurable reset device 10 is provided. The resetting device 10 is used for resetting the chip. Here, the chip is, for example, an Application Specific Integrated Circuit (ASIC) chip or a Field Programmable Gate Array (FPGA) chip.
As shown in fig. 3, the reset device 10 is a state machine based reset device, which includes a reset state machine 13 therein. The reset State Machine 13 may be a Finite State Machine (FSM). The FSM may be a control center that is configured by a unit such as a logic circuit, can perform state transition according to a preset state based on a control signal, and coordinates a relevant signal operation to complete a specific operation.
In the embodiment of the present disclosure, the reset device 10 may be configured by software, such that the reset state machine 13 is configured to jump states in a preset order, that is, to jump states among a plurality of states in a preset order. When the chip meets the reset condition, the reset device 10 can generate reset output according to the state jump sequence, and control the modules in the chip to complete the reset operation in sequence.
Generally, the reset operation of a certain module inside a chip may include the following processes: when the reset is started, outputting a reset output signal to the module; resetting release, namely releasing a reset output signal, and after the reset output signal of the module disappears, the module enters a determined state to complete the resetting operation; wherein after the reset is started, the module is kept in the reset state before the reset output signal is released, and the module is still in an uncertain state at the moment.
As shown in fig. 3, in some embodiments of the present disclosure, the resetting device 10 may specifically include: a configuration interface 11, a configurable reset condition register and a reset state machine 13. The configurable reset condition register may be a register bank 12 comprising a plurality of registers. The present disclosure should be mainly applied to integrated circuit design, and the configuration interface 11 may be a conventional bus interface, such as a custom local bus (local bus), an Advanced Microcontroller Bus Architecture (AMBA) bus of ARM, or other bus protocols, etc. the register bank 12 may be implemented by using a set of conventional registers, which includes a plurality of registers, the hardware implementation of the reset state machine 13 belongs to the prior art, and is not described herein again.
In the embodiment of the present disclosure, the reset state machine has at least two states and at least two reset outputs, such as the reset outputs 0 to n in fig. 3, where n is a positive integer. Each state corresponds to at least one path of reset output, and outputs a path of reset output signal, wherein the path of reset output signal is used for controlling the reset operation of at least one module in the chip. It should be noted that, at least one reset output corresponding to each state can be understood as: when the reset state machine jumps to the state, the output of the corresponding reset output signal is kept, so that the chip internal module receiving the reset output signal is kept in the reset state; when the reset state machine jumps to other states from the state, the reset output signal corresponding to the state is released, so that the chip internal module receiving the reset output signal enters a determined state along with the disappearance of the reset output signal, the reset operation is completed, and the normal operation can be realized.
In the embodiment of the present disclosure, the configuration interface is configured to acquire a configuration parameter, and configure a value of a register group serving as a configurable reset condition register, where the configuration value of the configurable reset condition register is used to indicate a state jump condition of the reset state machine, so that the reset state machine performs state jump according to a specified order.
In the embodiment of the present disclosure, the register set may include a plurality of registers, and a value of each register is used to indicate a corresponding jump condition. As shown in FIG. 3, the register set includes a start register and a plurality of condition registers 0-m, where m is a positive integer. The configuration parameters, such as 10010, are sequentially stored in a plurality of condition registers, and the assignment of the condition registers is completed, and the configured value of each condition register indicates whether the corresponding condition is valid. The value of the enable register indicates whether the enable condition (i.e., reset condition) is satisfied, and the value of the condition register indicates whether the corresponding jump condition is valid.
In the embodiment of the disclosure, the reset state machine reads the configuration values of the condition registers in the register group. The reset state machine is started when judging that the reset condition (namely the starting condition) is met according to the read configuration value, at least two paths of reset output signals such as n paths are output, n is a positive integer, the state is jumped according to the sequence designated by the configuration value, the at least two paths of reset output signals are sequentially released according to the state jumping sequence, and the modules in the control chip complete the reset operation in sequence.
The specific flow of the reset operation may include: in an initial state, the reset state machine firstly reads a configuration value of the starting register and judges whether the starting is performed, wherein the configuration value of the starting register indicates whether a reset condition is met, such as whether the power is on or not. Generally, a value of 1 may be used to indicate start-up, and a value of 0 may be used to indicate no start-up. If the reset state machine is started, the reset state machine is switched to the first state after being started, and the state 0 is used for representing the first state. Detecting a configuration value in a corresponding condition register in the state 0, and judging whether a corresponding jump condition is met according to whether the value is 1 or not so as to determine whether to jump to another state or not; if the jump is to the other state, judging whether to continue the jump or not in the other state according to the configuration value of the corresponding condition register; thus, jumping between a plurality of states is realized, and optionally, the initial state is finally returned. If the reset state machine is kept in a certain state, the module corresponding to the state is kept in the reset state; and if the previous state jumps to the next state, releasing the reset output signal corresponding to the previous state, so that the corresponding module completes the reset operation and enters a normal running state. Wherein isolation of one or more modules may be achieved by maintaining the modules in a reset state.
FIG. 4 is a logic diagram of a reset state machine in one embodiment. The state machine shown in FIG. 4 includes 7 states, an initial state and states 0-6. It is understood that in practical application design, the number of states is not limited to 7, but can be extended to n (n ≧ 1) states. The state machine shown in fig. 4 is designed with 6 jump conditions, i.e. conditions 0 to 5, for example, condition 0 indicates that condition 0 is detected to be satisfied and is kept in state 0, and condition 3 indicates that condition 0 is detected to be satisfied and is jumped to state 2 when condition 3 is detected to be satisfied.
Referring to fig. 5, it is a schematic diagram of a jump flow of the reset state machine shown in fig. 4 in an application scenario in an embodiment. The jump flow may include the following steps.
a1, judging whether to start in the initial state, if yes, shifting to the state 0, otherwise, keeping in the initial state.
a2, state 0, then detect condition 1 and condition 3, go to state 2 if condition 3 is satisfied, hold state 0 if condition 1 is satisfied, go to state 1 if neither is satisfied. Condition 1 and condition 3 are mutually exclusive conditions.
a3, state 1 is maintained if condition 2 is satisfied in state 1, otherwise state 2 is switched to.
a4, state 2 jumps directly to state 3.
a5, state 3 jumps directly to state 4.
a6, condition 4 is satisfied in state 4 and the transition is back to state 0 otherwise to state 5.
a7, state 5 satisfies condition 5 and goes to state 3, otherwise goes to state 6.
a8, state 6 satisfies condition 0, and goes to state 0, otherwise returns to the initial state.
As above, the present disclosure adjusts the state machine jump order by configuring the condition register contents, enabling reset order changes. Optionally, only a certain jump condition may be configured to implement a reset operation only in a specific state, and the reset state is maintained in other states, thereby implementing operations such as module isolation and debugging.
How the reset state machine is configured is illustrated by a few examples in connection with the state machine shown in fig. 4.
Example one:
the values of the registers in the register bank are configured as follows, and the configuration values of the registers represent corresponding conditions. Here, the condition valid is represented as 1, and the invalid is represented as 0.
Table 1 illustrates a list of configuration values
| Register name | Condition | Configuration value |
| Condition register 0 | Condition 0 | 0 |
| Bar register device 1 | Condition 1 | 0 |
| Condition register 2 | Condition 2 | 0 |
| Condition register 3 | Condition 3 | 1 |
| Condition register 4 | Condition 4 | 0 |
| Condition register 5 | Condition 5 | 0 |
| Start register | Starting conditions | 1 |
The reset state machine jump flow is shown in fig. 6 according to the above configuration.
The condition 3 in the jump flow is valid, and the reset state machine directly jumps from the state 0 to the state 2 after starting and then returns to the initial state after sequentially passing through the state 3, the state 4, the state 5 and the state 6. State 1 does not produce a reset output, implying that the module corresponding to state 1 is either not present in the design or needs to be no longer operational.
Example two:
table 2 example two configuration value list
The reset state machine jump flow is shown in fig. 7 according to the above configuration.
The condition 0 in the jump flow is valid, and the reset state machine jumps from the state 0 to the state 1, the state 3, the state 4, the state 5 and the state 6 in sequence after being started and then returns to the state 0. The reset flow means that the corresponding module works after reset output from the state 0 to the state 5, and when the module corresponding to the state 6 is released, the previously reset release module is reset again, so that the whole module is ensured to be reset in a determined state.
Referring to fig. 8, to facilitate understanding of the present disclosure, an embodiment of the present disclosure further provides a software configurable reset method, which is applied to the reset apparatus shown in fig. 1, and resets a chip, where the reset apparatus includes a reset state machine and a configurable reset condition register, and the chip may be, for example, an ASIC chip or an FPGA chip. The method comprises the following steps:
s1, the reset state machine of the reset device is configured to jump the state according to the order specified by the configurable reset condition register;
and S2, when the chip meets the reset condition, the reset device generates reset output in the corresponding state according to the state jump sequence, and the modules in the chip are controlled to complete the reset operation in sequence.
In some optional implementations, the reset device may further include a configuration interface and a register set, and the reset state machine may have at least two states, each state correspondingly controls at least one path of reset output signal, and the reset output signal is used to control a reset operation of at least one module inside the chip.
Step S1 may specifically include: and the configuration interface configures the value of the configurable reset condition register, and the configuration value of the configurable reset condition register is used for indicating the state jump condition of the reset state machine so that the reset state machine performs state jump according to a specified sequence.
Step S2 may specifically include: the reset state machine reads the configuration value of the configurable reset condition register, starts when the reset condition is judged to be met, outputs at least two reset output signals, performs state skipping according to the sequence specified by the configuration value, sequentially releases the at least two reset output signals according to the state skipping sequence, and controls modules in the chip to complete reset operation in sequence.
In some alternative implementations, the configurable reset condition register may include a start register and a plurality of condition registers, the plurality of registers corresponding to a plurality of states of the reset state machine, respectively.
Step S2 may specifically include:
the reset state machine judges whether to start or not according to the value of the start register in an initial state;
after the reset state machine is started, switching to a first state, and judging whether to jump to another state in the first state according to the configuration value of the corresponding register;
if the jump is to the other state, judging whether to continue the jump or not in the other state according to the configuration value of the corresponding register;
when the previous state jumps to the next state, the reset output signal corresponding to the previous state is released, so that the corresponding module completes the reset operation.
The software configurable reset apparatus and method provided by the embodiments of the present disclosure are described in detail above. By adopting the technical scheme disclosed by the invention, the following technical effects can be realized but not limited:
1. by adopting a configuration register, a reset source or a reset input signal can be flexibly configured through software;
2. the reset state can be realized by coding and can be flexibly configured by software;
3. the switching of the reset state and the switching condition (namely, the skipping condition) can be flexibly configured through software;
4. the reset logic is general logic, is not only suitable for modules with specific functions, can flexibly change a reset source, a reset state and a reset condition through software setting, and has strong universality;
5. when the design scheme changes and the synchronous modification of the reset design is needed, the modification can be completed only by simply updating the initial value of the configuration register;
6. after the chip is produced, the reset abnormity occurs or the debugging stage can carry out debugging, isolation and design defect positioning by configuring reset jump conditions.
In general, the software configurable reset method of the present disclosure is a method for redefining the automatic reset full flow by software. The reset device adopted by the method is a universal module based on a state machine, comprises the reset state machine, and can realize different reset functions through software configuration, so that the reset device controls the reset sequence of the internal modules of the chip according to the configuration sequence. The reset method has the mechanism characteristics of configurability, expandability and adjustability, and overcomes the defect that the reset source, the reset state and the reset state switching condition in the chip reset design can only be designed specifically and can not be suitable for the flexible configuration of software according to the requirements.
In the implementation manner of the embodiment of the present disclosure, the conventional reset flow is changed into a Finite State Machine (FSM) that can be configured by software, and the jump condition, the jump state, and the jump result in the conventional reset flow are implemented by using configurable registers, respectively. Therefore, the problems of reset sequence adjustment, reset output control and reset debugging are fundamentally solved, the reset design becomes a reusable design, software configuration can be carried out according to different use requirements, the design period is further saved, and the gap between the design intention and the realization is shortened.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
The above embodiments are merely illustrative of the technical solutions of the present disclosure, and not restrictive; those of ordinary skill in the art will understand that: the technical solutions described in the above embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.
Claims (8)
1. A software configurable reset device is used for resetting a chip and comprises a reset state machine and a configurable reset condition register, wherein the reset state machine is configured to perform state skipping according to the sequence specified by the configurable reset condition register, and when the reset condition is met, the reset device generates reset output in the corresponding state according to the state skipping sequence and controls modules inside the chip to complete reset operation in sequence.
2. The apparatus of claim 1,
the reset state machine has at least two states, each state correspondingly controls at least one path of reset output signals, and the reset output signals are used for controlling the reset operation of at least one module in the chip; and the number of the first and second groups,
the reset device further comprises a configuration interface, the configuration interface is used for configuring the value of the configurable reset condition register, and the configuration value of the configurable reset condition register is used for indicating the state jump condition of the reset state machine, so that the reset state machine performs state jump according to a specified order;
the reset state machine is used for reading the configuration value of the configurable reset condition register, starting when the reset condition is judged to be met, outputting at least two paths of reset output signals, performing state skipping according to the sequence specified by the configuration value, sequentially releasing the at least two paths of reset output signals according to the state skipping sequence, and controlling the modules in the chip to complete reset operation according to the sequence.
3. The apparatus of claim 2, wherein the configurable reset condition register comprises an enable register and at least two condition registers; and the number of the first and second groups,
the reset state machine is specifically configured to: in an initial state, judging whether to start or not according to the value of the start register; starting the system, switching to a first state, and judging whether to jump to another state in the first state according to the configuration value of the corresponding condition register; if the jump is to the other state, judging whether to continue the jump or not in the other state according to the configuration value of the corresponding condition register; when the previous state jumps to the next state, the reset output signal corresponding to the previous state is released, so that the corresponding module completes the reset operation.
4. The apparatus of claim 2, wherein the chip is an Application Specific Integrated Circuit (ASIC) chip or a Field Programmable Gate Array (FPGA) chip.
5. A software configurable reset method applied to a reset device for resetting a chip, the reset device comprising a reset state machine and a configurable reset condition register, the method comprising:
step S1: a reset state machine of the reset device is configured to perform state jumps in an order specified by the configurable reset condition register;
step S2: and when the reset condition is met, the reset device generates reset output in a corresponding state according to the state jump sequence, and controls modules in the chip to complete reset operation in sequence.
6. The method according to claim 5, wherein the reset state machine has at least two states, each state correspondingly controls at least one path of reset output signal, and the reset output signal is used for controlling the reset operation of at least one module inside the chip; the reset device further comprises a configuration interface; and
step S1 specifically includes: the configuration interface configures the value of the configurable reset condition register, and the configured value of the configurable reset condition register is used for indicating the state jump condition of the reset state machine, so that the reset state machine performs state jump according to a specified sequence;
step S2 specifically includes: and the reset state machine reads the configuration value of the configurable reset condition register, starts when the reset condition is judged to be met, outputs at least two paths of reset output signals, performs state skipping according to the sequence specified by the configuration value, sequentially releases the at least two paths of reset output signals according to the state skipping sequence, and controls the modules in the chip to complete reset operation in sequence.
7. The method of claim 6, wherein the configurable reset condition register comprises an enable register and a plurality of condition registers, the plurality of condition registers corresponding to a plurality of states of the reset state machine, respectively; and
step S2 specifically includes:
the reset state machine judges whether to start or not according to the value of the start register in an initial state;
the reset state machine is switched to a first state after being started, and whether the reset state machine is switched to another state is judged according to the configuration value of the corresponding condition register in the first state;
if the jump is to the other state, judging whether to continue the jump or not in the other state according to the configuration value of the corresponding condition register;
when the previous state jumps to the next state, the reset output signal corresponding to the previous state is released, so that the corresponding module completes the reset operation.
8. The method of claim 5, wherein the chip is an Application Specific Integrated Circuit (ASIC) chip or a Field Programmable Gate Array (FPGA) chip.
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