KR100390402B1 - Triple Modular Redundancy Apparatus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exchanger system, and more particularly, to a triple redundant modular apparatus (hereinafter, abbreviated as TMR apparatus) implemented as the same three modules in a hardware fault tolerant system. .

The present invention provides a TMR device having a simpler interface between multiplexed modules, and provides a TMR device capable of efficiently diagnosing and recovering an error operation of the multiplexed modules.

Description

Triple Modular Redundancy Apparatus

The present invention relates to an exchange system, and more particularly, to a TMR device implemented in the same three modules in a hardware fault tolerant system.

Generally, a hardware fault tolerance system is a system that can withstand failures. It is a system that duplicates arithmetic or logic circuits under the assumption that hardware faulty operation must occur so that faulty operation of these circuits can be automatically corrected. to be.

This hardware fault tolerant system keeps running processes even if part of the system fails, without affecting overall system operation.

It also diagnoses and automatically takes care of critical faults in parts of the system, ensuring correct results without the need for artificial handling of faulty behavior.

Such hardware fault tolerance systems use redundant or tripled redundant modular devices.

TMR devices are used in such hardware fault tolerant systems. The TMR device is designed to multiplex the major hardware elements such as the central processing unit, system bus memory, I / O processing unit, and I / O bus to diagnose and recover any failures. Equipped.

1 is a block diagram showing the structure of a conventional TMR system.

1, the first module (B1) (1), the second module (B2) (2) and the third module (B3) (3) have the same hardware structure, and the same software program is mounted It is.

Therefore, if each module (1, 2, 3) operates normally, it will be operated by a clock that is synchronized exactly, and will output the same processing results at the same time.

At this time, the output port module (V) 4 uses the processing results output from the modules 1, 2, and 3 as inputs, and compares each processing result, and sends out the final output according to the comparison result.

The output port module (V) 4 compares the processing result output from each module 1, 2, 3, and if two or more outputs among the three outputs are the same, these same outputs are sent out as final outputs. However, for the module that does not output the same processing result, it is regarded as an error and a diagnostic signal is provided.

In addition, the output port module (V) 4 compares the processing result output from each module (1, 2, 3), and if all three outputs are not the same, an error occurs in each module (1, 2, 3). Each of them provides a diagnostic signal.

Then, the corresponding module that receives the diagnostic signal from the output port module (V) 4 uses these diagnostic signals to diagnose an error generated.

Such a conventional TMR apparatus should be provided with an output port module for outputting the final output by comparing and determining the output of each module in addition to the multiplexed modules.

Due to this, the interconnection between the modules provided in the TMR apparatus is complicated, and in particular, when an error occurs in the output port module, there is no alternative to recover the system, which has an undesirable effect on the entire system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a TMR device having a simpler interface between multiplexed modules.

Another object of the present invention is to provide a TMR apparatus capable of efficiently diagnosing and recovering an error operation of multiplexed modules.

A feature of the TMR apparatus according to the present invention for achieving the above object is, by combining each of the results of the processing of the multiplexed modules combined by one or more, it is possible to determine whether each module has its own diagnosis based on the comparison results Comparing logic circuits each providing a constant signal are provided in the multiplexed module.

Preferably, the comparison logic circuit in the multiplexed module forms a loop in the order of the first module, the second module, and the third module.

In addition, the first comparison logic circuit provided in the first module of the comparison logic circuit, the result of comparing the output of the first module and the output of the third module located in the front end of the second comparison of the second module located in the next stage To the logic circuit.

Here, the first comparison logic circuit, the result of comparing the output of the second module and the output of the third module, and the result of comparing the output of the first module and the output of the second module is the third It is provided from the third comparison logic circuit provided in the module.

1 is a block diagram showing the structure of a conventional TMR device;

2 illustrates a structure of a comparison logic circuit according to the present invention;

Figure 3 is a block diagram showing the structure of a TMR apparatus according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: first module M1 11: first comparison logic circuit CL1

20: second module M2 21: second comparison logic circuit CL2

30: third module M3 31: third comparison logic circuit CL3

Hereinafter, a preferred embodiment of a TMR apparatus according to the present invention will be described with reference to the accompanying drawings.

The TMR apparatus of the present invention does not use an existing output port module for comparing and determining the result of processing output from each module, and includes a compiling logic circuit inside each module.

2 is a diagram showing the structure of a comparison logic circuit CL according to the present invention.

The following describes the operation of the comparison logic circuit CL according to the invention shown in FIG.

The input / output relationship of the comparison logic circuit CL is expressed as VHSIC Hardware Description Language (VHSIC), which is a description language used to design a very high speed integrated circuit (VHSIC).

"Entity CL is port (

SCS, CSI: in std_logic_vector (n downto 0);

PCRI, NCRI, P: in std_logic;

PCRO, CRO: out std_logic;

CSO: out std_logic_vector (n downto 0);

BE, D: out std_logic);

end CL;

architecture main of CL is

begin

CSO <= SCS;

PCRO <= PCRI;

CRO <= '0' when CSI = SCS else '1'

BE <= '0' when CSI = SCS and PCRI = '1'

'0' when CSI = SCS and PCRI = '0' and P = '0' else '1';

D <= '0' when CSI ≠ SCS and NCRI = '1' and PCRI = '1' else '1';

end main; "

As can be seen above, the CSO outputs the SCS as it is, and the PCRO outputs the PCRI as it is.

The CRO outputs '0' when the CSI and SCS are the same, and outputs '1' when the CSI and the SCS are different.

BE outputs '0' when CSI and SCS are equal and PCRI is '1', and outputs '0' when CSI and SCS are equal and PCRI is '0' and P is '0'. However, in other cases, it outputs '1'.

D outputs '0' when CSI and SCS are not equal, NCRI is '1', and PCRI is '1'. However, in other cases, it outputs '1'.

3 is a block diagram illustrating a structure of a TMR device according to the present invention. Hereinafter, the comparison logic circuit illustrated in FIG. 2 will be further described, and the operation of the TMR device according to the present invention will be described.

Referring to FIG. 3, the first module M1 10, the second module M2 20, and the third module M3 30 have the same hardware structure, and the same software program is mounted. It is.

In addition, the TMR apparatus of the present invention includes a comparison logic circuit CL shown in FIG. 2, and a loop is formed between the modules 10, 20, and 30 as shown.

The basic TMR device operates three identical modules 10, 20, and 30 simultaneously, and if two or more outputs of the modules 10, 20, and 30 are identical, the output at that time is a normal processing result. Acknowledge it as the final output.

For example, if two or more outputs among the outputs of each of the modules 10, 20, and 30 are the same, these same outputs are exported as the final output. However, for the module that does not output the same processing result, it is regarded as an error and a diagnostic signal is provided.

In addition, if all of the outputs of the modules 10, 20, and 30 are not identical to each other, it is assumed that an error has occurred in each of the modules 10, 20, and 30, and appropriate diagnostic processing is performed in each of the modules 10, 20, and 30. Each provides a diagnostic signal to be performed.

Here, each module 10, 20, 30 operates by the input-output relationship of the comparison logic circuit CL described above, which will be described in more detail.

In the following description, the first module M1 10 will be described.

The CRO of the first module (M1) 10 is a signal indicating the result of comparing the output of the module itself and the output of the third module (M3) 30 located at the front end when forming a loop, the resurrection signal (Active Low signal). At this time, the output of the first module M1 (10) itself is SCS, and the output of the third module (M3) 30 located at the front end is CSI.

This CRO outputs '0' when the CSI and SCS are the same, and outputs '1' when the CSI and the SCS are different.

The PCRO outputs the PCRI as it is as a result of comparing the outputs of the second module M2 20 and the third module M3 30.

The CSO is a signal informing the second module M2 20 located at the next stage of the output of the first module M1 10 itself, and outputs the SCS as it is.

BE is a signal indicating the active state of the first module (M1) 10, and outputs '0' when CSI and SCS are the same and PCRI is '1', and CSI and SCS are the same and PCRI is '0'. It is also an active low signal that outputs '0' when P is '0'. However, in other cases, it outputs '1'.

D is a signal indicating that the first module (M1) 10 is abnormally operating and that a diagnostic process should be performed. When CSI and SCS are not equal, NCRI is '1' and PCRI is '1', It is an active low signal that outputs 0 '. However, in other cases, it outputs '1'.

P is a signal indicating the position of the module, and only one module of the three modules 10, 20, and 30 is set to '0', and the other modules are set to '1'. In the above description, the first module M1 10 is described mainly, and only the first module M1 10 is set to '0'.

In consideration of the operation of the TMR device, if an error occurs in the first module M1 10, the second module M2 20 may not be the same since the CSI and the SCS are not the same in the second module M2 20. CRO outputs '1', and since CSI and SCS are the same in the third module M3 30, the CRO of the third module M3 30 outputs '0'.

As a result, BE and D of the second module M2 20 are '1', BE of the third module M3 30 is '0' and D is '1'.

However, D of the first module M1 10 becomes '0' to execute the diagnostic process.

In summary, the first comparison logic circuit 11 of the first module M1 10 may include the third module M3 30 positioned at the output and the front end of the first module M1 10. The result of comparing the outputs of the?) Is provided to the second comparison logic circuit 21 of the second module M2 20 located next.

At this time, the first comparison logic circuit 11 compares the output of the second module M2 20 with the output of the third module M3 30, and the first module M1 10. The result of comparing the output of the output with the second module (M2) 20 is received from the third comparison logic circuit 31 of the third module (M3) (30).

However, if all three modules 10, 20, 30 operate normally and output the same processing result, D of the three modules 10, 20, 30 becomes '1', and the three modules 10, 20, 30 ) Module with P '0' operates and sends out the final output. In FIG. 3, the first module M1 10 in which P is '0' operates.

In addition, if all three modules 10, 20, and 30 operate to output their respective processing results, it is difficult to determine which module is abnormally operated, so that D of the three modules 10, 20, and 30 is 0. Thus, the diagnostic processing is executed in all three modules 10, 20, and 30.

As described above, in the present invention, the interface between the multiplexed modules is simpler, but the error operation of each module can be efficiently diagnosed and recovered.

In addition, it is possible to ensure more stable system operation when using such a TMR device in the exchange system.

Claims (3)

By comparing and comparing each processing result of the multiplexed modules by one or more, a comparison logic circuit is provided to each of the multiplexed modules so that each module provides a predetermined signal so that each module can determine its diagnosis based on the compared result. Triple redundancy modular device characterized in that it is provided. The triple redundancy modular apparatus of claim 1, wherein the comparison logic circuit in the multiplexed module forms a loop in the order of a first module, a second module, and a third module. The second comparison logic circuit of claim 1, wherein the first comparison logic circuit provided in the first module compares the output of the first module with the output of the third module located at the front end of the second module. A second comparison logic circuit, wherein the first comparison logic circuit compares an output of the second module with an output of the third module, and compares an output of the first module with an output of the second module. The triple redundant modular apparatus characterized in that the result is provided from a third comparison logic circuit provided in the third module.