CN111599690A - Double-sided cavity digging ceramic packaging process based on coexistence of WB chip and FC chip - Google Patents

Double-sided cavity digging ceramic packaging process based on coexistence of WB chip and FC chip Download PDF

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CN111599690A
CN111599690A CN202010459040.8A CN202010459040A CN111599690A CN 111599690 A CN111599690 A CN 111599690A CN 202010459040 A CN202010459040 A CN 202010459040A CN 111599690 A CN111599690 A CN 111599690A
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chip
ceramic
ceramic substrate
digging
coexistence
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胡孝伟
代文亮
伊海伦
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Shanghai Sinbo Electronic Technology Co ltd
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Shanghai Sinbo Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807—Ceramic parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

According to the double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip, cavities are dug in advance at chip mounting positions on two side faces of a ceramic substrate, the WB chip and the FC chip are respectively sunk into corresponding ceramic cavities and connected with the ceramic substrate during packaging, a cover plate is welded on a kovar ring around the ceramic substrate through a parallel seam welding process, and balls are planted on the back face of the ceramic substrate to complete packaging. Dig the chamber and place WB chip or FC chip respectively through upper and lower side for ceramic substrate's encapsulation space grow has improved ceramic package's space utilization and has reduced ceramic package's overall dimension.

Description

Double-sided cavity digging ceramic packaging process based on coexistence of WB chip and FC chip
Technical Field
The invention belongs to the technical field of chip ceramic packaging, and particularly relates to a double-sided cavity digging ceramic packaging process based on coexistence of a WB chip and an FC chip.
Background
With the continuous development of semiconductor technology, more and more chip types are developed to meet different market demands, wherein WB chips and FC chips are one of the mainstream chips used for current packaging. However, the existing ceramic packaging structure of the chip has the problem that the requirement is difficult to meet due to small internal space.
Disclosure of Invention
1. Technical problem to be solved by the invention
The invention aims to solve the problem that the existing ceramic packaging structure of the chip is difficult to meet the requirement due to small internal space.
2. Technical scheme
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
according to the double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip, cavities are dug in advance at chip mounting positions on two side faces of a ceramic substrate, the WB chip and the FC chip are respectively sunk into corresponding ceramic cavities and connected with the ceramic substrate during packaging, a cover plate is welded on a kovar ring around the ceramic substrate through a parallel seam welding process, and balls are planted on the back face of the ceramic substrate to complete packaging.
Preferably, the packaging process specifically includes the following steps:
s100, digging cavities, namely digging the cavities at chip mounting positions on two side surfaces of the ceramic substrate;
s200, welding a kovar ring, and welding the kovar ring on a welding area on the ceramic substrate;
s300, insulating, namely isolating the cavities on the same plane from each other;
s400, mounting, namely sinking the WB chip and the FC chip into corresponding ceramic cavities respectively and fixing;
s500, bottom filling, namely filling the space between the FC chip (1) and the ceramic substrate (8) by using filling glue;
s600, conducting, namely conducting the WB chip and the FC chip with the ceramic substrate;
s700, sealing a cap, namely welding a cover plate on a kovar ring on a ceramic substrate in a parallel sealing and welding mode;
and S800, planting balls, namely planting the balls on the back of the ceramic substrate to complete packaging.
Preferably, the cavity digging in step S100 is specifically to firstly cut grooves in corresponding positions of the green ceramic sheets by laser or mechanical punching, and then to stack the green ceramic sheets of each layer together for sintering, and the grooves in the corresponding positions are stacked together to form a cavity.
Preferably, the mounting in step S400 is specifically to mount the FC chip into the cavity of the ceramic substrate in a surface mounting manner, with the mounting accuracy controlled within ± 35 um; and bonding the WB chip in the cavity of the ceramic substrate by using silver paste, wherein the bonding precision of the chip is controlled within +/-35 um.
Preferably, the underfill in step S500 is to perform underfill on the solder balls at the bottom of the FC chip in the cavity.
Preferably, the conducting in step S600 includes using gold wires or aluminum wires to connect the signals on the WB chip and the leads of the ceramic substrate by bonding.
Preferably, the width of the welding zone in the step S200 is 1.5-2.0 mm.
Preferably, baking is required after the underfill is completed to fully cure the underfill.
Preferably, the cavity digging depth for mounting FC chips is 0.2-0.4 mm, and the cavity digging depth for mounting WB chips is 0.4-0.6 mm.
Preferably, the baking process is to bake the ceramic substrate at 150 ℃ for 30-40 minutes to completely cure the filling adhesive.
3. Advantageous effects
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
according to the double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip, cavities are dug in advance at chip mounting positions on two side faces of a ceramic substrate, the WB chip and the FC chip are respectively sunk into corresponding ceramic cavities and connected with the ceramic substrate during packaging, a cover plate is welded on a kovar ring around the ceramic substrate through a parallel seam welding process, and balls are planted on the back face of the ceramic substrate to complete packaging. Dig the chamber and place WB chip or FC chip respectively through upper and lower side for ceramic substrate's encapsulation space grow has improved ceramic package's space utilization and has reduced ceramic package's overall dimension.
Drawings
Fig. 1 is an internal top view of a fabricated package structure of the present embodiment;
fig. 2 is an internal bottom view of the prepared package structure of the present embodiment;
fig. 3 is a schematic structural diagram of a package structure prepared according to the present embodiment;
FIG. 4 is a process flow diagram of the present invention.
The reference numerals in the schematic drawings illustrate:
1. a ceramic substrate; 2. a welding zone; 3. a top surface cavity I; 4. WB chip; 5. gold thread; 6. a pin; 7. a top surface cavity II; 8. an FC chip; 9. tin balls; 10. dispensing a glue layer; 11. a kovar ring; 12. a cover plate; 13. a bottom cavity; 17. and (5) planting balls.
Detailed Description
In order to facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings, in which several embodiments of the invention are shown, but which may be embodied in many different forms and are not limited to the embodiments described herein, but rather are provided for the purpose of providing a more thorough disclosure of the invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present; when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present; the terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention; as used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1-4, in the double-sided cavity digging ceramic packaging process based on coexistence of the WB chip and the FC chip of the embodiment, cavities are dug in advance at chip mounting positions on two side surfaces of a ceramic substrate 1, the WB chip 4 and the FC chip 8 are respectively sunk into corresponding ceramic cavities and connected with the ceramic substrate 1 during packaging, a cover plate 12 is welded on a kovar ring 11 around the ceramic substrate 1 through a parallel seam welding process, and balls 17 are planted on the back surface of the ceramic substrate 1 to complete packaging.
The packaging process specifically comprises the following steps:
s100, digging cavities, namely digging cavities at chip mounting positions on two side surfaces of a ceramic substrate 1, wherein the size of each digging cavity is matched with the size of a chip to be placed, the depth of the digging cavity for mounting an FC chip 8 is 0.2mm, and the depth of the digging cavity for mounting a WB chip 4 is 0.4 mm;
s200, welding a kovar ring 11, welding the kovar ring 11 on a welding area 2 on the ceramic substrate 1, wherein the kovar ring 11 is used for fixing a cover plate 12;
s300, insulating, namely isolating the cavities on the same plane from each other;
s400, mounting, namely sinking the WB chip 4 and the FC chip 8 into corresponding ceramic cavities respectively and fixing;
s500, bottom filling, namely filling the space between the FC chip 1 and the ceramic substrate 8 by using filling glue;
s600, conducting, namely conducting the WB chip 4 and the FC chip 8 with the ceramic substrate 1;
s700, sealing a cap, namely welding the cover plate 12 on the Kovar ring 11 on the ceramic substrate in a parallel sealing and welding mode;
and S800, planting balls, namely planting the balls 17 on the back surface of the ceramic substrate 1 to finish packaging.
The cavity digging step S100 is to first cut grooves in corresponding positions of the green ceramic sheets by laser or mechanical punching, and then to stack the green ceramic sheets together for sintering, and the grooves in the corresponding positions are stacked together to form a cavity. Grooving is performed on each green ceramic chip in advance, then the green ceramic chips are assembled and sintered to form a cavity, compared with the whole green ceramic chip, the green ceramic chip is more stable in forming the cavity, the size of the cavity is controllable, structural damage to the ceramic substrate 1 caused by the grooving process after sintering is reduced, and the integrity and the stability of the ceramic substrate 1 are greatly improved.
The mutual isolation is to fill the grounding hole on the ceramic body between the cavities, so that the mutual interference between the components of the adjacent cavities is prevented, and the stability of the whole chip is improved.
The mounting in step S400 is specifically to mount the FC chip 8 to the cavity of the ceramic substrate 1 in a surface mounting manner, the mounting accuracy is controlled within ± 35um, the WB chip 4 is bonded to the cavity of the ceramic substrate 1 by using silver paste, and the chip bonding accuracy is controlled within ± 35 um.
The underfill in step S500 is to perform underfill on the solder balls 9 at the bottom of the FC chip 8 in the cavity.
The conduction in step S600 includes using gold wires or aluminum wires to connect the signals on the WB chip 4 and the leads 6 of the ceramic substrate 1 by bonding.
The width of the welding area in step S200 is 1.5-2.0 mm.
Baking is required after the underfill is completed to cure the underfill. The specific baking process is to bake the ceramic substrate at the temperature of 150 ℃ for 30-40 minutes to completely cure the filling adhesive.
Dig the chamber including top surface chamber one 3 and top surface chamber two 7 to the side on this embodiment, the downside of ceramic substrate 1 digs the chamber including bottom surface chamber 13, top surface chamber one 3 and top surface chamber two 7 are laminated respectively and are had WB chip 4 and FC chip 8, the laminating has WB chip 4 or FC chip 8 in the bottom surface chamber 13. The ceramic packaging structure of this embodiment digs the chamber respectively through upper and lower side and forms top surface chamber one 3, top surface chamber two 7 and bottom surface chamber 13 to place WB chip 4 or FC chip 8 in top surface chamber one 3, top surface chamber two 7 and bottom surface chamber 13, make ceramic substrate 1's encapsulation space grow, improved ceramic packaging's space utilization and reduced ceramic packaging's overall dimension.
The WB chip 4 of this embodiment is connected to the leads 6 on the ceramic substrate 1 through gold wires 5, and the FC chip 8 is connected to the solder balls 9 on the ceramic substrate 1 and filled with a paste layer 10.
The side cover has apron 12 on ceramic substrate 1 of this embodiment, apron 12 is through kovar ring 11 and ceramic substrate 1 fixed connection, the area of apron 12 and the contact of kovar ring 11 is the notch cuttype structure, and the apron 12 of being convenient for carries out fixed mounting and can improve stability with kovar ring 11. The ceramic substrate 1 is provided with a welding area 2, and the kovar ring 11 is fixedly connected with the welding area 2.
The first top surface cavity 3 and the second top surface cavity 7 in the embodiment have the same area or different areas. At least one WB chip 4 or at least one FC chip 8 is arranged in the top surface cavity I3 and the top surface cavity II 7 respectively. The lower side of the ceramic substrate 1 is provided with the planting balls 17 in the area where the bottom cavity 13 is not formed.
The above-mentioned embodiments only express a certain implementation mode of the present invention, and the description thereof is specific and detailed, but not construed as limiting the scope of the present invention; it should be noted that, for those skilled in the art, without departing from the concept of the present invention, several variations and modifications can be made, which are within the protection scope of the present invention; therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A double-sided cavity digging ceramic packaging process based on coexistence of a WB chip and an FC chip is characterized in that: digging cavities in advance at chip mounting positions on two side faces of the ceramic substrate, respectively sinking the WB chip and the FC chip into corresponding ceramic cavities and connecting the WB chip and the FC chip with the ceramic substrate during packaging, welding the cover plate on kovar rings around the ceramic substrate through a parallel seam welding process, planting balls on the back of the ceramic substrate, and completing packaging.
2. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in claim 1, wherein the packaging process specifically comprises the following steps:
s100, digging cavities, namely digging the cavities at chip mounting positions on two side surfaces of the ceramic substrate;
s200, welding a kovar ring, and welding the kovar ring on a welding area on the ceramic substrate;
s300, insulating, namely isolating the cavities on the same plane from each other;
s400, mounting, namely sinking the WB chip and the FC chip into corresponding ceramic cavities respectively and fixing;
s500, bottom filling, namely filling the space between the FC chip (1) and the ceramic substrate (8) by using filling glue;
s600, conducting, namely conducting the WB chip and the FC chip with the ceramic substrate;
s700, sealing a cap, namely welding a cover plate on a kovar ring on a ceramic substrate in a parallel sealing and welding mode;
and S800, planting balls, namely planting the balls on the back of the ceramic substrate to complete packaging.
3. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in claim 2, wherein: the cavity digging in the step S100 is specifically to first cut grooves in corresponding positions of the green ceramic sheets by laser or mechanical punching, and then to stack the green ceramic sheets together for sintering, and the grooves in the corresponding positions are stacked together to form a cavity.
4. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in claim 2, wherein: the mounting in step S400 is specifically to mount the FC chip into the cavity of the ceramic substrate in a surface mounting manner, with mounting accuracy controlled within ± 35 um; and bonding the WB chip in the cavity of the ceramic substrate by using silver paste, wherein the bonding precision of the chip is controlled within +/-35 um.
5. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in claim 2, wherein: the underfill in step S500 is to perform underfill on the solder balls at the bottom of the FC chip in the cavity.
6. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in claim 2, wherein: the conducting in step S600 includes using gold wires or aluminum wires to connect the signals on the WB chip and the leads of the ceramic substrate by bonding.
7. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in claim 2, wherein: the width of the welding area in the step S200 is 1.5-2.0 mm.
8. The WB chip and FC chip coexistence-based double-sided cavity digging ceramic packaging process according to claim 5, characterized in that: baking is required after the underfill is completed to fully cure the underfill.
9. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in any one of claims 1 to 8, wherein: the cavity digging depth for mounting FC chips is 0.2-0.4 mm, and the cavity digging depth for mounting WB chips is 0.4-0.6 mm.
10. The double-sided cavity digging ceramic packaging process based on the coexistence of the WB chip and the FC chip as claimed in claim 8, wherein: the baking process is to bake the ceramic substrate at 150 ℃ for 30-40 minutes to completely cure the filling adhesive.
CN202010459040.8A 2020-05-27 2020-05-27 Double-sided cavity digging ceramic packaging process based on coexistence of WB chip and FC chip Pending CN111599690A (en)

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CN101010996A (en) * 2005-05-12 2007-08-01 株式会社村田制作所 Ceramic multilayer substrate
JP2009088338A (en) * 2007-10-01 2009-04-23 Mitsubishi Electric Corp Package for housing electronic component
CN101714543A (en) * 2009-11-12 2010-05-26 美新半导体（无锡）有限公司 Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof
CN203014756U (en) * 2012-11-26 2013-06-19 苏州工业园区阳晨封装技术有限公司 Percussion welding ceramic sealed housing and crystal oscillator employing same
CN106229301A (en) * 2016-08-01 2016-12-14 中国电子科技集团公司第五十八研究所 A kind of air-tightness surface attaching type digital isolator encapsulating structure
CN108428672A (en) * 2018-04-17 2018-08-21 中国电子科技集团公司第二十九研究所 The two-sided three-dimensionally integrated framework of ceramics and packaging method of ultra-wide band radio-frequency micro-system
CN109803523A (en) * 2019-02-23 2019-05-24 华为技术有限公司 A kind of encapsulation shielding construction and electronic equipment
CN111048500A (en) * 2019-12-17 2020-04-21 中国电子科技集团公司第三十八研究所 Integrally packaged radio frequency microsystem assembly

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
CN101010996A (en) * 2005-05-12 2007-08-01 株式会社村田制作所 Ceramic multilayer substrate
JP2009088338A (en) * 2007-10-01 2009-04-23 Mitsubishi Electric Corp Package for housing electronic component
CN101714543A (en) * 2009-11-12 2010-05-26 美新半导体（无锡）有限公司 Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof
CN203014756U (en) * 2012-11-26 2013-06-19 苏州工业园区阳晨封装技术有限公司 Percussion welding ceramic sealed housing and crystal oscillator employing same
CN106229301A (en) * 2016-08-01 2016-12-14 中国电子科技集团公司第五十八研究所 A kind of air-tightness surface attaching type digital isolator encapsulating structure
CN108428672A (en) * 2018-04-17 2018-08-21 中国电子科技集团公司第二十九研究所 The two-sided three-dimensionally integrated framework of ceramics and packaging method of ultra-wide band radio-frequency micro-system
CN109803523A (en) * 2019-02-23 2019-05-24 华为技术有限公司 A kind of encapsulation shielding construction and electronic equipment
CN111048500A (en) * 2019-12-17 2020-04-21 中国电子科技集团公司第三十八研究所 Integrally packaged radio frequency microsystem assembly

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Application publication date: 20200828