CN215297764U - High-density CPO silicon optical engine - Google Patents
High-density CPO silicon optical engine Download PDFInfo
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- CN215297764U CN215297764U CN202121895317.8U CN202121895317U CN215297764U CN 215297764 U CN215297764 U CN 215297764U CN 202121895317 U CN202121895317 U CN 202121895317U CN 215297764 U CN215297764 U CN 215297764U
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Abstract
The utility model provides a high-density CPO silicon photo engine, it includes: a circuit substrate, an optical chip, an electrical chip assembly and an optical coupling assembly; the top surface of the circuit substrate is provided with a first groove, the optical chip is arranged in the first groove, and the optical chip is connected with the circuit substrate through lead bonding; the second groove is formed in one side area of the top surface of the optical chip, the electrical chip assembly is arranged in the second groove in a flip-chip mode, and the optical coupling assembly is arranged on the other side area of the top surface of the optical chip. The utility model discloses a carry out three-dimensional stereoscopic packaging with circuit substrate, optical chip, electricity chip subassembly, can make CPO silicon photo engine transmission bandwidth increase one time. Meanwhile, the transmitting driving electric chip and the receiving electric chip are stacked and sealed into a packaging structure of an electric chip assembly, and the problems of high-frequency signal distortion and low bandwidth caused by insufficient space of the electric chip assembly and the connection mode of the photoelectric chip in the 2D packaging technology are solved.
Description
Technical Field
The utility model relates to a silica-based encapsulation technical field of optical communication especially relates to a high-density CPO silicon photo engine.
Background
With the development of industries such as artificial intelligence, big data, 5G application, supercomputing and the like and under a large environment with more and more severe energy consumption requirements of a data center and a supercomputing center, the optical module must be developed towards high integration, low power consumption, high density and low cost. The traditional optical module is limited by the board card panel space, the bandwidth can not be improved by increasing the number of the optical modules, and meanwhile, the ultrahigh-speed bandwidth high-frequency electric signal loss such as 800G, 1.6T and the like requires that the photoelectric conversion module is as close as possible to a switch chip.
In view of the above development requirements of high integration, low power consumption, high density and low cost, a conventional 2D package structure CPO silicon optical engine is disclosed in patent CN112859259A, in which the optoelectronic chips are connected by wire bonding. However, wire bonding can affect high frequency signal transmission, reducing the high frequency transmission bandwidth. And each silicon optical engine 8 channel has a bandwidth of 25G per single channel, i.e. each silicon optical engine has a bandwidth of 200G, the 1U switch can realize a transmission rate of 3.2T. However, with the explosive growth of data transmission in supercomputing centers, the 3.2T rate has not been able to meet its demand. Therefore, it is necessary to provide a further solution to the above problems.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a high-density CPO silicon light engine to overcome the not enough that exists among the prior art.
In order to solve the technical problem, the technical scheme of the utility model is that:
a high density CPO silicon light engine, comprising: a circuit substrate, an optical chip, an electrical chip assembly and an optical coupling assembly;
the top surface of the circuit substrate is provided with a first groove, the optical chip is arranged in the first groove and forms a height difference with the circuit substrate, and the height difference is suitable for the optical chip and the circuit substrate to be connected through wire bonding;
the optical chip comprises an optical chip and an electrical chip component, wherein the optical chip is arranged on the optical chip, the electrical chip component is arranged in the second groove in a flip-chip manner, and the optical coupling component is arranged on the other side area of the top surface of the optical chip.
As the utility model discloses the improvement of high-density CPO silicon light engine, optical chip is a plurality of, a plurality of optical chip set up jointly in perhaps set up in respective first recess, arbitrary be provided with in optical chip's the second recess electricity chip subassembly.
As the utility model discloses the improvement of high-density CPO silicon photo engine, circuit substrate's bottom surface still is provided with the array shell fragment.
As the utility model discloses the improvement of high-density CPO silicon light engine, still be provided with a plurality of first protruding electrodes in the second recess, a plurality of first protruding electrodes with electrode array on the electricity chip subassembly corresponds the setting.
As the utility model discloses the improvement of high-density CPO silicon photo engine, it has insulating heat conduction glue still to fill between electricity chip subassembly and the optical chip.
As the utility model discloses the improvement of high-density CPO silicon photo engine, electricity chip subassembly includes that from bottom to top sets gradually: the circuit board comprises a substrate layer, a driving chip, an isolation insulating layer, a TIA chip and a sealing layer.
As the utility model discloses the improvement of high-density CPO silicon photo engine, the base plate layer is ceramic substrate, sets up the through-hole of arranging with the array form on it, the lower surface of through-hole and ceramic substrate is provided with the gold-plated layer, just ceramic substrate's upper surface still is provided with the protruding electrode of a plurality of seconds, driver chip passes through the protruding electrode flip-chip of second weld in on the ceramic substrate.
As the utility model discloses the improvement of high-density CPO silicon photo engine, keep apart the insulating layer set up in driver chip's top, and its both ends have the undercut setting, keep apart the insulating layer through the sunk structure at its both ends with distribution on the ceramic substrate in the protruding electrode of second of driver chip both sides is connected.
As the utility model discloses the improvement of high-density CPO silicon light engine, the top surface of keeping apart the insulating layer still is provided with a plurality of third protruding electrodes, the TIA chip passes through a plurality of third protruding electrodes flip-chip weld in keep apart on the insulating layer.
As the utility model discloses the improvement of high-density CPO silicon light engine, the sealing layer is a metal seal cap, its set up in on the base plate layer, driver chip, isolation insulating layer, TIA chip package in the metal seal cap, just it has the heat conduction glue still to fill in the metal seal cap.
As the utility model discloses the improvement of high-density CPO silicon light engine, optical coupling subassembly adopts one of grating coupling subassembly, terminal surface coupling subassembly and the passive coupling subassembly of V type groove.
As an improvement of the high-density CPO silicon light engine of the present invention, the high-density CPO silicon light engine further comprises a sealing cover;
the sealing cover is arranged on the circuit substrate, the optical chip, the electrical chip assembly and the optical coupling assembly are packaged in the sealing cover, and the sealing cover is filled with heat-conducting glue.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model provides a high-density CPO silicon photo engine based on 3D stereoscopic packaging through carrying out three-dimensional stereoscopic packaging with circuit substrate, optical chip, electricity chip subassembly, can make CPO silicon photo engine transmission bandwidth increase one time, solves the problem that the electric chip connected mode that the space was arranged not enough, photoelectric chip leads to high frequency signal distortion, low bandwidth among the 2D packaging technology simultaneously.
Meanwhile, the electrical chip assembly is designed in a layered mode, so that the driving chip and the TIA chip are sealed in an overlapping mode, space is saved, and meanwhile heat dissipation of the TIA chip is not affected. In addition, the metal sealing cap is adopted for the electrical chip assembly, and the heat conducting glue is filled in the metal sealing cap, so that the heat dissipation performance of the electrical chip assembly is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic perspective view of an embodiment of a high-density CPO silicon optical engine according to the present invention;
FIG. 2 is a bottom view of the circuit substrate of FIG. 1;
FIG. 3 is a schematic view of the internal structure of the high density CPO silicon light engine of FIG. 1 with the sealing cover removed;
fig. 4 is a three-dimensional exploded view of the electrical chip assembly of the high-density CPO silicon photo engine of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a high-density CPO silicon optical engine, which includes: a circuit substrate 10, an optical chip 20, an electrical chip assembly 30, and an optical coupling assembly 40.
As shown in fig. 2, the circuit substrate 10 is used as a carrier for packaging other devices. In one embodiment, the circuit substrate 10 may be a PCBA, i.e., a PCB board on which electronic components are mounted. The bottom surface of this PCBA board still is provided with array shell fragment 11. The array elastic sheet 11 can be used as an electric signal interface between the silicon photo engine and a main board of the switch, and the array elastic sheet 11 can be repeatedly used for many times, so that the silicon photo engine can be flexibly replaced.
As shown in fig. 3, the high-density CPO silicon optical engine of the present embodiment three-dimensionally packages the circuit substrate 10, the optical chip 20, and the electrical chip assembly 30. Specifically, the top surface of the circuit substrate 10 is opened with a first groove 12, and the optical chip 20 is disposed in the first groove 12, so that a height difference is formed between the optical chip 20 and the circuit substrate 10, and the height difference is suitable for the connection between the optical chip 20 and the circuit substrate 10 through wire bonding. Thus, the optical chip 20 is partially embedded in the circuit substrate 10, so that the height of the optical chip 20 and the wire bonding electrode of the circuit substrate 10 is equal or small, the gold wire bonding is shorter, and the loss of high-frequency signals is reduced. That is, the depth of the first groove 12 matches the height difference of the optical chip 20 and the circuit substrate 10, facilitating wire bonding and high-frequency signal transmission. The optical chip 20 may be a silicon optical chip.
Further, in order to realize the packaging of the plurality of optical chips 20, the plurality of optical chips 20 are commonly disposed in one first groove 12 or disposed in respective first grooves 12. An optical chip 20 is disposed in any one of the first grooves 12. And the optical chip 20 and the circuit substrate 10 can be fixed by glue. The depth of the first groove 12 can be determined according to the thickness of the optical chip 20, so as to realize the equal height or small height difference between the optical chip 20 and the bonding electrode of the circuit substrate 10.
A second groove 21 is formed in a side region of the top surface of the optical chip 20, and the electrical chip assembly 30 is flip-chip mounted in the second groove 21. Therefore, the problems that in the prior art, the photoelectric chips are connected in a lead bonding mode, high-frequency signal transmission is influenced, and high-frequency transmission bandwidth is reduced are solved. When a plurality of optical chips 20 are packaged on the circuit substrate 10, an electrical chip assembly 30 is disposed in the second recess 21 of any optical chip 20.
The second groove 21 is further provided with a plurality of first protruding electrodes 211, and the plurality of first protruding electrodes 211 are arranged corresponding to the electrode array on the electrical chip assembly 30. Thus, flip chip technology can be employed with a bottom heating pattern to align the optical chip 20 and electrical chip assembly 30 assembly, the die eutectic. The first bump electrode 211 can be formed by etching, and has a height of about 3 μm and a surface plated with an alloy solder layer of about 2 μm. In addition, in order to improve the thermal conductivity of the package, an insulating thermal conductive adhesive is filled between the electrical chip assembly 30 and the optical chip 20.
The optical coupling component 40 is disposed on the other side region of the top surface of the optical chip 20, and is used as an optical interface of the optical engine of the present embodiment. The optical coupling component 40 is one of a grating coupling component, an end face coupling component and a V-groove passive coupling component, and the coupling component with a corresponding structure can be selected according to actual requirements to be combined and applied to the technical scheme of the embodiment.
As shown in fig. 4, electrical chip assembly 30 comprises, arranged in sequence from bottom to top: a substrate layer 31, a driving chip 32, an isolation insulating layer 33, a TIA chip 34, and a sealing layer 35. The driving chip and the TIA chip are sealed in a stacking mode through the electrical chip assembly 30 with the 5-layer design, so that the space is saved, and meanwhile the heat dissipation of the TIA chip is not influenced.
The substrate layer 31 is a ceramic substrate, through holes arranged in an array are formed in the ceramic substrate, and gold plating layers are arranged on the through holes and the lower surface of the ceramic substrate. The design of the through holes on the ceramic substrate described above should be adapted to the electrical interface parameters of the optical chip 20, the electrical chip assembly 30 and take into account the influence of high frequency performance. Meanwhile, the upper surface of the ceramic substrate is further provided with a plurality of second bump electrodes 311, and the driving chip 32 is used for driving the whole electrical chip assembly 30 to work and is flip-chip bonded on the ceramic substrate through the second bump electrodes 311. The second bump electrode 311 may be formed by an etching process, and has a height of about 3 μm and a surface plated with an alloy solder layer of about 2 μm.
The isolation insulating layer 33 is used to realize isolation and insulation of the driving chip 32 from the TIA chip 34. The isolation insulating layer 33 is disposed above the driving chip 32, and both ends of the isolation insulating layer are recessed downward, and the isolation insulating layer 33 is connected to the second bump electrodes 311 on the ceramic substrate, which are disposed on both sides of the driving chip 32, through the recessed structures on both ends of the isolation insulating layer 33. When the isolation insulating layer 33 is connected to the ceramic substrate, the isolation insulating layer 33 may be placed above the ceramic substrate, so that the recessed structure is just sleeved outside the corresponding second protruding electrode 311, pre-cured, and then a small amount of conductive adhesive is injected between the recessed structure and the ceramic substrate, and finally reflow soldering is performed.
Thus, the isolation insulating layer 33 can be made to escape from the driver chip 32 below. Meanwhile, the top surface of the isolation insulating layer 33 is further provided with a plurality of third bump electrodes 331, and the TIA chip 34 is configured to perform transimpedance amplification on the output electrical modulation signal to obtain a voltage signal. The TIA chip 34 is flip-chip bonded on the isolation insulating layer 33 through the third bump electrodes 331. When the TIA chip 34 is mounted, the isolation insulating layer 33 is fixed through a corresponding jig, the flip chip technology is also adopted, the array of the TIA chip 34 electrodes and the array of the third bump electrodes 331 of the isolation insulating layer 33 are aligned, and then eutectic mounting is performed.
The sealing layer 35 is used for packaging the driving chip 32, the isolation insulating layer 33 and the TIA chip 34. In this embodiment, the sealing layer 35 may be a metal sealing cap disposed on the substrate layer 31, the driving chip 32, the isolation insulating layer 33, and the TIA chip 34 are packaged in the metal sealing cap, and the metal sealing cap is further filled with a thermal conductive adhesive, which is a silica gel satisfying high insulation, low dielectric constant, and high thermal conductivity. This is advantageous in improving the heat dissipation performance of the electrical chip assembly 30. Correspondingly, the top of the metal sealing cap is provided with a glue injection hole. At the moment, pouring encapsulation silica gel from the glue injection hole on one side of the glass substrate, filling the whole space, and then curing.
In addition, the high density CPO silicon light engine also includes a sealing cover 50. The sealing cover 50 is disposed on the circuit substrate 10, the optical chip 20, the electrical chip assembly 30 and the optical coupling assembly 40 are packaged in the sealing cover 50, and the sealing cover 50 is further filled with a thermal conductive adhesive. Correspondingly, the sealing cover 50 is also provided with glue injection holes.
To sum up, the utility model provides a high-density CPO silicon photo engine based on 3D stereoscopic packaging through carrying out three-dimensional stereoscopic packaging with circuit substrate, optical chip, electricity chip subassembly, can make CPO silicon photo engine transmission bandwidth increase one time, solves the problem that the connected mode of photoelectricity chip leads to high frequency signal distortion, low bandwidth in the 2D packaging technology simultaneously.
Meanwhile, the electrical chip assembly is designed in a layered mode, so that the driving chip and the TIA chip are sealed in an overlapping mode, space is saved, and meanwhile heat dissipation of the TIA chip is not affected. In addition, the metal sealing cap is adopted for the electrical chip assembly, and the heat conducting glue is filled in the metal sealing cap, so that the heat dissipation performance of the electrical chip assembly is improved.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A high-density CPO silicon light engine, comprising: a circuit substrate, an optical chip, an electrical chip assembly and an optical coupling assembly;
the top surface of the circuit substrate is provided with a first groove, the optical chip is arranged in the first groove and forms a height difference with the circuit substrate, and the height difference is suitable for the optical chip and the circuit substrate to be connected through wire bonding;
the optical chip comprises an optical chip and an electrical chip component, wherein the optical chip is arranged on the optical chip, the electrical chip component is arranged in the second groove in a flip-chip manner, and the optical coupling component is arranged on the other side area of the top surface of the optical chip.
2. The high density CPO silicon light engine as claimed in claim 1, wherein the optical chip is plural, and plural optical chips are commonly disposed in the first recess or disposed in respective first recesses, and the electrical chip assembly is disposed in the second recess of any one of the optical chips.
3. A high density CPO silicon light engine as claimed in claim 1, wherein said second recess further has a plurality of first bump electrodes disposed therein, said plurality of first bump electrodes being disposed in correspondence with said array of electrodes on said electrical chip assembly.
4. A high density CPO silicon light engine as claimed in claim 1 or 3, wherein the electrical chip assembly and the optical chip are further filled with an insulating thermal conductive adhesive.
5. A high density CPO silicon light engine as claimed in claim 1, wherein said electrical chip assembly comprises, in order from bottom to top: the circuit board comprises a substrate layer, a driving chip, an isolation insulating layer, a TIA chip and a sealing layer.
6. The high-density CPO silicon light engine as claimed in claim 5, wherein the substrate layer is a ceramic substrate, through holes are formed in the ceramic substrate, the through holes and the lower surface of the ceramic substrate are provided with gold plating layers, the upper surface of the ceramic substrate is further provided with a plurality of second bump electrodes, and the driving chip is flip-chip bonded on the ceramic substrate through the second bump electrodes.
7. The high-density CPO silicon light engine as claimed in claim 6, wherein the isolation insulating layer is disposed above the driving chip and has a downward recess at two ends, and the isolation insulating layer is connected to the second bump electrodes on the ceramic substrate at two sides of the driving chip via the recess structures at two ends.
8. The high-density CPO silicon light engine of claim 7, wherein the top surface of the isolation insulating layer is further provided with a plurality of third bump electrodes, and the TIA chip is flip-chip bonded on the isolation insulating layer through the plurality of third bump electrodes.
9. The high-density CPO silicon light engine as claimed in claim 5, wherein the sealing layer is a metal sealing cap disposed on the substrate layer, the driver chip, the isolation insulating layer and the TIA chip are packaged in the metal sealing cap, and the metal sealing cap is further filled with a thermal conductive adhesive.
10. A high density CPO silicon light engine as recited in claim 1, wherein said optical coupling component is one of a grating coupling component, an end-face coupling component and a V-groove passive coupling component.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121895317.8U CN215297764U (en) | 2021-08-13 | 2021-08-13 | High-density CPO silicon optical engine |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121895317.8U CN215297764U (en) | 2021-08-13 | 2021-08-13 | High-density CPO silicon optical engine |
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| CN215297764U true CN215297764U (en) | 2021-12-24 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113534366A (en) * | 2021-08-13 | 2021-10-22 | 亨通洛克利科技有限公司 | High-density CPO silicon optical engine |
| CN114371537A (en) * | 2022-02-17 | 2022-04-19 | Nano科技(北京)有限公司 | Split type integrated packaging optical module |
-
2021
- 2021-08-13 CN CN202121895317.8U patent/CN215297764U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113534366A (en) * | 2021-08-13 | 2021-10-22 | 亨通洛克利科技有限公司 | High-density CPO silicon optical engine |
| CN114371537A (en) * | 2022-02-17 | 2022-04-19 | Nano科技(北京)有限公司 | Split type integrated packaging optical module |
| CN114371537B (en) * | 2022-02-17 | 2024-06-25 | Nano科技(北京)有限公司 | Split type integrated packaging optical module |
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Address after: No. 168 Jiaotong North Road, Wujiang Economic and Technological Development Zone, Suzhou City, Jiangsu Province Patentee after: Suzhou Zhuoyu Photon Technology Co.,Ltd. Address before: 215200 Hengdao 88, Wujiang Economic and Technological Development Zone, Suzhou City, Jiangsu Province Patentee before: HENGTONG ROCKLEY TECHNOLOGY Co.,Ltd. |