CN111596494B - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
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- CN111596494B CN111596494B CN202010433344.7A CN202010433344A CN111596494B CN 111596494 B CN111596494 B CN 111596494B CN 202010433344 A CN202010433344 A CN 202010433344A CN 111596494 B CN111596494 B CN 111596494B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/133711—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by organic films, e.g. polymeric films
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
Abstract
The application discloses an array substrate and a preparation method thereof, wherein the array substrate comprises a first substrate; the color resistance layer is arranged above the first substrate, the color resistance layer is a matrix with a plurality of color resistance units arranged, and the color resistance units arranged on the side of the matrix are positioned on the same horizontal plane on the surface of one side far away from the first substrate; and the PI layer is arranged on one side surface of the color resistance layer, which is far away from the first substrate. The application has the beneficial effects that: according to the array substrate and the preparation method thereof, the thickness of the part of the first insulating layer in the array substrate is reduced, so that the height difference between the color resistance units close to the non-display area is reduced, the PI solution is conveniently coated, PI is prevented from accumulating at the joint of the adjacent color resistance units, poor display caused by accumulation of the PI solution at the non-display area of the display panel is avoided, the position of the retaining wall is moved to the side close to the display area, the risk of frame glue fracture is reduced, the service life of the display panel is prolonged, and the product quality is improved.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate and a preparation method thereof.
Background
One of the main causes of the dot-like defects at the periphery of the display Panel is that the peripheral local Cell thickness (Cell Gap), pretilt angle and surface are different due to the accumulation of the Panel periphery PI (polyimide inkjet film) or uneven PI distribution, so that the Panel periphery transmittance is larger or smaller, and bright state (Gap/pretilt angle is larger) or dark point (Gap/pretilt angle is smaller) is displayed.
With the development of TFT LCD industry, the demands of customers on the narrow frames/no frames of the TFT LCD are obviously improved, and meanwhile, the precision demands of the narrowed frames of the TFT LCD on PI are also improved, because of the difference of the layout of peripheral circuits of the TFT LCD, the local uneven diffusion of PI is caused to have dot-shaped defects, the quality of products is reduced, and the selling price of the products and the satisfaction of the customers are influenced.
At present, the countermeasure for improving the peripheral spot defect is mainly to cover the design by sticking the anti-light leakage adhesive tape, PI and the spacing columns, so that the peripheral defect cannot be solved fundamentally or the cost can be increased.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which are used for solving the technical problem that PI (polyimide) arranged on a color resistance unit is easy to accumulate due to different thicknesses of the color resistance unit in a display panel in the prior art, so that poor display of the display panel is caused.
In order to solve the technical problems, the application provides an array substrate, which comprises a first substrate; the color resistance layer is arranged above the first substrate, the color resistance layer is a matrix with a plurality of color resistance units arranged, and the color resistance units arranged on the side of the matrix are positioned on the same horizontal plane on the surface of one side far away from the first substrate; and the PI layer is arranged on one side surface of the color resistance layer away from the first substrate.
Further, the array substrate further comprises a retaining wall, wherein the retaining wall is arranged on one side surface of the first substrate and is arranged on the side of the color resistance layer; and the frame glue is arranged on one side of the retaining wall, which is far away from the color resistance layer, and is arranged on the surface of one side of the first substrate.
Further, the distance between the retaining wall and the display area is L1, the distance between the frame glue and the display area is L2, and the ratio of L2 to L1 is 2-3.
Furthermore, a gap is formed between the retaining wall and the color resistance layer, and the PI layer is arranged in the gap.
Further, the array substrate further comprises a thin film transistor structure, including a first metal layer, arranged on one side surface of the first substrate; the first insulating layer is arranged on one side surface of the first substrate and covers the first metal layer; the color resistance layer is arranged on the surface of one side of the thin film transistor structure, which is far away from the first substrate.
Further, the color resistance unit comprises a red color resistance unit, a green color resistance unit and a blue color resistance unit, wherein the thickness of the blue color resistance unit is larger than that of the red color resistance unit; the thickness of the blue resistance unit is larger than that of the blue resistance unit; the thickness of the part of the first insulating layer corresponding to the red color resistance unit at the side of the matrix is larger than that of the part of the first insulating layer corresponding to the blue color resistance unit at the side of the matrix; and the thickness of the part of the first insulating layer corresponding to the green resistance unit at the side of the matrix is larger than that of the part of the first insulating layer corresponding to the blue resistance unit at the side of the matrix.
Further, the array substrate further comprises a conductive layer, the conductive layer is arranged on the color resistance layer, and the PI layer covers the conductive layer.
Further, the method comprises the following steps: providing a first substrate; preparing a color resistance layer on the first substrate, wherein the color resistance layer is a matrix with a plurality of color resistance units arranged, and the color resistance units arranged on the side of the matrix are positioned on the same horizontal plane on the surface of one side far away from the first substrate; and preparing a PI layer on the color resistance layer, wherein the PI layer covers the conductive layer.
Further, after the step of preparing the first substrate, the method further includes the steps of: preparing a thin film transistor structure on the first substrate, wherein the preparation step of the thin film transistor structure comprises the following steps: preparing a first metal layer on the substrate; preparing a first insulating layer on the substrate, wherein the first insulating layer covers the first metal layer; and reserving part of the first insulating layers, and etching the rest of the first insulating layers, wherein the reserved first insulating layers correspond to the color resistance units at the side of the color resistance layers.
Further, the color resistance unit comprises a red color resistance unit, a green color resistance unit and a blue color resistance unit, wherein the first insulating layer corresponding to the red color resistance unit at the side of the color resistance layer and the first insulating layer corresponding to the green color resistance unit at the side of the color resistance layer are not etched.
The application has the beneficial effects that: according to the array substrate and the preparation method thereof, the thickness of the part of the first insulating layer in the array substrate is increased, so that the height difference between the color resistance units close to the non-display area is reduced, the application of PI solution is facilitated, PI is prevented from accumulating at the joint of the adjacent color resistance units, the volume of PI solution flowing to the non-display area of the display panel is reduced, the phenomenon of poor display caused by PI solution accumulating at the non-display area of the display panel is avoided, the position of the retaining wall is moved to the side close to the display area, the risk of frame glue breakage is reduced, the service life of the display panel is prolonged, and the product quality is improved.
Drawings
The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a top view of an array substrate in an embodiment.
Fig. 2 is a partial side view of a display panel in an embodiment.
Fig. 3 is a partial side view of the direction a of fig. 1.
Fig. 4 is a partial side view of the direction C of fig. 1.
Reference numerals in the figures
10 array base plate; 20 color film substrates;
101 a first substrate;
102 a color resistance layer; 103 color resistance units;
104 a first conductive layer; 105 a first PI layer;
106 retaining walls; 107 frame glue;
108 a thin film transistor structure; 11 display area;
12 non-display area; 1081 pixel electrodes;
1082 storage capacitance; a second substrate 201;
202 a light shielding layer; 203 a second conductive layer;
204 a second PI layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
Examples
As shown in fig. 1 and 2, in the present embodiment, the display panel of the present application includes an array substrate 10 and a color film substrate 20, wherein the array substrate 10 includes a first substrate 101, a color resist layer 102, a first conductive layer 104, a first PI layer 105, a retaining wall 106, a frame glue 107, and a thin film transistor structure 108.
The display panel comprises a display area 11 and a non-display area 12, wherein the non-display area 12 surrounds the display area 11.
The first substrate 101 is a hard glass substrate for receiving each film layer and blocking external moisture from penetrating into the display panel.
The thin film transistor structure 108 is disposed on one side surface of the first substrate 101, wherein the thin film transistor structure 108 includes a pixel electrode 1081 and a storage capacitor 1082.
The storage capacitor 1082 includes a first metal layer, a first insulating layer and a second metal layer, where the first metal layer is disposed on a side surface of the first substrate 101, the first insulating layer is disposed on a side surface of the first substrate 101 and covers the first metal layer, the second metal layer is disposed on a side surface of the first insulating layer away from the first metal layer, and the first metal layer and the second metal layer that are disposed opposite to each other can store the capacitor, so as to keep the display screen of the display panel until the next charge, and realize continuous display of the display panel.
As shown in fig. 3 and fig. 4, the resistive layer 102 is disposed on a surface of the thin film transistor structure 108, which is far away from the first substrate 101, wherein the resistive layer 102 includes a plurality of color resistive units 103 arranged in an array, and the color resistive units 103 are distributed in a matrix manner to realize color display of the display panel.
The color block unit 103 includes a red color block unit, a blue color block unit and a green color block unit, and generally, the blue color block thickness is higher than the red color block thickness and the green color block thickness, so as to adjust the chromatic aberration caused by different wavelengths.
The red color resistance units, the blue color resistance units and the green color resistance units are distributed in rows and columns, the colors of two adjacent first color resistance units are the same on the same column, and the red color resistance units, the blue color resistance units and the green color resistance units are distributed at intervals on the same row.
The first conductive layer 104 is disposed on a surface of the color resist layer 102 away from the tft structure 108 for transmitting electrical signals.
The first PI layer 105 is disposed on a side surface of the first conductive layer 104 away from the color resistance layer 102, because the PI layer is generally made by coating, if there is a step difference between the color resistance units, PI liquid is easy to accumulate, and because of the liquid characteristic, PI liquid on a higher color resistance unit surface flows to a lower color resistance unit surface, which causes the PI solution to be lacking on the higher color resistance unit surface, so that a continuous first PI layer 105 cannot be formed, or, in order to ensure that PI solution is present on the higher color resistance unit surface, a large amount of PI solution needs to be coated, so that PI liquid overflows around the real panel 1, and is accumulated at a sparse line position around the display panel, thereby causing abnormal display of the display panel.
To solve this problem, in the present embodiment, the step difference between the red color resist unit, the blue color resist unit and the green color resist unit in the color resist unit 103 of the color resist layer 102 near the non-display area 12 is reduced, so that the surface of the area of the color resist layer 102 near the non-display area 12 is flat, and the accumulation of PI solution therein is reduced. Specifically, the thickness of the first insulating layer corresponding to the blue resistive element is reduced, the reduced thickness is the thickness difference between the blue resistive element and the red resistive element, in this embodiment, the thickness of the red resistive element is the same as the thickness of the green resistive element, so that the surface of the blue resistive element on the side far from the first substrate 101 is flush with the surface of the red resistive element and the surface of the green resistive element on the side far from the first substrate 101, in other preferred embodiments of the present application, the thicknesses of the red resistive element and the green resistive element are different, the thickness of the first insulating layer corresponding to the red resistive element is reduced by the thicker color group element in the red resistive element and the green resistive element, and the reduced thickness is the thickness difference between the blue resistive element and the green resistive element or the red resistive element, so that the surface of the green resistive element on the side far from the first substrate 101 is flush with the surface of the blue resistive element on the side far from the first substrate 101, that is the area of the color resistive layer 102 near the non-display area 12 is a smooth plane, so that the PI layer 105 is not stacked on the edge of the non-display area 12.
In this embodiment, by changing the thickness of a portion of the first insulating layer, under the condition that the thickness of each color resistor unit 103 is not changed, one side of the color resistor unit 103 away from the first substrate 101 is located on the same plane, so that the display quality of the display panel is not affected at the same time for convenience of manufacturing process, and only the thickness of the first insulating layer corresponding to the width of two or three color resistor units 103 at the position where the color resistor layer 102 is close to the non-display area 12, that is, the width of two or three color resistor units 103 at the side of the color resistor layer 102 is changed, so that PI is not stacked in the non-display area 12 of the display panel.
In order to better explain the application, the embodiment also provides a preparation method of the array substrate, which comprises the steps of S1-S5.
S1 provides a first substrate.
S2, preparing a thin film transistor structure on the first substrate.
S3, preparing a color resistance layer on the thin film transistor structure, wherein the color resistance layer is a matrix with a plurality of color resistance units arranged, and the color resistance units arranged on the side of the matrix are positioned on the same horizontal plane on the surface of one side of the color resistance units far away from the first substrate.
S4, preparing a conductive layer on the color resistance layer.
S5, preparing a PI layer on the color resistance layer, wherein the PI layer covers the conductive layer.
In the step S2, the preparation step of the thin film transistor structure includes: a first metal layer is prepared on the substrate. And preparing a first insulating layer on the substrate, wherein the first insulating layer covers the first metal layer. And reserving part of the first insulating layers, and etching the rest of the first insulating layers, wherein the reserved first insulating layers correspond to the color resistance units at the side of the color resistance layers. And depositing an amorphous silicon semiconductor layer and a source-drain electrode layer on the first insulating layer, wherein the amorphous silicon semiconductor layer adopts chemical vapor deposition (Chemical Vapor Deposition, CVD), and the source-drain metal layer adopts physical vapor deposition (Physical Vapor Deposition, PVD) to form a film.
The color resistance unit comprises a red color resistance unit, a green color resistance unit and a blue color resistance unit, wherein the first insulating layer corresponding to the red color resistance unit at the side of the color resistance layer and the first insulating layer corresponding to the green color resistance unit at the side of the color resistance layer are not etched.
The color film substrate 20 is disposed opposite to the array substrate 10, where the color film substrate 20 includes a second substrate 201, a light shielding layer 202, a second conductive layer 203, and a second PI layer 204.
The second substrate 201 is a hard glass substrate for receiving each film layer and blocking external moisture from invading the display panel.
The light shielding layer 202 is disposed on a side surface of the second substrate 202, which is close to the array substrate 10, and the light shielding layer 202 includes a plurality of light shielding units, wherein the light shielding units are disposed at the seams between the non-display area and the adjacent color set units, and are used for shielding light and preventing light leakage of the display panel.
The second conductive layer 203 is disposed on a side surface of the second substrate 201 near the array substrate 10 and covers the light shielding layer 202, the second PI layer 204 is disposed on a side surface of the second conductive layer 203 near the array substrate 10, the first PI layer 105 and the second PI layer 204 are both alignment films, the first PI layer 105 is provided with a plurality of optical axes parallel to each other for transmitting light beams of a fixed angle, the second PI layer 204 is provided with a plurality of optical axes parallel to each other and perpendicular to the optical axes on the first PI layer 105 for transmitting light beams of a fixed angle, in this embodiment, the display panel is a liquid crystal display panel, after the first conductive layer 104 and the second conductive layer 203 are electrified, an electric field is formed between the first conductive layer 104 and the second conductive layer 203, and the liquid crystal can deflect under the action of the electric field, so that the light beams originally perpendicular to the optical axes on the second PI layer 204 deflect and then transmit the first PI layer 204.
The retaining wall 106 is disposed in the non-display area 12, and a gap is formed between the retaining wall 106 and the side surface of the color resist layer 102, wherein the gap is used for accommodating the PI solution overflowed from the color resist layer 102.
The frame glue 107 is disposed in the non-display area 12 and on a side of the retaining wall 106 away from the color resist layer 102, and is disposed between the array substrate 10 and the color film substrate 20, for supporting the array substrate 10 and the color film substrate 20, so as to ensure that the thickness of the display panel is uniform.
Because the color resistance layer 102 adopts the method of etching the thickness of the first insulating layer, the first PI layer 105 can be gently coated on the color resistance layer 102, so that the flow rate of the PI solution overflowing between the retaining wall 106 and the color resistance layer 102 becomes low, in this embodiment, the distance between the retaining wall 106 and the display area 11 is 1600um, in other preferred embodiments of the present application, the distance between the retaining wall 106 and the display area 11 is 160um, the ratio of the distance between the side surface of the retaining wall 106 and the color resistance layer 102 to the distance between the frame glue 107 and the color resistance layer 102 is 1:3, and the retaining wall 106 moves from the position originally close to the frame glue 107 to the direction of the display area 11, thereby effectively avoiding the fracture risk caused to the frame glue due to the external force effect in the use process of the display panel, and improving the service life of the display panel.
The array substrate and the preparation method thereof have the beneficial effects that the thickness of part of the first insulating layer in the array substrate is increased, so that the height difference between color resistance units close to the non-display area is reduced, the PI solution is conveniently coated, PI is prevented from accumulating at the joint of adjacent color resistance units, the volume of PI solution flowing to the non-display area of the display panel is reduced, the phenomenon of poor display caused by accumulation of the PI solution at the non-display area of the display panel is avoided, the position of the retaining wall is moved to the side close to the display area, the risk of frame glue breakage is reduced, and the service life of the display panel is prolonged.
The above description of the embodiments is only for helping to understand the technical solution of the present application and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (9)
1. An array substrate is characterized by comprising a display area and a non-display area, and comprises
A first substrate;
the color resistance layer is arranged above the first substrate, the color resistance layer is a matrix with a plurality of color resistance units arranged, the color resistance layer is not arranged in the non-display area, two or three color resistance units which are arranged on the side of the matrix and are close to the non-display area are arranged on the same horizontal plane, the surfaces of one sides of the color resistance units which are far away from the first substrate are arranged on the other areas, and the surfaces of one sides of the color resistance units which are far away from the first substrate are not arranged on the same horizontal plane; and
and the PI layer is arranged on the surface of one side of the color resistance layer away from the first substrate.
2. The array substrate of claim 1, further comprising
The retaining wall is arranged on one side surface of the first substrate and on the side of the color resistance layer; and
and the frame glue is arranged on one side of the retaining wall, which is far away from the color resistance layer, and is arranged on the surface of one side of the first substrate.
3. The array substrate of claim 2, wherein,
the distance between the retaining wall and the display area is L1, the distance between the frame glue and the display area is L2, and the ratio of L2 to L1 is 2-3.
4. The array substrate of claim 2, wherein,
a gap is formed between the retaining wall and the color resistance layer, and the PI layer is arranged in the gap.
5. The array substrate of claim 1, further comprising
A thin film transistor structure includes
The first metal layer is arranged on one side surface of the first substrate; and
the first insulating layer is arranged on one side surface of the first substrate and covers the first metal layer;
the color resistance layer is arranged on the surface of one side of the thin film transistor structure, which is far away from the first substrate.
6. The array substrate of claim 5, wherein,
the color resistance unit comprises a red color resistance unit, a green color resistance unit and a blue color resistance unit, wherein the thickness of the blue color resistance unit is larger than that of the red color resistance unit; the thickness of the blue resistance unit is larger than that of the green resistance unit;
the thickness of the part of the first insulating layer corresponding to the red color resistance unit at the side of the matrix is larger than that of the part of the first insulating layer corresponding to the blue color resistance unit at the side of the matrix; and
the thickness of the first insulating layer corresponding to the green resistance unit at the side of the matrix is larger than that of the first insulating layer corresponding to the blue resistance unit at the side of the matrix.
7. The array substrate of claim 5, further comprising
And the conductive layer is arranged on the color resistance layer, and the PI layer covers the conductive layer.
8. The preparation method of the array substrate is characterized in that the array substrate comprises a display area and a non-display area, and comprises the following steps:
providing a first substrate;
preparing a color resistance layer on the first substrate, wherein the color resistance layer is a matrix with a plurality of color resistance units arranged, and the color resistance layer is not arranged in the non-display area, wherein two or three color resistance units which are arranged on the side of the matrix and are close to the non-display area are arranged on the same horizontal plane on the surface of one side of the color resistance layer, which is far away from the first substrate, and all color resistance units which are arranged in other areas are not arranged on the same horizontal plane on the surface of one side of the color resistance unit, which is far away from the first substrate;
preparing a conductive layer on the color resistance layer;
and preparing a PI layer on the color resistance layer, wherein the PI layer covers the conductive layer.
9. The method of manufacturing an array substrate according to claim 8, further comprising, after the step of manufacturing the first substrate, the steps of:
preparing a thin film transistor structure on the first substrate, wherein the preparation step of the thin film transistor structure comprises the following steps:
preparing a first metal layer on the substrate;
preparing a first insulating layer on the substrate, wherein the first insulating layer covers the first metal layer;
and etching the rest of the first insulating layers by reserving part of the first insulating layers, wherein the color resistance unit comprises a red color resistance unit, a green color resistance unit and a blue color resistance unit, and the first insulating layers corresponding to the red color resistance units at the side of the color resistance layer and the first insulating layers corresponding to the green color resistance units at the side of the color resistance layer are not etched.
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