CN112259561A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN112259561A CN112259561A CN202011170942.6A CN202011170942A CN112259561A CN 112259561 A CN112259561 A CN 112259561A CN 202011170942 A CN202011170942 A CN 202011170942A CN 112259561 A CN112259561 A CN 112259561A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
Abstract
The array substrate and the display panel disclosed by the application comprise a substrate, a buffer layer, a source drain layer, an inorganic insulating layer and a packaging layer, wherein the inorganic insulating layer comprises a first area and a second area; the second area comprises a first sub-partition and a second sub-partition, the first sub-partition is provided with a plurality of switching holes, and the second sub-partition is provided with signal diffusion lines; the first sub-partition is arranged on one side, close to the first area, of the second area, and the gradient of the transfer hole is between 30 degrees and 60 degrees, or the second sub-partition is arranged on one side, close to the first area, of the second area; the slope of the transfer hole is changed to make the transfer hole smooth or change the position of the second sub-partition, so that the technical problems that the display brightness of the liquid crystal display panel is different and traces appear due to the fact that PI is stacked in the display area are solved.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate and a display panel.
Background
At present, a common electrode signal line needs to be added to the periphery of an external (Add On) product Thin Film Transistor (TFT) in a display (Active Area, AA) Area, that is, a via hole penetrating through an inorganic insulating layer is formed On the inorganic insulating layer covering a Source Drain electrode, and a common electrode (COM) layer located above the inorganic insulating layer is connected to a Source Drain electrode (SD) layer located below the inorganic insulating layer through the via hole, so as to achieve the purpose of signal connection.
However, since the design position of the current switch hole is close to the AA region, the close arrangement of the switch holes prevents the normal diffusion of the Photoresist (PI), the PI liquid accumulation phenomenon is easily formed, and the PI liquid easily enters the AA region to form stacking, thereby causing the display brightness of the display panel to be uneven and various traces to appear.
Therefore, how to solve the technical problems that the PI accumulation is caused by the connection holes in the conventional array substrate, and further the display brightness of the display panel is not uniform, and various traces appear is a difficult problem in the effort of panel manufacturers at present.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel, and the technical problems that PI accumulation is caused by a transfer hole in the existing array substrate, the display brightness of a liquid crystal display panel is uneven, and various trace phenomena are caused can be solved.
The embodiment of the application provides an array substrate, array substrate includes interconnect's display area and non-display area, non-display area sets up the one end in display area, just array substrate includes:
a substrate;
a buffer layer disposed on the substrate;
the source drain layer is arranged on the buffer layer;
the inorganic insulating layer is arranged on the source drain electrode layer and comprises a first area and a second area which are mutually connected, the first area corresponds to the display area, and the second area corresponds to the non-display area; wherein the content of the first and second substances,
the second area comprises a first sub-partition and a second sub-partition which are connected with each other, the first sub-partition is provided with a plurality of switching holes, and the second sub-partition is provided with signal diffusion lines; the first sub-partition is arranged on one side, close to the first zone, of the second zone, the gradient of the transfer hole is between 30 degrees and 60 degrees, and a drainage groove is formed in one end, close to the first zone, of the transfer hole, so that photoresist liquid flows into the transfer hole, or the second sub-partition is arranged on one side, close to the first zone, of the second zone;
and the packaging layer is arranged on the inorganic insulating layer.
In the array substrate provided by the embodiment of the present application, a length of one end of the via hole near the first region is not greater than 30 micrometers.
In the array substrate provided by the embodiment of the application, the pitch of the adjacent transfer holes is not less than 30 micrometers.
In the array substrate provided by the embodiment of the application, the width of the cross section of the through hole is not less than 4 microns.
In the array substrate provided by the embodiment of the application, the gradient of the drainage groove is smaller than that of the transfer hole and is located between 30 degrees and 60 degrees.
In the array substrate that this application embodiment provided, still include the guide plate, the guide plate sets up the switching hole is close to the one end in first district, just the guide plate is close to one side of switching hole with the switching hole is close to one side coincidence of guide plate.
In the array substrate provided by the embodiment of the application, one end of the guide plate, which is close to the display area, is a vertex or a straight line; wherein the content of the first and second substances,
when one end of the guide plate close to the display area is a vertex, the guide plate is in a circular arc shape, an elliptic arc shape or a triangular shape;
when one end of the guide plate close to the display area is a straight line, the guide plate is trapezoidal and rectangular.
In the array substrate that this application embodiment provided, the shape of guide plate is triangle-shaped, the guide plate is including the first limit, second limit and the third limit that connect gradually, the third limit does the guide plate with the one side of switching hole coincidence, first limit is located with the second limit the guide plate is close to one side of first district, just first limit and second limit are alternately formed first contained angle, first contained angle is not more than 30 degrees.
In the array substrate that this application embodiment provided, the shape of guide plate is oval arc, the guide plate is including the fourth edge and the fifth edge that connect gradually, the fifth edge does the guide plate with the one side of switching hole coincidence, the fourth edge is the guide plate is close to the oval arc limit of first district, just the fourth edge is close to the summit of first district arrives the distance on fifth edge with the ratio on fifth edge is not less than 1.5: 1.
The application also provides a display panel, which comprises an array substrate, wherein the array substrate is the array substrate.
In the array substrate and the display panel provided by the embodiment of the application, the slope of the switching hole is adjusted to be gentle or the positions of the first sub-partition and the second sub-partition are adjusted, and the second sub-partition is positioned on one side of the second area close to the first area, so that in the process of PI coating, the switching hole cannot have the defect of blocking PI diffusion, and further, the phenomenon that the display brightness of the liquid crystal display panel is uneven and various marks are generated due to the fact that the PI is stacked in the display area is prevented.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
Fig. 2 is a schematic view of a first structure of an inorganic insulating layer according to an embodiment of the present disclosure.
Fig. 3 is a schematic view of a second structure of the inorganic insulating layer according to the embodiment of the present application.
Fig. 4 is a schematic view of a third structure of the inorganic insulating layer according to the embodiment of the present application.
Fig. 5 is a fourth structural diagram of an inorganic insulating layer according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of a fifth structure of the inorganic insulating layer according to the embodiment of the present application.
Fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "length," "width," "thickness," "upper," "lower," and the like, as used herein, refer to an orientation or positional relationship as shown in the drawings, which is used for convenience in describing the present application and to simplify the description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be taken as limiting the present application. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between.
Specifically, referring to fig. 1, fig. 1 is a schematic structural diagram of an array substrate 10 according to an embodiment of the present disclosure. As shown in fig. 1, the array substrate 10 provided in the embodiment of the present application includes a display area 10a and a non-display area 10b connected to each other, and the non-display area 10b is disposed at one end of the display area 10 a. The array substrate 10 includes a substrate 101, a buffer layer 102, a source/drain layer 103, an inorganic insulating layer 104, and an encapsulation layer 105. The buffer layer 102 is disposed on the substrate 101, the source drain layer 103 is disposed on the buffer layer 102, the inorganic insulating layer 104 is disposed on the source drain layer 103, and the encapsulation layer 105 is disposed on the inorganic insulating layer 104.
The inorganic insulating layer 104 includes a first region 1041 and a second region 1042 connected to each other, the first region 1041 corresponds to the display region 10a, and the second region 1042 corresponds to the non-display region 10 b. The second region 1042 includes a first sub-partition 1042a and a second sub-partition 1042b connected to each other, and the first sub-partition 1042a is disposed on a side of the second region 1042 close to the first region 1041. The first sub-partition 1042a is provided with a plurality of through holes 10421, one end of the through hole 10421 close to the first region 1041 is provided with a drainage slot 10422, and the second sub-partition 1042b is provided with a signal diffusion line 10423.
Here, the common electrode layer is disposed on the inorganic insulating layer 104, and therefore, it is necessary to provide a via hole 10421 for connecting the common electrode layer with the source/drain electrode layer 103 on the inorganic insulating layer 104.
In addition, the drainage groove 10422 is disposed at an end of the adapting hole 10421 close to the first zone 1041 to facilitate drainage of the photoresist solution into the adapting hole 10421.
The slope of the through hole 10421 is between 30 degrees and 60 degrees, and specifically, the slope of the through hole 10421 may be 30 degrees, 40 degrees, 50 degrees, or 60 degrees.
The slope of the adapting hole 10421 is set to be gentle, which is beneficial to the photoresist liquid flowing into the adapting hole 10421. Therefore, the photoresist solution is not blocked by the edge of the through hole 10421 to form a backflow in the coating process, and the photoresist is not accumulated at the boundary of the first region 1041 and the first region 1042. Therefore, the technical problems that the display brightness of the liquid crystal display panel is not uniform and various trace phenomena occur due to the fact that photoresist liquid is accumulated at the junction of the first zone 1041 and the first zone 1042 can be solved.
Wherein, in one embodiment, the slope of the drainage slot 10422 is less than the slope of the through hole 10421 and is between 30 degrees and 60 degrees. The slope of the drainage groove 10422 is smaller than the slope of the through hole 10421, which is more favorable for the drainage groove 10422 to drain the photoresist solution to the through hole 10421.
Specifically, referring to fig. 2, fig. 2 is a schematic view of a first structure of the inorganic insulating layer 104 according to the embodiment of the present disclosure, and as shown in fig. 2, the inorganic insulating layer 104 according to the embodiment of the present disclosure includes a first region 1041 and a second region 1042, which are connected to each other. The second region 1042 includes a first sub-partition 1042a and a second sub-partition 1042b connected to each other, and the first sub-partition 1042a is disposed on a side of the second region 1042 close to the first region 1041. The first sub-partition 1042a is provided with a plurality of switch holes 10421, and the second sub-partition 1042b is provided with a signal diffusion line 10423.
The length of the end of the via hole 10421 close to the first region 1041 is not greater than 30 microns, and specifically, the length of the end of the via hole 10421 close to the first region 1041 may be 4 microns, 10 microns, 16 microns, 22 microns, or 30 microns.
In the process of coating the photoresist, the direction from the display region to the non-display region is generally used as the printing direction, and for the purposes of this application, the direction perpendicular to the boundary between the first region 1041 and the second region 1042 is the printing direction of the photoresist in the coating process.
The end of the via hole 10421 perpendicular to the printing direction of the photoresist solution may have a certain influence on the coating of the photoresist solution. Therefore, as the length of the end of the adapting hole 10421 perpendicular to the printing direction of the photoresist solution increases, the adapting hole 10421 has an increasing influence on the coating of the photoresist solution. Therefore, the influence of the via hole 10421 on the coating of the photoresist solution can be reduced by reducing the length of the via hole 10421 at the end perpendicular to the printing direction of the photoresist solution, that is, the length of the via hole 10421 at the end close to the first region 1041, so that the photoresist solution can be prevented from accumulating at the boundary between the first region 1041 and the first region 1042. In addition, the shorter the length of the end of the via hole 10421 near the first region 1041, the less the via hole 10421 affects the photoresist coating.
In addition, when the direction parallel to the boundary between the first region 1041 and the second region 1042 is the printing direction of the photoresist solution during the coating process, the length of the end of the via hole 10421 perpendicular to the boundary between the first region 1041 and the second region 1042 needs to be reduced to achieve the effect of preventing the photoresist solution from accumulating at the edge of the via hole 10421.
The pitch of the adjacent via holes 10421 is not less than 30 micrometers, and specifically, the pitch of the adjacent via holes 10421 may be 30 micrometers, 45 micrometers, or 60 micrometers.
When the photoresist is applied to the area between the adjacent through holes 10421, if the distance between the adjacent through holes 10421 is too small, the side edges of the through holes 10421 may limit the application of the photoresist, so that the distance between the adjacent through holes 10421 needs to be increased to prevent the side edges of the through holes 10421 from obstructing the application of the photoresist.
The width of the cross section of the through hole 10421 is not less than 4 micrometers, and specifically, the width of the cross section of the through hole 10421 may be 4 micrometers, 6 micrometers, or 8 micrometers.
The via hole 10421 is formed by an exposure process, and if the width of the via hole 10421 is smaller than 4 microns, the via hole 10421 cannot be formed by the exposure process, so that the width of the via hole 10421 is not smaller than 4 microns.
Specifically, referring to fig. 3, fig. 3 is a schematic view of a second structure of the inorganic insulating layer 104 provided in the embodiment of the present disclosure, as shown in fig. 3, the difference between the inorganic insulating layer 104 provided in the embodiment of the present disclosure and the inorganic insulating layer 104 provided in fig. 2 is that a diversion plate 10424 is disposed at one end of the adapting hole 10421 close to the first region 1041, and one side of the diversion plate 10424 close to the adapting hole 10421 coincides with one side of the adapting hole 10421 close to the diversion plate 10424. The shape of the diversion plate 10424 is triangle, the diversion plate 10424 includes a first side 10424a, a second side 10424b and a third side 10424c that connect gradually, the third side c is the one side that diversion plate 10424 and switching hole 10421 coincide, first side 10424a and second side 10424b are located the one side that the diversion plate 10424 is close to first district 1041, and first side 10424a and second side 10424b intersect and form first contained angle 10424 d.
Wherein the shape of the diversion plate 10424 is triangular. Therefore, in the process of coating the photoresist solution, the photoresist solution flows from the top of the diversion plate 10424 close to the first zone 1041, a part of the photoresist solution flows along the first edge 10424a and the second edge 10424b to the direction far away from the first zone 1041, a part of the photoresist solution flows into the inside of the adapting hole 10421 through the diversion plate 10424, and the tip of the diversion plate 10424, the first edge 10424a and the second edge 10424b play a role in guiding the flow of the photoresist solution, so as to prevent the photoresist solution from accumulating at the edge of the adapting hole 10421.
The first included angle 10424d is not greater than 30 degrees, and specifically, the angle of the first included angle 10424d may be 10 degrees, 20 degrees, or 30 degrees.
When the first included angle is greater than 30 degrees, the first edge 10424a and the second edge 10424b no longer play a role in guiding but play a role in blocking in the process of coating the photoresist solution. Therefore, the first included angle 10424d is not greater than 30 degrees, so as to prevent the first edge 10424a and the second edge 10424b from obstructing the photoresist solution phenomenon. In addition, the smaller the first included angle 10424d is, the larger the diversion function of the first edge 10424a and the second edge 10424b on the photoresist coating is.
Specifically, referring to fig. 4, fig. 4 is a schematic view of a third structure of the inorganic insulating layer 104 provided in the embodiment of the present disclosure, as shown in fig. 4, the difference between the inorganic insulating layer 104 provided in the embodiment of the present disclosure and the inorganic insulating layer 104 provided in fig. 2 is that a diversion plate 10424 is disposed at one end of the adapting hole 10421 close to the first region 1041, one side of the diversion plate 10424 close to the adapting hole 10421 is overlapped with one side of the adapting hole 10421 close to the diversion plate 10424, and the diversion plate 10424 is in an elliptical arc shape. The guide plate 10424 includes a fourth side 10424e and a fifth side 10424f that connect in proper order, and the fifth side 10424f is the one side that the guide plate 10424 coincides with the through-hole 10421, and the fourth side 10424e is the elliptic arc shape side that the guide plate 10424 is close to the first district 1041.
The fourth side 10424e is curved, so that the photoresist liquid can be guided to flow during the coating process of the photoresist liquid, and the photoresist liquid is prevented from accumulating at the edge of the through hole 10421.
The ratio of the distance from the vertex of the fourth side 10424e close to the first region 1041 to the fifth side 10424f is not less than 1.5: 1. Specifically, the ratio of the distance from the vertex of the fourth side 10424e close to the first region 1041 to the fifth side 10424f is 1.5:1, 2:1, or 3: 1.
The larger the ratio of the distance from the vertex of the fourth edge 10424e close to the first region 1041 to the fifth edge 10424f is, the larger the guiding effect of the fourth edge 10424e of the guide plate 10424 on the photoresist liquid flow is in the photoresist liquid coating process. Therefore, the ratio of the distance from the vertex of the fourth side 10424e close to the first region 1041 to the fifth side 10424f needs to be not less than 1.5: 1.
Specifically, referring to fig. 5, fig. 5 is a schematic diagram of a fourth structure of the inorganic insulating layer 104 provided in the embodiment of the present application, and as shown in fig. 5, the difference between the inorganic insulating layer 104 provided in the embodiment of the present application and the inorganic insulating layer 104 provided in fig. 2 is that a diversion plate 10424 is disposed at one end of the adapting hole 10421 close to the first region 1041, one side of the diversion plate 10424 close to the adapting hole 10421 coincides with one side of the adapting hole 10421 close to the diversion plate 10424, and the diversion plate 10424 is in the shape of an arc.
The guide plate 10424 includes a sixth side and a seventh side that are connected in sequence, the seventh side is a side where the guide plate 10424 coincides with the transfer hole 10421, and the sixth side is an arc-shaped side where the guide plate 10424 is close to the first region 1041. At this time, the sixth side is curved, so that a certain flow guiding effect can be exerted on the flow of the photoresist liquid in the process of coating the photoresist liquid, and the photoresist liquid is prevented from being accumulated at the edge of the adapting hole 10421.
In one embodiment, a ratio of a distance from a vertex of the sixth edge close to the first region 1041 to the seventh edge is not less than 1:1, and specifically, a ratio of a distance from a vertex of the sixth edge close to the first region 1041 to the seventh edge is 1:1, 2:1, or 3: 1.
The larger the ratio of the distance from the vertex of the sixth side close to the first area 1041 to the seventh side is, the larger the diversion effect of the outer side of the diversion plate 10424 on the flowing of the photoresist liquid is in the coating process of the photoresist liquid, so the ratio of the distance from the vertex of the sixth side close to the first area 1041 to the seventh side needs to be not less than 1: 1.
Specifically, referring to fig. 6, fig. 6 is a schematic diagram of a fifth structure of the inorganic insulating layer 104 provided in the embodiment of the present disclosure, as shown in fig. 6, the difference between the inorganic insulating layer 104 provided in the embodiment of the present disclosure and the inorganic insulating layer 104 provided in fig. 2 is that a diversion plate 10424 is disposed at one end of the adapting hole 10421 close to the first region 1041, one side of the diversion plate 10424 close to the adapting hole 10421 coincides with one side of the adapting hole 10421 close to the diversion plate 10424, and the diversion plate 10424 is in a trapezoid shape.
The side of the trapezoid can play a role in guiding the photoresist coating, so that the photoresist can flow into the through hole 10421.
In addition, the smaller the length of the side of the diversion plate 10424 close to the first region 1041, the more the trapezoidal side is shaken, and the greater the diversion function of the trapezoidal side is. Therefore, under the condition that the structural stability of the diversion plate 10424 is not affected, the length of the diversion plate 10424 close to the first region 1041 is reduced as much as possible, which is beneficial to diversion of the photoresist solution to the transfer hole 10421.
Specifically, referring to fig. 7, fig. 7 is a schematic structural diagram of another array substrate 20 provided in the embodiment of the present application, and as shown in fig. 7, the another array substrate 20 provided in the embodiment of the present application includes a display area 20a and a non-display area 20b connected to each other, and the non-display area 20b is disposed at one end of the display area 20 a. The array substrate 20 includes a substrate 201, a buffer layer 202, a source drain layer 203, an inorganic insulating layer 204, and an encapsulation layer 205. The buffer layer 202 is disposed on the substrate 201, the source drain layer 203 is disposed on the buffer layer 202, the inorganic insulating layer 204 is disposed on the source drain layer 203, and the encapsulation layer 205 is disposed on the inorganic insulating layer 204.
The inorganic insulating layer 204 includes a first region 2041 and a second region 2042 connected to each other, the first region 2041 corresponds to the display region 20a, and the second region 2042 corresponds to the non-display region 20 b; the second area 2042 includes a first sub-partition 2042a and a second sub-partition 2042b, which are connected to each other, the second sub-partition 2042b is disposed on one side of the second area 2042 close to the first area 2041, the first sub-partition 2042a is provided with a plurality of switching holes 20421, and the second sub-partition 2042b is provided with signal diffusion lines 20422.
The second sub-partition 2042b is provided with the signal diffusion line 20422, and the signal diffusion line 20422 has a relatively flat line, so that the photoresist diffusion is not affected. Therefore, the second sub-area 2042b is disposed on the side of the second area 2042 close to the first area 2041, and when the photoresist solution is coated, the photoresist solution reaches the second sub-area 2042b without backflow, and thus the photoresist solution is not accumulated at the boundary between the first area 2041 and the second area 2042.
Even if the photoresist solution reflows due to the existence of the via hole 20421 when applied to the first sub-sector 2042a, the photoresist solution is only deposited at the boundary between the first sub-sector 2042a and the second sub-sector 2042b and is not deposited at the boundary between the first sector 2041 and the second sector 2042.
Therefore, the second sub-partition 2042b is disposed on the side of the second area 2042 close to the first area 2041, so as to prevent the photoresist solution from accumulating at the boundary between the first area 2041 and the second area 2042, and solve the technical problems of uneven display brightness and various trace phenomena of the liquid crystal display panel caused by the accumulation of the photoresist solution at the boundary between the first area 2041 and the first area 2042.
In the array substrate that this application provided, through the slope of adjustment switching hole, make it gentle, or set up the guide plate, or adjust the position of first subregion and second subregion, make the second subregion be located the second and distinguish one side that is close to the first district, thereby make at the in-process of PI coating, the switching hole can not have the drawback of blockking the PI diffusion, and then has just also prevented to pile up and cause liquid crystal display panel to show luminance inhomogeneous because of PI at the display area, the phenomenon of various vestige appears takes place.
The present application further provides a display panel, wherein the display panel includes an array substrate, and the array substrate is the array substrate described in the above embodiments, and therefore details are not repeated here.
In the display panel that this application provided, through the slope of adjustment switching hole, make it gentle, or set up the guide plate, or adjust the position of first subregion and second subregion, make the second subregion be located the second and distinguish one side that is close to the first district, thereby make at the in-process of PI coating, the switching hole can not have the drawback of blockking the PI diffusion, and then has just also prevented to pile up and cause liquid crystal display panel to show luminance inhomogeneous because of PI at the display area, the phenomenon of various vestige appears takes place.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. An array substrate, comprising a display area and a non-display area connected to each other, wherein the non-display area is disposed at one end of the display area, and the array substrate comprises:
a substrate;
a buffer layer disposed on the substrate;
the source drain layer is arranged on the buffer layer;
the inorganic insulating layer is arranged on the source drain electrode layer and comprises a first area and a second area which are mutually connected, the first area corresponds to the display area, and the second area corresponds to the non-display area; wherein the content of the first and second substances,
the second area comprises a first sub-partition and a second sub-partition which are connected with each other, the first sub-partition is provided with a plurality of switching holes, and the second sub-partition is provided with signal diffusion lines; the first sub-partition is arranged on one side, close to the first zone, of the second zone, the gradient of the transfer hole is between 30 degrees and 60 degrees, and a drainage groove is formed in one end, close to the first zone, of the transfer hole, so that photoresist liquid flows into the transfer hole, or the second sub-partition is arranged on one side, close to the first zone, of the second zone;
and the packaging layer is arranged on the inorganic insulating layer.
2. The array substrate of claim 1, wherein the length of the end of the transfer aperture proximate to the first region is no greater than 30 microns.
3. The array substrate of claim 1, wherein a pitch of adjacent vias is not less than 30 microns.
4. The array substrate of claim 1, wherein the cross-sectional width of the transfer aperture is not less than 4 microns.
5. The array substrate of claim 1, wherein the slope of the drainage grooves is less than the slope of the transfer holes and is between 30 degrees and 60 degrees.
6. The array substrate of claim 1, further comprising a baffle plate disposed at an end of the via hole near the first region, wherein an edge of the baffle plate near the via hole coincides with an edge of the via hole near the baffle plate.
7. The array substrate of claim 6, wherein one end of the flow guide plate near the display area is a vertex or a straight line; wherein the content of the first and second substances,
when one end of the guide plate close to the display area is a vertex, the guide plate is in a circular arc shape, an elliptic arc shape or a triangular shape;
when one end of the guide plate close to the display area is a straight line, the guide plate is trapezoidal and rectangular.
8. The array substrate of claim 7, wherein the flow guiding plate is triangular, the flow guiding plate includes a first edge, a second edge and a third edge connected in sequence, the third edge is an edge of the flow guiding plate coinciding with the via hole, the first edge and the second edge are located on a side of the flow guiding plate close to the first region, and the first edge and the second edge intersect to form a first included angle, and the first included angle is not greater than 30 degrees.
9. The array substrate of claim 7, wherein the baffle is shaped as an elliptical arc, the baffle comprises a fourth edge and a fifth edge connected in sequence, the fifth edge is an edge of the baffle coinciding with the via hole, the fourth edge is an elliptical arc edge of the baffle close to the first area, and a ratio of a distance from a vertex of the fourth edge close to the first area to the fifth edge is not less than 1.5: 1.
10. A display panel comprising an array substrate according to any one of claims 1 to 9.
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|---|---|---|---|
| CN202011170942.6A CN112259561A (en) | 2020-10-28 | 2020-10-28 | Array substrate and display panel |
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| CN202011170942.6A CN112259561A (en) | 2020-10-28 | 2020-10-28 | Array substrate and display panel |
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| CN107422552A (en) * | 2017-08-16 | 2017-12-01 | 京东方科技集团股份有限公司 | Display base plate and display device |
| CN109212845A (en) * | 2018-10-25 | 2019-01-15 | 合肥鑫晟光电科技有限公司 | The preparation method of display base plate, display device and display base plate |
| CN209460546U (en) * | 2018-12-29 | 2019-10-01 | 成都中电熊猫显示科技有限公司 | A kind of array substrate, display panel and display device |
| CN110308815A (en) * | 2019-05-28 | 2019-10-08 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111596494A (en) * | 2020-05-21 | 2020-08-28 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
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| CN107422552A (en) * | 2017-08-16 | 2017-12-01 | 京东方科技集团股份有限公司 | Display base plate and display device |
| CN109212845A (en) * | 2018-10-25 | 2019-01-15 | 合肥鑫晟光电科技有限公司 | The preparation method of display base plate, display device and display base plate |
| CN209460546U (en) * | 2018-12-29 | 2019-10-01 | 成都中电熊猫显示科技有限公司 | A kind of array substrate, display panel and display device |
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