CN110596978A - Array substrate, manufacturing method thereof and display panel - Google Patents

Array substrate, manufacturing method thereof and display panel Download PDF

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Publication number
CN110596978A
CN110596978A CN201910843134.2A CN201910843134A CN110596978A CN 110596978 A CN110596978 A CN 110596978A CN 201910843134 A CN201910843134 A CN 201910843134A CN 110596978 A CN110596978 A CN 110596978A
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China
Prior art keywords
substrate
pixel electrode
array substrate
color
layer
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CN201910843134.2A
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Chinese (zh)
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刘军正
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201910843134.2A priority Critical patent/CN110596978A/en
Publication of CN110596978A publication Critical patent/CN110596978A/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention discloses an array substrate, a manufacturing method thereof and a display panel. According to the invention, the filling body is filled in the color resistance opening, and the top of the filling body is flush with the top of the pixel electrode, so that the surface of the alignment layer to be formed is flattened, the PI solution in the alignment layer manufacturing process is prevented from being accumulated in the area where the color resistance opening is located, and the thickness uniformity of the finally formed alignment layer is higher, thereby being beneficial to reducing the risk of the display panel that a diagonal phenomenon occurs during display; in addition, the array substrate is flattened, and the problems of bubbles, complex topography and large step difference of the COA product are favorably solved.

Description

Array substrate, manufacturing method thereof and display panel
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have advantages of high image quality, power saving, and wide application range, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices.
Most of the existing liquid crystal displays in the market are backlight liquid crystal displays (lcds), which include a liquid crystal panel and a backlight module (backlight module). The Liquid Crystal panel generally includes a Color Filter (CF) Substrate, a Thin Film Transistor Array (TFT Array Substrate), and a Liquid Crystal Layer (Liquid Crystal Layer) disposed between the two substrates, and the Liquid Crystal panel operates by applying a driving voltage to the two substrates and controlling an orientation of Liquid Crystal molecules in the Liquid Crystal Layer by an electric field generated between the two substrates, so as to refract light of the backlight module to generate a picture.
In a conventional liquid crystal panel, color resistors of various colors, a common electrode, and the like are prepared on one side of a color film substrate, and a TFT, a pixel electrode, and the like are prepared on one side of an array substrate. The traditional liquid crystal panel is limited by the alignment precision of the array substrate and the color film substrate, and the pixel aperture opening ratio is influenced.
In order to solve the problem of high requirement on alignment accuracy of the array substrate and the Color film substrate and improve the aperture opening ratio, the Color resistors can be integrally manufactured on one side of the array substrate, that is, a Color Filter on array (COA) technology is adopted to directly manufacture the Color Filter layer on the array substrate. The current COA array substrate generally includes a substrate, a color resistor disposed on the front surface of the substrate, a passivation layer disposed on the color resistor, a pixel electrode disposed on the passivation layer, and an alignment layer disposed on the pixel electrode, wherein the pixel electrode contacts the drain electrode of the TFT through a via hole penetrating through the passivation layer and the color resistor.
The height of the area where the via hole, also called a color-resist opening (CF open), is lower than the height of other areas, which causes Polyimide (PI) solution for preparing the alignment layer to be accumulated in the area where the color-resist opening is located, and the thickness of the formed alignment layer is not uniform, so that a display panel using the COA array substrate is prone to display a cross grain (mura) phenomenon.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a manufacturing method thereof, and a display panel, so as to solve the problem that a PI solution is easily accumulated in a region where a color-blocking hole is located in an alignment layer process of an existing COA array substrate, and a diagonal phenomenon occurs in the display panel.
The invention provides an array substrate, which comprises a substrate base material and a thin film transistor arranged on the substrate base material, and the array substrate also comprises:
the first passivation protective layer covers the thin film transistor;
the color resistors are arranged on the first passivation protective layer at intervals;
the second passivation protective layer covers the plurality of color resistors and the first passivation protective layer;
the pixel electrode is arranged on the second passivation protective layer and contacts the drain electrode of the thin film transistor through a through hole penetrating through the second passivation protective layer, the color resistor and the first passivation protective layer;
the filling body is filled in the through hole, and the top of the filling body is flush with the top of the pixel electrode;
and the alignment layer is covered on the pixel electrode and the filling body.
In one embodiment of the present invention, the top edge of the filling body completely contacts the top of the pixel electrode.
In one embodiment of the present invention, the main material of the filling body includes a photoresist.
In an embodiment of the invention, the color resistors include a red color resistor, a green color resistor and a blue color resistor.
In an embodiment of the invention, the color resistors include a red color resistor, a green color resistor, a blue color resistor and a white color resistor.
The invention provides a display panel, which comprises a first substrate and a second substrate which are oppositely arranged at intervals, and liquid crystal clamped between the two substrates, wherein the first substrate or the second substrate is any one of the array substrates.
In an embodiment of the invention, the display panel further includes a spacer for maintaining a uniform gap between the first substrate and the second substrate, and the spacer and the filling body are made of the same main material.
The invention provides a manufacturing method of an array substrate, which comprises the following steps:
providing a substrate base material;
forming a thin film transistor on the substrate base material;
forming a first passivation protective layer covering the thin film transistor;
forming a plurality of color resistors arranged at intervals on the first passivation protection layer;
forming a second passivation protective layer covering the plurality of color resists and the first passivation protective layer;
forming a pixel electrode on the second passivation protection layer, wherein the pixel electrode contacts the drain electrode of the thin film transistor through a via hole penetrating through the second passivation protection layer, the color resistor and the first passivation protection layer;
forming a filler in the via hole, wherein the top of the filler is flush with the top of the pixel electrode;
and forming an alignment layer covering the filling body and the pixel electrode.
In one embodiment of the present invention, the top edge of the filling body completely contacts the top of the pixel electrode.
In one embodiment of the present invention, the filling body is prepared by using a photoresist.
According to the array substrate, the manufacturing method thereof and the display panel, the filling body is formed in the through hole (namely the color resistance opening hole), and the top of the filling body is flush with the top of the pixel electrode, so that the surface of the alignment layer to be formed is flattened, the PI solution is prevented from being accumulated in the area where the color resistance opening hole is located in the alignment layer manufacturing process, the thickness uniformity of the finally formed alignment layer is high, and the risk of the display panel that a diagonal phenomenon occurs during display is favorably reduced; in addition, the array substrate is flattened, which is beneficial to improving the problems of bubbles (bubbles) of COA products (such as a display panel with the array substrate), complex topography, large step and the like.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the invention;
fig. 3 is a flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
The technical solutions of the exemplary embodiments provided in the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. The following embodiments and their technical features may be combined with each other without conflict.
Directional phrases used herein, such as, for example, upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, transverse, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., refer only to the orientation of the figure. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In addition, the same reference numerals are used to identify structural elements having the same or similar characteristics.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention. As shown in fig. 1, the array substrate 10 employs COA technology, which may be referred to as a COA array substrate, and includes a substrate 11 and structural members disposed on the substrate 11, wherein: a thin film transistor 12, a first Passivation (PV) layer 131, a plurality of color resistors 14 (only one is shown), a second Passivation layer 132, a pixel electrode 15, a filler 16, and an alignment layer 17. Wherein:
the thin film transistor 12 is provided on the substrate 11.
The first passivation layer 131 covers the thin film transistor 12.
The plurality of color resistors 14 are disposed on the first passivation layer 131, and any two adjacent color resistors 14 are disposed at an interval, and each color resistor 14 is disposed in a pixel opening area of the array substrate 10.
The second passivation layer 132 covers the color resistors 14, and the second passivation layer 132 covers the thin film transistor 12 and the first passivation layer 131.
The pixel electrode 15 is disposed on the second passivation layer 132, and the pixel electrode 15 contacts the drain of the thin film transistor 12 through a via hole 141 penetrating through the first passivation layer 131, the color resistor 14 and the second passivation layer 132, so that the pixel electrode 15 and the drain can be electrically connected. The via 141 is referred to as a color-blocking opening.
The via hole 141 is filled with the filler 16, and the top of the filler 16 is flush with the top of the pixel electrode 15, that is, the top surface of the filler 16 and the top surface of the pixel electrode 15 are located on the same horizontal plane.
The alignment layer 17 covers the pixel electrode 15 and the filling body 16, and of course, the alignment layer 17 serves as a whole structure and also covers the second passivation layer 132.
Based on the above, in the embodiment of the invention, the filling body 16 is formed in the color-resisting opening 141, and the top of the filling body 16 is flush with the top of the pixel electrode 15, which is equivalent to filling the color-resisting opening 141 with the filling body 16, so that the surface of the alignment layer 17 to be formed is flattened, thereby preventing the PI solution from being accumulated in the region where the color-resisting opening 141 is located in the process of forming the alignment layer 17, and the thickness uniformity of the finally formed alignment layer 17 is high, thereby being beneficial to reducing the risk of the display panel with the array substrate 10 that the diagonal phenomenon occurs during displaying; in addition, the embodiment of the invention planarizes the array substrate 10, which is beneficial to improving the problems of bubbles and complicated topography and large variation of COA products (such as a display panel with the array substrate 10).
It should be understood that the array substrate 10 of the embodiment of the invention may further include other structural elements, such as a Gate Insulation Layer (GI Layer), a Dielectric isolation Layer (IDL, also called Dielectric Layer), data lines, scan lines, etc., and the specific arrangement of these structural elements may refer to the prior art and will not be described herein.
In addition, the thin film transistor 12 may be a bottom gate TFT or a top gate TFT, and the embodiment of the present invention is not limited thereto. Wherein, the grid of the bottom grid type TFT is arranged below the channel layer, and the grid of the top grid type TFT is arranged above the channel layer. Specifically, the above-described array substrate 10 will be described continuously below with reference to the bottom gate type TFT shown in fig. 1.
The substrate 11 may be a glass substrate, a plastic substrate, or a flexible substrate.
The thin film transistor 12 includes a gate 121, a channel layer 122, a source 123 and a drain 124, and a gate insulating layer 125, wherein the gate 121 is disposed on the substrate 11, the gate insulating layer 125 covers the gate 121, the channel layer 122 is disposed on the gate insulating layer 125 and located above the gate 121, the source 123 and the drain 124 are disposed on the gate insulating layer 125 in the same layer, and the source 123 and the drain 124 are respectively in contact with two ends of the gate insulating layer 125.
It should be understood that, according to the specific type of the thin film transistor 12, the embodiment of the present invention may select a corresponding type of the channel layer 122, specifically, for the thin film transistor 12 adopting a Low Temperature Poly-silicon (LTPS) technology, a main material of the channel layer 122 may be polysilicon (Poly), at this time, two ends of the channel layer 122 may be respectively provided with doped regions, one side of each doped region near the middle of the channel layer 122 may be an N-type lightly doped region, and one side of each doped region far from the middle of the channel layer 122 may be an N-type heavily doped region; for a thin film transistor 12 using amorphous Oxide semiconductor technology, the main material of the channel layer 122 may be Indium Gallium Zinc Oxide (IGZO).
The first passivation layer 131 covers the thin film transistor 12, and specifically, the first passivation layer 131 serves as a whole surface structure covering the channel layer 122, the source electrode 123 and the drain electrode 124, and also covering the gate insulating layer 125. The main material of the first passivation protection layer 131 includes, but is not limited to, a silicon nitride compound, such as Si3N4(silicon nitride).
A plurality of color resistors 14 are disposed on the first passivation protection layer 131, and each color resistor 14 is disposed in a corresponding pixel opening region of the array substrate 10. For an array substrate 10 employing an RGB subpixel design, the plurality of color resists 14 includes a red color resist, a green color resist, and a blue color resist. For an array substrate 10 using an RGBW subpixel design, the plurality of color resistors 14 may include a red color resistor, a green color resistor, a blue color resistor, and a white color resistor.
The main materials of the second passivation protection layer 132 and the first passivation protection layer 131 may be the same.
The color resistor opening 141 sequentially penetrates through the first passivation layer 131, the color resistor 14 and the second passivation layer 132 from top to bottom, and exposes the drain of the thin film transistor 12. Here, a portion of the pixel electrode 15 is disposed in the color-resist opening 141 and contacts the drain of the thin film transistor 12, so that the pixel electrode 15 and the drain can be electrically connected, and the pixel electrode 15 is used for defining a pixel opening region of the array substrate 10 and may be made of ITO (indium tin oxide).
The top edge of the filling body 16 completely contacts the top of the pixel electrode 15, that is, the forward projection area of the filling body 16 is equal to the forward projection area of the color-resist opening 141, and the two areas are located on the array substrate 10, so that the top edge of the filling body 16 completely contacts the top surface of the pixel electrode 15, that is, the top edge of the filling body 16 and the edge of the pixel electrode 15 at the color-resist opening 141 are in seamless contact. In addition, the main material of the filling body 16 may be photoresist, or other physically and chemically stable material.
In the embodiment of the present invention, the filling body 16 is equivalent to a filling member filled in the recessed region, and has a certain similarity with the structural form and the preparation principle of a Spacer (Photo Spacer, PS) for maintaining the thickness of the liquid crystal cell and the thickness uniformity in the liquid crystal display panel, so that the main materials and the preparation principles of the filling body 16 and the Spacer can be the same.
Because the color resistance openings 141 are filled with the filler 16, and the top of the filler 16 is flush with the top of the pixel electrode 15, the top surface of the filler 16 and the top surface of the pixel electrode 15 are positioned on the same horizontal plane, so that the surface of the alignment layer 17 to be formed is ensured to be flat, the PI solution can be uniformly diffused on the flat surface in the alignment layer manufacturing process, the PI solution cannot be accumulated in the area where the color resistance openings 141 are positioned, the thickness uniformity of the finally formed alignment layer 17 is high, and the risk of a diagonal phenomenon of the display panel during display is favorably reduced; in addition, the array substrate 10 is planarized, which is beneficial to improving the problems of bubbles, complicated topography, large offset and the like of COA products.
The alignment layer 17 may be a thin film with straight scratches for guiding the alignment direction of the liquid crystal molecules, and may be fabricated by a uv (ultraviolet) photo-alignment method, an electron plasma alignment method, or an ion beam alignment method. The component of the alignment layer 17 can be polyimide which is an aromatic heterocyclic high molecular compound with a molecular structure containing imide chain links, the solid component of the PI alignment layer 17 is a small molecular compound in the stock solution, the PI alignment layer generates polymerization reaction at high temperature to form long-chain macromolecular solid polymer polyamide with a plurality of branched chains, the included angle between the branched chain and the main chain in the polymer molecule forms a pretilt angle of the guide layer, and the liquid crystal molecules can be arranged in the pretilt angle direction due to the strong acting force between the branched chain group of the polymer and the liquid crystal molecules and the anchoring effect on the liquid crystal molecules.
As shown in fig. 2, the display panel 20 includes a first Substrate 21 and a second Substrate 22 that are disposed at an interval, and a liquid crystal molecule 23 sandwiched between the first Substrate 21 and the second Substrate 22, where one of the first Substrate 21 and the second Substrate 22 is a Color Filter Substrate (CF Substrate), the other of the first Substrate 21 and the second Substrate 22 is an array Substrate, and the liquid crystal molecule 23 is located in a liquid crystal box formed by overlapping the Color Filter Substrate and the array Substrate.
However, the display panel 20 may use the COA technology, that is, the array substrate of the liquid crystal display panel 20 may have the same structure as the array substrate 10, and thus, the liquid crystal display panel 20 may have the same advantageous effects as the array substrate 10.
The embodiment of the invention further provides a manufacturing method of an array substrate, which can be used for manufacturing the array substrate 10 of the foregoing embodiment. Fig. 3 is a flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the invention. As shown in FIG. 3, the method may include steps S31-S38.
S31: a substrate is provided.
The substrate base material may be a transparent base material such as a glass base material, a plastic base material, or a flexible base material. Of course, the substrate base material may also be provided with a passivation Layer, that is, the substrate base material includes a base material and a Buffer Layer (Buffer Layer) formed on the base material, in this case, the base material may be a glass base material, a transparent plastic base material or a flexible base material, and the Buffer Layer may be a silicon nitride compound for ensuring the wear resistance and cleanliness of the upper surface of the substrate base material. It should be understood that when the substrate base is provided with the buffer layer, the thin film transistor of the array substrate 10 is directly formed on the buffer layer.
S32: a thin film transistor is formed on the substrate.
Taking a bottom gate type thin film transistor as an example, the formation principle or process of the thin film transistor is as follows:
first, the embodiment of the invention may form a full-surface metal layer on a substrate by using a Physical Vapor Deposition (PVD) method, and then perform a patterning process on the full-surface metal layer, so as to only retain the metal layer in a predetermined region, where the metal layer in the predetermined region forms a gate. The patterning process may include processes such as photoresist coating, exposure, development, and etching, which are described in detail herein with reference to the prior art.
Then, the present embodiment may form a gate insulating layer covering an entire surface of the gate electrode by using a Chemical Vapor Deposition (CVD) method. The gate insulating layer may be made of silicon oxide (SiO)x) Or the gate insulating layer comprises a silicon oxide layer and a silicon nitride layer, such as SiO, sequentially covering the gate2(silicon dioxide) layer and Si3N4And the (silicon nitride) layer further improves the wear resistance and the insulating property of the gate insulating layer.
Next, the embodiment of the invention may form the channel layer by using a mask process.
Finally, the source and drain electrodes of the thin film transistor may be formed by the same patterning process as that for forming the gate electrode.
S33: and forming a first passivation protection layer covering the thin film transistor.
The first passivation layer is a whole surface structure covering the thin film transistor, and the first passivation layer can be formed in sequence by adopting a CVD method in the embodiment of the invention.
S34: and forming a plurality of color resistors arranged at intervals on the first passivation protection layer.
Depending on the material properties of the color resists, embodiments of the present invention may be adapted to a method, for example, a CVD method or a sputtering method may be used.
S35: and forming a second passivation protective layer covering the plurality of color resists and the first passivation protective layer.
In the embodiment of the invention, the second passivation layer can be formed by the same process as the first passivation layer, and the main materials of the second passivation layer and the first passivation layer can be the same.
S36: and forming a pixel electrode on the second passivation protection layer, wherein the pixel electrode contacts the drain electrode of the thin film transistor through a via hole penetrating through the second passivation protection layer, the color resistor and the first passivation protection layer.
In the embodiment of the invention, the second passivation protective layer, the color resistor and the first passivation protective layer at the preset positions can be perforated by adopting an etching process, so that the through holes (namely color resistor openings) which sequentially penetrate through the second passivation protective layer, the color resistor and the first passivation protective layer from top to bottom are formed, and the drain electrode of the thin film transistor is exposed through the through holes.
Further, a PVD method and a patterning process may be used to form a pixel electrode in the pixel opening region of the array substrate 10. The main material of the pixel electrode may be a light-transmitting conductive material such as ITO, and a portion of the light-transmitting conductive material is filled in the via hole and contacts with the drain electrode of the thin film transistor.
S37: and forming a filling body in the via hole, wherein the top of the filling body is flush with the top of the pixel electrode.
The main material of the filling body can be photoresist or other materials with stable physical and chemical properties. In the embodiment, the filling body is equivalent to the filling member filled in the recessed region, and has a certain similarity with the structure form and the preparation principle of the PS in the liquid crystal display panel, so that the main materials and the preparation principle of the filling body and the PS can be the same.
Preferably, the top edge of the filling body completely contacts the top of the pixel electrode, that is, the area of the front projection of the filling body is equal to the area of the front projection of the color-resisting opening, and the two areas are located on the array substrate 10, so that the top edge of the filling body completely contacts the top surface of the pixel electrode, in other words, the top edge of the filling body and the edge of the pixel electrode at the color-resisting opening seamlessly contact.
S38: and forming an alignment layer covering the filling body and the pixel electrode.
The component of the alignment layer can be polyimide, so that the alignment layer can also be called as a PI alignment layer, and the PI solution can be freely diffused in the plane where the filler and the pixel electrode are located by adopting a coating process, and finally the required alignment layer is formed by processes such as curing and the like.
In the manufacturing method of the embodiment of the invention, because the top of the filling body prepared in the step S37 is flush with the top of the pixel electrode, the top surface of the filling body and the top surface of the pixel electrode are positioned on the same horizontal plane, thereby ensuring the surface planarization of the alignment layer to be formed, the PI solution can be uniformly diffused on the planarized surface in the alignment layer process, and cannot be accumulated in the region where the color resistance opening is located, the thickness uniformity of the finally formed alignment layer is higher, thereby being beneficial to reducing the risk of the display panel that a diagonal phenomenon occurs during display; in addition, the embodiment of the invention planarizes the array substrate 10, which is beneficial to improving the problems of bubbles and complicated topography and large variation of COA products (such as a display panel with the array substrate 10).
Although the invention has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present invention includes all such modifications and variations, and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by using the contents of the present specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present invention.
In addition, while a particular feature of the specification may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising. Further, it is understood that reference to "a plurality" herein means two or more.

Claims (10)

1. An array substrate comprises a substrate and a thin film transistor arranged on the substrate, and is characterized in that the array substrate further comprises:
the first passivation protective layer covers the thin film transistor;
the color resistors are arranged on the first passivation protective layer at intervals;
the second passivation protective layer covers the plurality of color resistors and the first passivation protective layer;
the pixel electrode is arranged on the second passivation protective layer and contacts the drain electrode of the thin film transistor through a through hole penetrating through the second passivation protective layer, the color resistor and the first passivation protective layer;
the filling body is filled in the through hole, and the top of the filling body is flush with the top of the pixel electrode;
and the alignment layer is covered on the pixel electrode and the filling body.
2. The array substrate of claim 1, wherein the top edge of the filling body completely meets the top of the pixel electrode.
3. The array substrate of claim 1 or 2, wherein the main material of the filling body comprises photoresist.
4. The array substrate of claim 1, wherein the plurality of color resistors comprise a red color resistor, a green color resistor, and a blue color resistor.
5. The array substrate of claim 1, wherein the plurality of color resistors comprise a red color resistor, a green color resistor, a blue color resistor, and a white color resistor.
6. A display panel, comprising a first substrate and a second substrate disposed at an interval, and a liquid crystal sandwiched between the two substrates, wherein the first substrate or the second substrate is the array substrate according to any one of claims 1 to 5.
7. The display panel according to claim 6, wherein the display panel further comprises spacers for maintaining a uniform gap between the first substrate and the second substrate, and the spacers and the filler are mainly made of the same material.
8. A method for manufacturing an array substrate, the method comprising:
providing a substrate base material;
forming a thin film transistor on the substrate base material;
forming a first passivation protective layer covering the thin film transistor;
forming a plurality of color resistors arranged at intervals on the first passivation protection layer;
forming a second passivation protective layer covering the plurality of color resists and the first passivation protective layer;
forming a pixel electrode on the second passivation protection layer, wherein the pixel electrode contacts the drain electrode of the thin film transistor through a via hole penetrating through the second passivation protection layer, the color resistor and the first passivation protection layer;
forming a filler in the via hole, wherein the filler is flush with the top of the pixel electrode;
and forming an alignment layer covering the filling body and the pixel electrode.
9. The method of claim 8, wherein a top edge of the filling body completely contacts a top of the pixel electrode.
10. The method of claim 8 or 9, wherein the filling body is prepared by using a photoresist.
CN201910843134.2A 2019-09-06 2019-09-06 Array substrate, manufacturing method thereof and display panel Pending CN110596978A (en)

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CN110941123A (en) * 2019-11-07 2020-03-31 深圳市华星光电半导体显示技术有限公司 COA type array substrate and manufacturing method thereof
CN111596494A (en) * 2020-05-21 2020-08-28 Tcl华星光电技术有限公司 Array substrate and preparation method thereof
CN111610659A (en) * 2020-05-19 2020-09-01 深圳市华星光电半导体显示技术有限公司 Array substrate and preparation method thereof
CN115220266A (en) * 2022-07-07 2022-10-21 广州华星光电半导体显示技术有限公司 Array substrate and manufacturing method thereof

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CN110941123A (en) * 2019-11-07 2020-03-31 深圳市华星光电半导体显示技术有限公司 COA type array substrate and manufacturing method thereof
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Application publication date: 20191220