CN111584490A

CN111584490A - Separated three-dimensional longitudinal memory

Info

Publication number: CN111584490A
Application number: CN202010369182.5A
Authority: CN
Inventors: 张国飙
Original assignee: Hangzhou Haicun Information Technology Co Ltd
Current assignee: Hangzhou Haicun Information Technology Co Ltd
Priority date: 2015-02-26
Filing date: 2015-02-26
Publication date: 2020-08-25
Also published as: CN105990351A

Abstract

Separate three-dimensional vertical memory (3D-M)_V) 50 contain a three-dimensional array chip 30 and a peripheral circuit chip 40/60. The three-dimensional array chip 30 includes a plurality of 3D-M chips_VArray of 3D-M each_VThe array contains a plurality of vertical memory strings. 3D-M_VA peripheral circuit of the array is located within the peripheral circuit die 40/60 rather than within the three-dimensional array die 30. The vertical memory string 16X contains a greater number of memory cells 8a-8h in the direction perpendicular to chip 30 than the number of layers of interconnects contained in chip 40/60 in the direction perpendicular to chip 40/60.

Description

Separated three-dimensional longitudinal memory

The present application is a divisional application of an invention patent application having an application number of 201510088410.0, an application date of 2015, 26.2, entitled "separated three-dimensional vertical memory".

Technical Field

The present invention relates to the field of integrated circuit memories, and more particularly to three-dimensional vertical memories.

Background

Three-dimensional vertical memory (3D-M for short)_V) Is a monolithic semiconductor memory that contains multiple vertical memory strings. 3D-M_VIncluding a three-dimensional read-only memory (3D-ROM) and a three-dimensional random access memory (3D-RAM). The 3D-ROM can be further divided into a three-dimensional mask-programmed read-only memory (3D-MPROM) and a three-dimensional electrically-programmed read-only memory (3D-EPROM). Based on its programming mechanism, 3D-M_VMay contain a memory, a resistive random-access memory (RRAM or ReRAM), a phase-change memory (PCM), a programmable registration memory (PMM), or a capacitive-resonant random-access memory (CB)RAM), and the like.

U.S. Pat. No. 8,638,611 discloses a 3D-M_VIt is a vertical nand. As shown in FIG. 1, the 3D-M_VThe chip 20V contains at least one 3D-M_VAn array 16V and peripheral circuitry 18. 3D-M_VThe array 16V contains a plurality of

vertical storage strings

16X, 16Y. Each memory string (e.g., 16X) contains a plurality of vertically stacked memory elements (e.g., 8a-8 h). The memory elements are coupled to each other via a vertical address line. Each memory cell (e.g., 8 f) contains a vertical transistor having a gate 6, a memory film 7, and a vertical channel 9. The peripheral circuit 18 contains a transistor 0t and its interconnect line 0 i. The transistor 0t is formed in the semiconductor substrate 0, which is a conventional planar transistor. The interconnection line 0i realizes interconnection for the transistor 0 t. In fig. 1, the substrate interconnect line 0i contains metal layers 0M1, 0M 2.

The peripheral circuit 18 is a 3D-M_VThe array 16V generates read/write voltages and/or translates address/data. Specifically, it converts the externally supplied power voltage into a read voltage and/or a write voltage, and also converts the external logical address/data into 3D-M_VPhysical address/data of array 16V. 3D-M of the prior art_VIs an integrated 3D-M_VI.e. 3D-M_VThe array 16V and its peripheral circuits 18 are integrated within the same chip 20V. That is, 3D-M_VThe chip 20V internally generates read/write voltages and/or converts address/data. Due to 3D-M_VThe

vertical memory strings

16X, 16Y occupy the substrate 0 therebelow, and the peripheral circuits 18 can only be located in 3D-M_VOutside the array 16V.

The main views of the prior art are: and the cost is reduced by integration. Unfortunately, this view is on 3D-M_VIt is not true. For 3D-M_VIn other words, since the

vertical memory strings

16X, 16Y employ a cumbersome back-end-of-line (BEOL) process, and the back-end process of the peripheral circuits 18 is relatively simple, the direct result of blindly integrating the

memory strings

16X, 16Y and the peripheral circuits 18 is that the peripheral circuits 18 have to be manufactured using an expensive process flow for manufacturing the

memory strings

16X, 16Y, which not only does not reduce the cost, but also increases the cost.

Disclosure of Invention

It is a primary object of the present invention to provide a less expensive three-dimensional vertical memory (3D-M)_V）。

It is another object of the invention to improve 3D-M_VThe array efficiency of (1).

To achieve these and other objects, the present invention follows the following design principles: the three-dimensional circuit and the two-dimensional circuit are separated into different chips so as to be optimized respectively. In order to improve the array efficiency of the three-dimensional array chip, the peripheral circuits thereon should be minimized. For example, 3D-M may be used_VThe voltage generator of (2) is separated into another chip. Accordingly, the invention provides a separation 3D-M_VIt contains at least one three-dimensional array chip and at least one voltage generator chip. The three-dimensional array chip (three-dimensional circuit) is constructed in a three-dimensional space and comprises a plurality of functional layers, and the voltage generator chip (two-dimensional circuit) is constructed in a two-dimensional space and only comprises one functional layer. Since the voltage generator component realizes 3D-M_VThe functional necessary components, the three-dimensional array chip without the voltage generator components, are not themselves a memory chip capable of independent operation. Separation of 3D-M_VOne advantage is brought about: the three-dimensional array chip has higher array efficiency.

In the separation of 3D-M_VIn (b), since the three-dimensional array chip and the voltage generator chip can be designed and manufactured separately, they may have different back-end (BEOL) structures: the voltage generator chip may contain fewer back-end membranes. Although three-dimensional array chip and integrated 3D-M_VThe die cost is similar, but because the voltage generator die can be manufactured using a separate, inexpensive back-end process, the die cost is lower. Thus, for the same storage capacity, the 3D-M is split_VTotal cost of less than integrated 3D-M_V。

The invention provides a separation 3D-M_V(50) The method is characterized by comprising the following steps: a compound containing at least one 3D-M_VA three-dimensional array chip (30) of an array (16V), the 3D-M_VThe array (16V) contains a plurality of vertical memory strings (16X, 16Y), each vertical memory string containing a plurality of vertically stacked memory cells(8a-8 h); a voltage generator chip (40) including at least part of a voltage generator for providing at least one voltage and a power supply voltage (V) to the three-dimensional array chip (30)_DD) Different read voltages (V)_R) And/or write voltage (V)_W) (ii) a The three-dimensional array chip (30) does not contain the partial voltage generator, the three-dimensional array chip (30) contains more back-end films than the voltage generator chip (40), and the three-dimensional array chip (30) and the voltage generator chip (40) are two different chips.

Drawings

FIG. 1 is an integrated 3D-M_VCross-sectional view of a chip (prior art).

FIG. 2A is a schematic representation of a separation 3D-M_VFIG. 2B is a schematic view of the separation 3D-M_VA circuit block diagram of (1).

FIG. 3 is another separation 3D-M_VSchematic representation of (a).

FIG. 4 is a schematic diagram of a separation 3D-M_VCross-sectional view of a medium three-dimensional array chip.

FIG. 5 is the separation 3D-M_VCross-sectional view of a medium voltage generator chip.

Fig. 6A-6C are circuit diagrams of three voltage generators.

FIGS. 7A-7C are three separations 3D-M_VCross-sectional view of (a).

It is noted that the figures are diagrammatic and not drawn to scale. Dimensions and structures of parts in the figures may be exaggerated or reduced for clarity and convenience. The same reference numbers in different embodiments generally indicate corresponding or similar structures.

Detailed Description

In the present invention, "/" indicates a relationship of "and" or ". For example, the read/write voltage means a read voltage, or a write voltage, or a read voltage and a write voltage; address/data represents an address, or data, or an address and a voltage.

FIGS. 2A-2B show a separation 3D-M _V50. It contains a three-dimensional array chip 30 (three-dimensional circuit) and a voltage generator chip 40 (two-dimensional circuit). Wherein, the three-dimensional array chip30 are built in three dimensions and contain a plurality of functional layers (i.e. memory layers), and the voltage generator chip 40 is built in two dimensions and contains only one functional layer. Separating the three-dimensional and two-dimensional circuits into different chips allows them to be optimized separately.

Separation 3D-M in FIG. 2A _V50 is a 3D-M_VThe memory card includes an interface 54 that enables physical connection to various hosts and communication according to a communication standard. The interface 54 includes a plurality of

contact terminals

52a, 52b, 54a-54d that are capable of coupling with corresponding contact terminals of a host jack. Wherein the supply terminal 52a is coupled to a supply contact terminal of the host, the supply voltage V being supplied by the host via the supply terminal 52a_DD(ii) a Ground terminal 52b is split 3D-M _V50 supply ground voltage V_SS(ii) a Signal terminals 54a-54D are host and split 3D-M _V50 provide for the exchange of signals including address/data. Since these addresses/data are used directly by the host, they are logical addresses/data.

The voltage generator chip 40 obtains the power supply voltage V from the power supply terminal 52_DDConverted into a read/write voltage and supplied to the three-dimensional array chip 30 through the power bus 56. The read/write voltage may be a read voltage V only_ROr only the write voltage V_WOr both the read voltage V_RAnd a write voltage V_W(ii) a In addition, V_RAnd V_WAnd V_DDWith different values. In this embodiment, the read/write voltage includes a read voltage V_RAnd two write voltages V_W1、V_W2. In other embodiments, the read/write voltages may include more than one read voltage or two write voltages.

FIG. 2B is a schematic representation of the separation of 3D-M _V50. The three-dimensional array chip 30 includes a plurality of 3D-M chips_VThe arrays 22aa, 22ay … and their

decoders

24, 24G. The voltage generation chip 40 is located between the integral decoder 24G of the three-dimensional array chip 30 and the interface 54. It contains at least one 3D-M_VThe voltage generator assembly of (1). With integrated 3D-M_VInstead, the components are located in the voltage generating chip 40, not the three-dimensional array chip 30. Since the component is an implementation3D-M_VThe functional necessary components, the three-dimensional array chip 30 without the voltage generator components, are not themselves a memory chip capable of independent operation.

3D-M_VMay contain a plurality of voltage generator components such as a bandgap reference circuit (precision reference voltage source) 40B, a read voltage generator 40R, and a charge pump 40W. Wherein the read voltage generator 40R generates a read voltage V_RThe charge pump 40W generates a write voltage V_W(see U.S. Pat. No. 6,486,728). Fig. 6A-6C disclose further examples of voltage generators.

Separation 3D-M in FIG. 3_V50 may be used as a mass storage card or solid state drive that contains a plurality of three-

dimensional array chips

30a, 30b … 30 w. The voltage generator chip 40 supplies read/write voltages to these three-dimensional array chips through the power bus 56. The converter chip 60 converts logical addresses/data from the contact terminals 54a-54d into physical addresses/data. The three-dimensional array chip constitutes two channels: a and B. In lane a, the internal bus 58A provides physical addresses/data for the three-

dimensional array chips

30a, 30b … 30 i; in lane B, the internal bus 58B provides physical addresses/data for the three-

dimensional array chips

30r, 30s … 30 w. Although the embodiment has only two channels, it is obvious to those skilled in the art that the mass storage card and the solid state disk may have more channels.

FIG. 4 is a schematic representation of the separation of 3D-M _V50, cross-sectional view of three-dimensional array chip 30. The three-dimensional array chip 30 is formed in a three-dimensional space and contains a plurality of

memory strings

16X, 16Y. Each memory string (e.g., 16X) contains a plurality of vertically stacked memory elements (e.g., 8a-8 h). The memory elements are coupled to each other via a vertical address line. Each memory cell (e.g., 8 f) contains a vertical transistor having a gate 6, a memory film 7, and a vertical channel 9. A 3D-M_VAn example of (c) is vertical nand (vertical nand). Since one vertical NAND memory string contains 24 to 256 vertically stacked memory cells, the three-dimensional array chip 30 contains a large number (24 to 256 layers) of back-end films.

FIG. 5 is a schematic representation of the separation of 3D-M_VCross-sectional view of voltage generator chip 40 in 50. Voltage generator chip40 are formed in two dimensions and contain only one functional layer, i.e. the substrate layer 0K'. The substrate layer 0K' includes the transistor 0t and its interconnect line 0 iB. Transistor 0t is formed on voltage generator substrate 0B, and interconnect line 0iB includes two metal layers 0M1 '-0M 2'. Since each metal layer (e.g., 0M 1') contains 2 back end films, the voltage generating chip 40 contains only 4 back end films in total.

In the separation of 3D-M _V50, since the three-dimensional array chip 30 and the voltage generator chip 40 can be designed and manufactured separately, they can have different backend structures: the voltage generator chip 40 may contain fewer back-end membranes. Although the three-dimensional array chip 30 and the integrated 3D-M_VThe die 20V has a similar wafer cost, but because the voltage generator die 40 can be fabricated using a separate, inexpensive back-end process, the wafer cost is lower. Thus, for the same storage capacity, the 3D-M is split_V50 total cost lower than integrated 3D-M _V20V。

For a conventional two-dimensional memory (2D-M, the memory elements are distributed in a two-dimensional plane, such as a flash memory), although it is also possible to separate the 3D-M_VThe 2D-M array and the voltage generator are also separated on different chips, which increases the overall cost. This is because the two-dimensional array chip and the voltage generating chip have similar back-end structures and similar wafer costs, and the separate 2D-M is more expensive than the integrated 2D-M, plus additional packaging costs. This is in contrast to 3D-M_VAre very different. 3D-M_VThe middle three-dimensional array chip 30 and the voltage generation chip 40 have different backend structures, thereby separating 3D-M_V3D-M integration_VIt is cheap.

Fig. 6A-6C are circuit diagrams of three voltage generators. The voltage generator preferably uses a direct current-direct current converter (DC-DC converter). The DC-DC converter includes a booster and a step-down transformer. The output voltage of the booster is higher than the input voltage, and the input voltage of the step-down transformer is lower than the input voltage. Examples of the booster include a charge pump (fig. 6A), a Boost converter (fig. 6B), and the like. Examples of the step-down device include a low dropout regulator (fig. 6C), a Buck converter (Buck converter), and the like.

The voltage generator of FIG. 6A includes a charge pump 72 that outputs a voltage V_outGreater than the input voltage V_in. Generally, the charge pump 72 also contains one or more capacitors. The voltage generator of fig. 6B includes a high frequency Boost converter 74, which outputs a voltage V_outGreater than the input voltage V_in. Boost converter 74 also contains an inductor. The inductor is preferably a thin inductor to meet the thickness requirements of the memory card or solid state drive. The voltage generator of FIG. 6C includes a low dropout regulator 76 having an output voltage V_outLess than the input voltage V_in. Generally, the LDO 76 also contains one or more capacitors.

FIGS. 7A-7C are three separations 3D-M_VCross-sectional view of (a). Separation 3D-M in FIGS. 7A-7B_VIs a multi-chip package (MCP). Among them, 3D-M in FIG. 7A_VThe multi-chip package 60 contains two separate chips: a three-dimensional array chip 30 and a voltage generator chip 40. The

chips

30, 40 are stacked on a package substrate (interposer) 63 and in the same package 61. Lead wires 65 provide electrical connections for the

chips

30, 40. In addition to the lead, a solder ball (solderump) or the like may be used. To ensure data security, the

chips

30, 40 are preferably encapsulated in a molding compound 67. In the present embodiment, the three-dimensional array chip 30 is stacked on the voltage generator chip 40. In other embodiments, the voltage generator chip 40 may be stacked on the three-dimensional array chip 30, or the three-dimensional array chip 30 and the voltage generator chip 40 are stacked face to face, or the three-dimensional array chip 30 and the voltage generator chip 40 are placed side by side.

3D-M in FIG. 7B_VThe multi-chip package 60 contains at least two three-

dimensional array chips

30a, 30b and a voltage generator chip 40. These

chips

30a, 30b and 40 are three separate chips. They are located in the same package 61. Wherein the three-dimensional array chip 30a is stacked on the three-dimensional array chip 30b, and the three-dimensional array chip 30b is stacked on the voltage generator chip 40. Leads 65 provide electrical connections for

chips

30a, 30b, and 40.

Separation 3D-M in FIG. 7C_VIs a 3D-M_VA multi-chip module (MCM) 60 includes a frame 76. The frame 76 contains two separate packages: a three-dimensional array package 72 and a voltage generator package 74. Therein, the three-dimensional array package 72 contains two three-

dimensional array chips

30a, 30b, and the voltage generator package 74 contains the voltage generator chip 40. The frame 76 also provides electrical connections (not shown here) for the three-dimensional array package 72 and the voltage generator package 74.

It will be understood that changes in form and detail may be made therein without departing from the spirit and scope of the invention, and are not intended to impede the practice of the invention. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

1. Separated three-dimensional longitudinal memory (3D-M)_V) (50), characterized by comprising:

a three-dimensional array chip (30), the three-dimensional array chip (30) formed on a first substrate (0A) and containing a plurality of vertical memory strings (16X, 16Y), each vertical memory string containing a plurality of vertically stacked memory cells (8a-8 h);

a peripheral circuit chip (40 or 60), the peripheral circuit chip (40 or 60) being formed on the second substrate (0B) and containing at least one peripheral circuit of the three-dimensional array chip (30); the three-dimensional array chip (30) is free of the peripheral circuit;

the vertical memory string (16X) contains a greater number of memory cells (8a-8h) in a direction perpendicular to the first substrate (0A) than a number of interconnect layers contained in the peripheral circuit chip (40 or 60) in a direction perpendicular to the second substrate (0B);

the three-dimensional array chip (30) and the peripheral circuit chip (40 or 60) are at least two different chips.

2. The memory of claim 1, further characterized by: the peripheral circuit chip (40 or 60) is a voltage generator chip (40).

3. The memory of claim 1, further characterized by: the peripheral circuit chip (40 or 60) is a converter chip (60).

4. The memory of claim 1, further characterized by: the three-dimensional vertical memory is a vertical NAND.

5. The memory of claim 1, further characterized by: the three-dimensional vertical memory is a three-dimensional read-only memory (3D-ROM).

6. The memory of claim 1, further characterized by: the three-dimensional vertical memory is a three-dimensional random access memory (3D-RAM).

7. The memory of claim 1, further characterized by: the three-dimensional longitudinal memory is at least one of a memory card, a solid state disk, a multi-chip package and a multi-chip assembly.