WO2014134865A1

WO2014134865A1 - Three-dimensional memory comprising independent intermediate circuit chip

Info

Publication number: WO2014134865A1
Application number: PCT/CN2013/075222
Authority: WO
Inventors: 张国飙
Original assignee: Zhang Guobiao
Priority date: 2013-03-06
Filing date: 2013-05-06
Publication date: 2014-09-12

Abstract

Proposed is a separate three-dimensional memory (separate 3D-M) comprising an intermediate circuit chip. The separate three-dimensional memory comprises at least one three-dimensional array chip and at least one intermediate circuit chip. The three-dimensional array chip comprises a plurality of three-dimensional storage arrays, wherein each three-dimensional storage array comprises a plurality of storage layers mutually stacked, and the storage layers do not comprise elements similar to transistors. The intermediate circuit chip comprises at least one of a read-write voltage generator and an address/data converter, and achieves conversions of the voltage, address or/and data between a core area of the 3D-M and a host. A separate 3D-M supports a plurality of three-dimensional array chips.

Description

Three-dimensional memory with independent intermediate circuit chip

Technical field

This invention relates to the field of integrated circuit memory and, more particularly, to a three dimensional memory (3D-M).

Background technique

The three-dimensional memory (3D-M) is a monolithic semiconductor memory whose memory elements are distributed in three-dimensional space. The 3D-M includes a three-dimensional read only memory (3D-ROM) and a three-dimensional random read memory (3D-RAM). 3D-ROM can be further divided into 3D mask programming read-only memory ( 3D-MPROM) and 3D electrical programming read only memory (3D-EPROM). Based on its programming mechanism, 3D-M can contain printed memory elements (see PCT application) PCT/CN2012/080895), memristor memory elements, resistive memory elements (RRAM or ReRAM), phase-change memory (PCM), programmable metallization memory (PMM), or conductive-bridging Random-access memory (CBRAM), etc.

U.S. Patent 5,835,396 discloses a 3D-M, 3D-ROM. As shown in Figure 1A, 3D-M The chip 20 includes a substrate layer 0K and a plurality of

memory layers

16A, 16B stacked on the substrate layer 0K and stacked on each other. Substrate layer 0K contains transistor 0t and its interconnect 0i . Wherein transistor 0t is formed in semiconductor substrate 0; interconnect 0i contains substrate metal layers 0M1, 0M2 which are above substrate 0 but at the lowest memory level 16A Below. A memory layer (e.g., 16A) is coupled to the substrate layer 0K through contact via holes (e.g., 1av).

Each storage layer (such as 16A) contains multiple top address lines (such as 2a), bottom address lines (such as 1a), and storage elements (such as 5aa). The memory cells can be diodes, transistors or other devices. Among the various memory elements, a memory cell using a diode is especially important: its area is the smallest, only 4F ² (F is the minimum feature size). Diode memory cells are typically formed at the intersection of the top address line and the bottom address line to form a cross-point array. Here, a diode generally refers to any two-terminal device having a characteristic that when its applied voltage is smaller than the read voltage or the applied voltage is opposite to the read voltage, its resistance is greater than its resistance at the read voltage. Examples of the diode include a semiconductor diode (such as a pin silicon diode) and a metal oxide diode (such as a titanium oxide diode, a nickel oxide diode, etc.).

The

storage layers

16A, 16B constitute at least one three-dimensional memory array 16 and the substrate layer 0K contains a three-dimensional memory array 16 Peripheral circuit. Wherein, some of the peripheral circuits are located under the three-dimensional memory array, which are referred to as the lower peripheral circuits of the array; and another part of the peripheral circuits are located outside the three-dimensional memory array, which are referred to as array peripheral circuits 18 . Since the space 17 above the array peripheral circuit 18 does not contain a memory cell, the space is actually wasted.

U.S. Patent No. 7,388,476 discloses an integrated 3D-M chip 20 which can directly use the power supply voltage supplied by the host 23 and exchange address/data directly with the host 27 . Here, the host is a device that directly uses the chip 20, and the address/data 27 used by the host is a logical address/data.

As shown in FIG. 1B, the integrated 3D-M chip 20 includes a 3D-M core region 22 and an intermediate circuit region 28 . The 3D-M core area 22 contains multiple 3D storage arrays (such as 22aa, 22ay) and its decoders (such as 24, 24G). These decoders 24 include a local decoder ( Local decoder ) 24 and global decoder (24G). Where local decoder 24 addresses the address of a single 3D storage array / The data is decoded and the overall decoder 24G decodes the overall address/data 25 into a single three dimensional memory array. Note that the address/data 25 of the 3D-M core area 22 is the physical address. / Data.

The intermediate circuit area 28 contains an intermediate circuit between the 3D-M core area 22 and the host. The intermediate circuit 28 implements voltage, data, and address conversion between the 3D-M core area 22 and the host. For example, it converts the supply voltage 23 into a read voltage V _R or / and a write (program) voltage V _W , converting the logical address / data 27 and the physical address / data 25 to each other. The intermediate circuit 28 includes a read/write voltage generator 21 and an address/data converter 29. Among them, the read/write voltage generator 21 includes a bandgap reference circuit (precise reference voltage source) 21B, a read voltage generator 21R, and a charge pump 21W (refer to US Pat. No. 6,486,728). The address/data converter 29 includes an error check and correction circuit (ECC) 29E, a page register 29P, and a smart write controller 29W. The ECC circuit 29E performs ECC decoding on the data read from the three-dimensional memory array while performing error checking and correction (refer to U.S. Patent No. 6,591,394); the page register 29P functions to temporarily store data between the host and the three-dimensional memory array, and it also functions. The data can be ECC encoded (refer to US Pat. No. 8,223,525); the intelligent write controller 29W monitors the write error during the programming process, and once the write error occurs, the self-repair mechanism is initiated to write the data into the redundant row (refer to the US patent) 7,219,271). The prior art integrated 3D-M chip 20 implements voltage, data, and address conversion inside the chip. In general, the intermediate circuit 28 is an array outer peripheral circuit 18.

technical problem

In the prior art integrated 3D-M chip 20, the three-dimensional memory array is integrated with all intermediate circuit components on one chip. Since the intermediate circuit occupies a large amount of chip area in the 3D-M chip 20, the integrated 3D-M chip 20 has a lower array efficiency. Here, the array efficiency is defined as the ratio of the total storage area (ie, the chip area for storing user data) to the total chip area. In 3D-M, the total storage area A _M is the total area of the storage element for storing user data projected onto the surface of the chip, which can be expressed as: A _M = A _c * C _L = (4F ² ) * C _{3D -M} /N. Where A _c is the chip area occupied by a single storage element, C _L is the amount of data stored in one storage layer, F is the half cycle of the address line, C _3D-M is the storage capacity of 3D-M, and N is 3D- The number of all storage tiers in M. The following paragraphs take two 3D-M as examples to calculate their array efficiency.

The first example of 3D-M is 3D-on-a-chip memory (3D-OTP) (see Crowley et al., 512Mb PROM with 8 layers of antifuse/diode cells, 2003 International Solid State Circuits Conference, Figure 16.4.5). The 3D-OTP chip has a storage capacity of 512Mb and contains 8 memory layers and a 0.25um production process. Its total storage area is (4*0.25um ² )*512Mb/8 = 16mm ² . Since the total chip area is 48.3 mm ² , the array efficiency of the 3D-OTP chip is ~33%.

The second example of 3D-M is a three-dimensional resistive memory (3D-ReRAM) (see Liu et al., "A 130.7mm ² 2-Layer 32Gb ReRAM Memory Device in 24nm Technology", 2013 International Solid State Circuits Conference, Figure 12.1. 7). The 3D-ReRAM chip has a storage capacity of 32Gb and contains 2 memory layers and uses a 24nm production process. Its total storage area is (4*24nm ² )*32Gb/2 = 36.8mm ² . Since the total chip area is 130.7 mm ² , the array efficiency of the 3D-ReRAM chip is ~28%.

The mainstream view of integrated circuits is that integration reduces costs. Unfortunately, this view is not universal, it is in 3D-M Not in the middle. Since the intermediate circuit is weighted by the front-end process, and the rear-end process of the three-dimensional memory array is heavy and its production cost is higher than that of the intermediate circuit, the consequence of blindly integrating the intermediate circuit and the three-dimensional memory array is that the expensive process for manufacturing the three-dimensional memory array has to be used. The process of manufacturing intermediate circuits not only does not reduce costs, but increases costs. In addition, since the intermediate circuit can only use the same number of metal layers as the three-dimensional memory array (for example, only two layers), the design of the intermediate circuit is cumbersome, and the required chip area is large. In addition, due to 3D-M memory cells are generally subjected to high-temperature processes, and intermediate circuits require high-temperature interconnect materials such as tungsten (W). These materials generally have poor electrical conductivity, which makes 3D-M The overall performance is degraded.

Technical solution

The present invention follows the guiding principle of separating three-dimensional circuits and two-dimensional circuits into different chips in order to optimize them separately; in order to improve array efficiency, voltage, address and data should be avoided in a three-dimensional array chip. Accordingly, the present invention proposes a separate three-dimensional memory containing an intermediate circuit chip (separation 3D-M ), it contains at least one three-dimensional array chip (three-dimensional circuit) and at least one intermediate circuit chip (two-dimensional circuit). The three-dimensional array chip is constructed in a three-dimensional space and contains a plurality of functional layers (ie, storage layers), which generally do not contain transistors; the intermediate circuit chip is constructed in a two-dimensional space and contains only one functional (analog, digital) layer. Mainly through the transistor to complete its function. Separating the three-dimensional memory circuit and the two-dimensional intermediate circuit into different chips can be optimized separately. Since the three-dimensional array chip contains fewer intermediate circuit components, its array efficiency can be greater than 40%. If the 3D array chip does not include a read/write voltage generator and an address/data converter, its array efficiency can easily exceed 40% or even reach ~60%. Separation 3D-M Support for multiple 3D array chips, which can be used for high-capacity 3D-M memory cards and 3D-M solid state drives.

Since the intermediate circuit chip can be fabricated using a separate, inexpensive process flow, the cost of the wafer is much lower than that of the three-dimensional array chip. So for the same storage capacity, the total cost of separating 3D-M is lower than the integrated 3D-M . In addition, since the number of metal layers in the intermediate circuit chip is no longer limited by the three-dimensional array chip, it can contain more metal layers (such as from two layers of metal to four layers of metal), so the intermediate circuit components thereon (such as Read / The design of the write voltage generator, address/data converter is simpler and requires a smaller chip area. In addition, since the intermediate circuit chip does not need to undergo a high temperature process, its interconnects can use high speed interconnect materials such as copper ( Cu), etc., these materials can improve the overall performance of 3D-M.

Intermediate circuit components include read/write voltage generators and addresses / Data converter. In an embodiment, the intermediate circuit components are integrated in the same intermediate circuit chip, so that the three-dimensional array chip can ensure high array efficiency and reduce the packaging cost of the intermediate circuit chip. In another embodiment, these components can also be separated into different chips. This means three-dimensional storage circuit (three-dimensional storage array), two-dimensional analog circuit (read / Write voltage generator) and two-dimensional digital circuit (address / data converter) are separated into different chips, and their performance can be optimized by different process flows: storage performance optimization of three-dimensional array chip, read / Write voltage generator chip for analog performance optimization, and digital performance optimization for address / data converter.

Beneficial effect

The main advantageous effect of the present invention is to provide a more inexpensive three-dimensional memory (3D-M).

Another advantageous effect of the present invention is to provide a 3D-M which is excellent in performance.

Another benefit of the present invention is to increase the array efficiency of the three-dimensional array chip.

DRAWINGS

1A is a cross-sectional view of a prior art three-dimensional memory (3D-M); FIG. 1B is an integrated 3D-M The system architecture of the chip (prior art).

Figure 2A - Figure 2H are block diagrams of eight separate 3D-Ms with intermediate circuit chips.

Figure 3A is a cross-sectional view of a three-dimensional array chip in a separate 3D-M; Figure 3B is a cross-sectional view of a circuit chip in between.

Figure 4A - Figure 4C are cross-sectional views of three separate 3D-M.

Figures 5A-5C are circuit diagrams of three read/write voltage generators.

Figure 6A - Figure 6B are circuit block diagrams of two address/data converters.

It is noted that the drawings are only schematic and are not drawn to scale. In order to be conspicuous and convenient, some of the dimensions and structures in the figures may be enlarged or reduced. In the different embodiments, the same symbols generally indicate corresponding or similar structures.

Embodiments of the invention

In the present invention, ' / ' denotes a relationship between 'and' or 'or'. For example, read / The write voltage generator indicates that it can generate only the read voltage, or only the write voltage, or both the read voltage and the write voltage; address / A data converter means that it can convert only addresses, or just convert data, or both address and voltage.

In the present invention, the intermediate circuit refers to a circuit between the 3D-M core area and the host that implements voltage, address or/and data conversion between the host and the 3D-M core area. For example, it converts the external voltage (ie, supply voltage V _DD ) from the host, the external address (ie, the logical address), and the external data (ie, the logical data) into the internal voltage of the 3D-M core region (ie, the read voltage V _R and write Voltage V _W ), internal address (ie physical address) and internal data (ie physical data). The intermediate circuit components include a read/write voltage generator and an address/data converter.

Figure 2A - Figure 2H show eight separate three-dimensional memories (separated 3D-M) with intermediate circuit chips 50 . Each of these embodiments includes at least one three-dimensional array chip (three-dimensional circuit) and at least one intermediate circuit chip (two-dimensional circuit). Among them, the three-dimensional array chip is constructed in a three-dimensional space and contains a plurality of functional (storage) layers, and the intermediate circuit chip is constructed in a two-dimensional space and contains only one functional (analog, digital) layer. Separating the three-dimensional memory circuit and the two-dimensional intermediate circuit into different chips can be optimized separately.

The split 3D-M 50 includes an interface 52 that can physically interface with various hosts and communicate in accordance with a communication standard. The interface 52 includes a plurality of contact ends 52x, 52y, 52a-52b that are coupled to corresponding contact ends of the host jack. For example, the host provides a supply voltage V _DD and a ground voltage V _SS for the split 3D-M 50 through the power supply terminal 52x and the ground terminal 52y, respectively; the host exchanges address/data with the separate 3D-M 50 via the signal terminals 52a - 52d. Since these addresses/data are used directly by the host, they are logical addresses/data.

The split 3D-M 50 in Figure 2A is a 3D-M memory card. It contains a separate three-dimensional array chip (three-dimensional circuit) 30 and a separate intermediate circuit chip (two-dimensional circuit) 40 . The three-dimensional array chip 30 contains a 3D-M core region 22 as in Figure 1B, which contains a plurality of three-dimensional memory arrays (e.g., 22aa, 22ay) and decoders thereof (e.g., 24, 24G). The three-dimensional array chip 30 also includes an address/data converter 47 that converts the logical address/data of the host and the physical address/data of the 3D-M core area 22 to each other. The intermediate circuit chip 40 includes a read/write voltage generator 41 that takes the power supply voltage V _DD from the host, converts it into a read/write voltage, and transmits it to the three-dimensional array chip 30 through the power bus 56. This read/write voltage is supplied. Here, the read/write voltage may be only the read voltage V _R , or only the write voltage V _W , or both the read voltage V _R and the write voltage V _W , which have different values from the power supply voltage V _DD . In this embodiment, the read/write voltage includes a read voltage V _R and two write voltages V _W1 , V _W2 . In other embodiments, the read/write voltage can include more than one read voltage or two write voltages. Since the three-dimensional array chip 30 does not include the read/write voltage generator 41, its array efficiency can be greater than 40%.

The split 3D-M 50 in Figure 2B is also a 3D-M memory card. Similar to Figure 2A, the intermediate circuit chip 40* An address/data converter 47 is included, and the address/data converter 47 includes an address translator 43 and a data converter 45. Where address translator 43 will be the external bus 54 The logical address on the internal bus 58 (including the signals from the contacts 52a - 52d) is converted to the physical address on the internal bus 58; the data converter 45 takes the logical data on the external bus 54 to the internal bus The physical data on 58 is converted to each other. Here, the address/data converter 47 can implement only address translation, or only data conversion, or both address and data conversion. Since the 3D array chip 30 does not contain an address / Data Converter 47, whose array efficiency can be greater than 40%.

The separation 3D-M 50 in Figure 2C is also a 3D-M memory card. With Figure 2A and Figure 2B Similarly, the intermediate circuit chip 40 includes a read/write voltage generator 41 and an address/data converter 47. In other words, the read/write voltage generator 41 and the address/data converter 47 is integrated in the same intermediate circuit chip 40. Since the 3D array chip 30 does not include an address/data converter and a read/write voltage generator, its array efficiency can easily exceed 40% or even reach ~60%. Integrating the read/write voltage generator 41 and the address/data converter 47 into the same intermediate circuit chip 40 ensures the three-dimensional array chip 30 It has higher array efficiency and lowers the packaging cost of the intermediate circuit chip 40.

The split 3D-M 50 in Figure 2D is also a 3D-M memory card. The difference with Figure 2C is that read / The write voltage generator 41 and the address/data converter 47 are separated into different

intermediate circuit chips

40, 40*. In this embodiment, a three-dimensional memory circuit (three-dimensional array chip 30) ), a two-dimensional analog circuit (read/write voltage generator 41) and a two-dimensional digital circuit (address/data converter 47) are further separated into

different chips

30, 40, 40* In this way, different performances can be optimized by different processes: storage performance optimization of the three-dimensional array chip 30, simulation performance optimization of the read/write voltage generator chip 40, and address/ Data Converter 40* for digital performance optimization. Since the three-dimensional array chip 30 does not include the read/write voltage generator 41 and the address/data converter 47, its array efficiency can easily exceed 40. %, even up to ~60%.

Due to the intermediate circuit chip (including the read/write voltage generator chip 40 and the address/data converter chip 40*) It can be manufactured in a separate, inexpensive process flow, and its wafer cost is much lower than that of the three-dimensional array chip 30. As a simple estimate, if the

intermediate circuit chip

40, 40* wafer cost is a three-dimensional array chip Half of 30, and the array efficiency is increased from 30% of the integrated 3D-M chip 20 to 40% of the 3D array chip 30 (Figure 2A - Figure 2B) ), then for the same storage capacity, the total cost of separating the 3D-M 50 is ~88% of the integrated 3D-M 20; if the array efficiency is increased to 60% (Figure 2C - Figure 2D) ), then the total cost of separating the 3D-M 50 is only ~75% of the integrated 3D-M 20.

The split 3D-M 50 in Figure 2E is also a 3D-M memory card. The difference from Figure 2C is that the three-dimensional array chip 30 also includes a serializer-deserializer (Ser-Des) 49 that will parallel digital signals within the three-dimensional array chip 30 (eg, address/data/instructions/ State, etc.) is converted to its external serial digital signal 58'; the address/data converter chip 40* also contains a second serializer-deserializer (Ser-Des) 49* which will address / The parallel digital signal (such as address/data/instruction/status, etc.) inside the data converter chip 40* is converted into its external serial digital signal 58'. By serializing the digital signal, Figure 2E The number of connecting wires 58' (such as leads, solder balls) between the middle three-dimensional array chip 30 and the address/data converter chip 40* is less than the connecting line in Fig. 2C. The number of this can help reduce packaging costs.

The split 3D-M 50 in Figure 2F is also a 3D-M memory card. Similar to Figure 2E, it is in Figure 2D A first serializer-deserializer (Ser-Des) 49 is added to the three-dimensional array chip 30, and a second serializer-deserializer 49* is added to the intermediate circuit chip 40. Thus, Figure 2F The number of connection lines 58' between the middle three-dimensional array chip 30 and the intermediate circuit chip 40 is less than the number of connection lines 58 in Fig. 2D, which can help reduce packaging costs.

The separation in Figure 2G 3D-M 50 is a large capacity 3D-M memory card or a 3D-M SSD. It contains an intermediate circuit chip 40 and a plurality of three-

dimensional array chips

30a, 30b... 30w. The intermediate circuit chip 40 includes a plurality of read/

write voltage generators

41a, 41b... 41w and multiple address /

data converters

47a, 47b... 47w. Each read/write voltage generator (such as 41a) is a three-dimensional array chip (such as 30a) Providing read voltage or / and write voltage; each address / data converter (such as 47a) performs address or / and data conversion for a three-dimensional array chip (such as 30a). Three-

dimensional array chip

30a, 30b... 30w makes up two channels: A and B. In channel A, the internal bus 58A from the intermediate circuit chip 40 is a three-

dimensional array chip

30a, 30b... 30i The physical address/data is provided; in channel B, the internal bus 58B from the intermediate circuit chip 40 provides physical addresses for the three-

dimensional array chips

30r, 30s... 30w / Data. At the same time, the power bus 56 from the intermediate circuit chip 40 provides read for the

dimensional array chips

30a, 30b...30w / Write voltage. Although this embodiment has only two channels, a large-capacity 3D-M memory card and a 3D-M solid state hard disk can contain more channels for those skilled in the art.

Separation in Figure 2H The 3D-M 50 is also a large capacity 3D-M memory card or a 3D-M solid state drive. With Figure 2G The difference is that the read/

write voltage generators

41a, 41b... 41w and the address/

data converters

47a, 47b... 47w are separated into different

intermediate circuit chips

40, 40* Medium. Similar to FIG. 2D, this embodiment will have three-dimensional memory circuits (three-

dimensional array chips

30a, 30b...30w) and two-dimensional analog circuits (read/write voltage generator chip 40). ), the two-dimensional digital circuit (address/data converter chip 40*) is separated into different chips, so that their performance can be optimized separately by different processes.

3A-3B are separated 3D array chip 30 and intermediate circuit chip 40 in 3D-M 50 (including 40*) section view. The three-dimensional array chip 30 in Fig. 3A is formed in a three-dimensional space and contains a plurality of functional layers including a substrate layer 0K and

memory layers

16A, 16B. Substrate layer 0K Contains transistor 0t and its interconnect 0iA. The transistor 0t is formed on the three-dimensional array substrate 0A, and the interconnection 0iA includes two substrate metal layers 0M1, 0M2 . In order to accommodate the high temperature process required to fabricate memory cells (e.g., 5aa), the substrate metal layers 0M1, 0M2 are preferably made of a high temperature interconnect material such as tungsten (W).

Storage layers

16A and 16B contain multiple address lines (such as 2a, etc.) and multiple storage elements (such as 5aa). Wait). Each memory element can contain at least one of the following components, such as a printed storage element (see PCT application PCT/CN2012/080895), memristor Storage element, resistive storage element (RRAM or ReRAM), phase-change memory (PCM), programmable Metallization memory ( PMM ), or conductive-bridging random-access memory ( CBRAM )Wait. These components are typically combined with diode or diode-like components (ie, diode-like components) to implement a memory array. In order to reduce costs, storage layers 16A, 16B There are no transistor or transistor-like components (ie, transistors-like components). Of course, since the memory layer does not contain transistor-like components, the memory layers 16A, 16B The required analog functions (such as signal amplification) and digital functions (such as address decoding) are implemented in the substrate layer 0K.

The intermediate circuit chip 40 in Fig. 3B is formed in a two-dimensional space and contains only one functional layer, that is, the substrate layer 0K'. Substrate layer 0K 'includes transistor 0t and its interconnect 0iB. The transistor 0t is formed on the intermediate circuit substrate 0B, and the interconnection 0iB includes four metal layers 0M1' - 0M4'. Since the three-dimensional array chip 30 and the intermediate circuit chip 40 are two separate chips, the intermediate circuit chip 40 can be fabricated in an independent, inexpensive process flow instead of using an expensive, three-dimensional array chip. The craft to manufacture. Therefore, the wafer cost of the intermediate circuit chip 40 is much lower than that of the three-dimensional array chip 30.

Since it is a single chip, the intermediate circuit chip 40 can be integrated with the 3D-M chip 20 There are more metal layers (such as from two layers of metal to four layers of metal), so the intermediate circuit components on it (such as read / write voltage generator, address / The data converter is designed to be simpler and requires a smaller chip area. In addition, since the metal layer 0M1' - 0M4' of the intermediate circuit chip 40 does not need to undergo a high temperature process, its interconnection 0iB High performance interconnect materials such as copper (Cu) can be used. These materials can improve the functionality of the intermediate circuit chip 40 and can also improve the overall performance of the 3D-M.

4A-4C are cross-sectional views of three separate 3D-M 50s. Figure 3A - Figure 4B Separation 3D-M 50 is a multi-chip package (MCP). The 3D-M multi-chip package 50 of FIG. 4A contains two separate chips: a three-dimensional array chip 30 and an intermediate circuit chip 40. . The

chips

30, 40 are stacked on an interposer 53 and located in the same package 51. The lead wire 55 is the

chip

30 , 40 provides electrical connection. In addition to the leads, solder bumps and the like can also be used. In order to ensure data security, the

chips

30, 40 are preferably packaged in a molding compound (molding) Compound ) 57 inside. In the present embodiment, the three-dimensional array chip 30 is stacked on the intermediate circuit chip 40. In other embodiments, the intermediate circuit chip 40 can be stacked on a three-dimensional array chip. 30, or the three-dimensional array chip 30 is stacked face-to-face with the intermediate circuit chip 40, or the three-dimensional array chip 30 and the intermediate circuit chip 40 are juxtaposed. The 3D-M multi-chip package 50 The circuit block diagram in Figure 2A - Figure 2F can be used.

The 3D-M multi-chip package 50 in Figure 4B contains at least two three-

dimensional array chips

30a, 30b And an intermediate circuit chip 40. These

chips

30a, 30b and 40 are three separate chips. They are located in the same package 51. Wherein, the three-dimensional array chip 30a Stacked on the three-dimensional array chip 30b, the three-dimensional array chip 30b is stacked on the intermediate circuit chip 40. Lead 55 provides electrical connections for

chips

30a, 30b, and 40. The 3D-M Multi-Chip Package 50 The circuit block diagram in Figure 2G - Figure 2H can be used.

The split 3D-M in Figure 4C is a 3D-M Multi-Chip Component (MCM) 50* with a frame 66 . The frame 66 contains two separate packages: a three-dimensional array package 62 and an intermediate circuit package 64. Wherein, the three-dimensional array package 62 includes two three-

dimensional array chips

30a, 30b The intermediate circuit package 64 contains an intermediate circuit chip 40. Frame 66 also provides an electrical connection (not shown here) for three-dimensional array package 62 and intermediate circuit package 64. The 3D-M multi-chip component 50* The circuit block diagram in Figure 2G - Figure 2H can be used.

5A to 5C are circuit diagrams of three kinds of read/write voltage generators 41. Read/Write Voltage Generator 41 It is best to use a DC-DC converter (DC-DC converter) ). The DC-DC converter includes a booster and a buck. The output voltage of the booster is higher than the input voltage, and the input voltage of the buck is lower than the input voltage. Examples of boosters include charge pumps (charge pumps) 5A) and Boost converter (Boost converter, Fig. 5B) and so on. Examples of bucks include low dropout regulators (low dropout, Figure 5C) and Buck converter, etc.

FIG 5A is read / write voltage generator 41 comprises a charge pump 72, whose output voltage V _out is greater than the input voltage V _in. In general, charge pump 72 also contains one or more capacitors. 5B, the read / write voltage generator 41 comprises a high frequency Boost converter 74, the output voltage V _out is greater than the input voltage V _in. The Boost converter 74 also contains an inductor. The inductor is preferably a thin inductor to meet the thickness requirements of the memory card or solid state drive. FIG. 5C read / write voltage generator 41 comprises a low dropout voltage regulator 76, output voltage V _out which is less than the input voltage V _in. In general, the low dropout regulator 76 also contains one or more capacitors.

Figures 6A-6B show two components of the address/data converter 47: address translator 43 and data converter, respectively. 45. Fig. 6A shows an address converter 43. It converts the logical address 54A from the host into the physical address 58A of the three-dimensional array chip 30. Address converter 43 contains a processor 92 and a memory 94. The memory 94 stores an address mapping table 82, a fault block table 84, and a wear management table 86. These status tables 82, 84, 86 Usually stored in read-only memory (ROM). It is loaded into random access memory (RAM) at the time of use. Here, the read only memory can be a nonvolatile memory (NVM) ), such as flash memory. For an address/data converter 47 that supports multiple 3D array chips (30a, 30b... 30w in Figure 2G - Figure 2H), memory 94 The state tables 82, 84, 86 are stored for all three-

dimensional array chips

30a, 30b... 30w, which are shared by all three-

dimensional array chips

30a, 30b... 30w.

In the various status tables 82, 84, 86 of the memory 94, the address mapping table 82 Stores the mapping between logical addresses and physical addresses; the fault block table 84 stores the addresses of faulty memory blocks in the 3D storage array; the wear management table 86 records each memory block read / The number of times written. Here, 'memory block' refers to a memory allocation unit that can be sized from one memory element to all memory elements in a three-dimensional memory array.

During the read process, once the processor 92 receives the logical address 54A of the memory block that needs to be read, it slave address map 82 Get the corresponding physical address 58A. During the write process, once the processor 92 receives the logical address 54A of the memory block to be written, it slave address mapping table 82, fault block table 84, and wear management table. Select an unoccupied, fault-free, and less-used block of memory to write data. The address of the selected memory block is the physical address.

Figure 6B shows a data converter 45. It converts the logical data 54D from the host into the physical data of the 3D storage array 58D, or convert the physical data 58D of the 3D storage array into logical data 54D output to the host. The data converter 45 contains an error check correction (ECC) encoder 96 and a ECC Decoder 98. The ECC encoder 96 converts the input logical data 54D into physical data 58D to be stored to the three-dimensional storage array. ECC Decoder 98 The physical data 58D read out from the three-dimensional memory array is converted into logical data 54D to be output. During this process, the error bits in physical data 58D are checked and corrected. ECC for 3D-M The code includes Reed-Solomon code, Golay code, BCH code, multi-dimensional parity code and Hamming code.

It is to be understood that the form and details of the invention may be modified without departing from the spirit and scope of the invention. Therefore, the invention should not be limited in any way by the spirit of the appended claims.

Claims

A three-dimensional memory (50), comprising:

a three-dimensional array chip (30), the three-dimensional array chip (30) comprising at least one three-dimensional memory array (22aa...), the three-dimensional memory array (22aa...) comprising a plurality of memory layers (16A, 16B...) stacked on each other, the memory layer containing no transistor-like components;

An intermediate circuit chip (40), the intermediate circuit chip including at least one read/write voltage generator (41), the read/write voltage generator (41) providing at least one and a power supply voltage for the three-dimensional array chip (30) V DD ) different read voltage (V R ) or / and write voltage (V W );

The three-dimensional array chip (30) and the intermediate circuit chip (40) are two different chips.
A three-dimensional memory (50), comprising:

a three-dimensional array chip (30), the three-dimensional array chip (30) comprising at least one three-dimensional memory array (22aa...), the three-dimensional memory array (22aa...) comprising a plurality of memory layers (16A, 16B...) stacked on each other, the memory layer containing no transistor-like components;

An intermediate circuit chip (40*), the intermediate circuit chip (40*) containing at least one address/data converter (47), the address / The data converter (47) converts the address/data (54) of the host to the address/data (58) of the three-dimensional array chip (30);

The three-dimensional array chip (30) and the intermediate circuit chip (40*) are two different chips.
A three-dimensional memory (50), comprising:

a three-dimensional array chip (30), the three-dimensional array chip (30) comprising at least one three-dimensional memory array (22aa...), the three-dimensional memory array (22aa...) comprising a plurality of memory layers (16A, 16B...) stacked on each other, the memory layer containing no transistor-like components;

An intermediate circuit chip (40) comprising a read/write voltage generator (41) and an address/data converter (47), the read/write voltage generator (41) being the three-dimensional array chip ( 30) providing at least one read voltage (V R ) or / and write voltage (V W ) different from the power supply voltage (V DD ), the address/data converter (47) and the host address/data (54) The address/data (58) of the three-dimensional array chip (30) is converted to each other;

The three-dimensional array chip (30) and the intermediate circuit chip (40) are two different chips.
A three-dimensional memory (50), comprising:

a three-dimensional array chip (30), the three-dimensional array chip (30) comprising at least one three-dimensional memory array (22aa...), the three-dimensional memory array (22aa...) comprising a plurality of memory layers (16A, 16B...) stacked on each other, the memory layer containing no transistor-like components;

a first intermediate circuit chip (40), the first intermediate circuit chip comprising at least one read/write voltage generator (41), the read/write voltage generator (41) providing at least one for the three-dimensional array chip (30) a different read voltage (V R ) or / and write voltage (V W ) than the supply voltage (V DD );

a second intermediate circuit chip (40*), the second intermediate circuit chip containing at least one address/data converter (47), the address/data converter (47) converting the address/data (54) of the host with the address/data (58) of the three-dimensional array chip (30);

The three-dimensional array chip (30), the first and second intermediate circuit chips (40, 40*) For three different chips.
A three-dimensional memory (50), comprising:

First and second three-dimensional array chips (30a, 30b), the first and second three-dimensional array chips (30a, 30b) Each of the three-dimensional storage arrays (22aa...) contains a plurality of storage layers (16A, 16B...) stacked on each other. The storage layer does not contain a transistor-like component;

At least one intermediate circuit chip (40 or 40*) having a read/write voltage generator (41) and an address/data converter At least one of (47), the intermediate circuit chip (40 or 40*) implements voltage, data or / between the first and second three-dimensional array chips (30a, 30b) and the host And address translation;

The first and second three-dimensional array chips (30a, 30b) and the intermediate circuit chip (40 or 40*) For at least three different chips.
A memory according to claims 1 and 3 - 5, characterized in that said read/write voltage generator (41) comprises a DC-DC converter ( DC - DC converter ).
A memory according to claims 2 - 5, characterized in that the address/data converter (47) is an address translator (43) The address translator (43) contains at least one of an address mapping table (82), a fault block table (84), and a wear management table (86).
A memory according to claims 2 - 5, characterized in that the address/data converter (47) is a data converter (45). The data converter (45) contains at least one of an ECC encoder (96) and an ECC decoder (98).
The memory according to claim 2 - 5, wherein the three-dimensional array chip (30) further comprises a serializer-deserializer (49) .
A memory according to claims 1 - 5, characterized in that said three-dimensional memory contains a three-dimensional read only memory (3D-ROM) .
A memory according to claim 10, further characterized in that said 3D-ROM contains a three-dimensional electrically programmable read only memory (3D-EPROM) ) or 3D mask programming read-only memory (3D-MPROM).
A memory according to claims 1 - 5, characterized in that said three-dimensional memory contains a three-dimensional random read memory (3D-RAM) .
A memory according to claims 1 - 5, characterized in that said three-dimensional memory contains memristor, resistive Random-access memory ( RRAM or ReRAM ), phase-change memory ( PCM ), Programmable metallization cell (PMC) and conductive-bridging random-access At least one of memory ( CBRAM ).
The memory according to any one of claims 1 to 5, wherein the memory is at least one of a memory card, a solid state hard disk, a multi-chip package, and a multi-chip module. .
The memory according to any of claims 1 - 5, wherein the array efficiency of said three-dimensional array chip is greater than 40%.