CN106206587B - The longitudinal memory of three-dimensional of address/data converter separation - Google Patents
The longitudinal memory of three-dimensional of address/data converter separation Download PDFInfo
- Publication number
- CN106206587B CN106206587B CN201510228946.8A CN201510228946A CN106206587B CN 106206587 B CN106206587 B CN 106206587B CN 201510228946 A CN201510228946 A CN 201510228946A CN 106206587 B CN106206587 B CN 106206587B
- Authority
- CN
- China
- Prior art keywords
- address
- chip
- data converter
- dimensional
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention proposes a kind of separation 3D MV50, it contains an at least three-dimensional array chip 30 and at least an address/data converter chip 40*.Three-dimensional array chip 30 contains multiple vertical storage strings 16X, 16Y.At least an address/data converter is located in address/data converter chip 40* rather than in three-dimensional array chip 30.Three-dimensional array chip 30 and address/data converter chip 40* have entirely different rear end（BEOL）Structure.
Description
Technical field
The present invention relates to integrated circuit memory fields, more precisely, being related to three-dimensional longitudinal memory（3D-MV）.
Background technology
Three-dimensional storage（3D-M）It is a kind of monomer（monolithic）Semiconductor memory, it contains multiple be stacked with
Storage member.3D-M includes 3 D ROM（3D-ROM）Memory is read with three-dimensional random（3D-RAM）.3D-ROM can
To be further divided into three-dimensional masking film program read-only memory（3D-MPROM）And three-dimensional electric programming read-only memory（3D-
EPROM）.Based on its programming mechanism, 3D-M can be 3D-memristor, 3D-RRAM or 3D-ReRAM（resistive
random-access memor）、3D-PCM（phase-change memory）、3D-PMC（programmable
metallization-cell memory）Or 3D-CBRAM（conductive-bridging random-access
memory）Deng.
United States Patent (USP) 5,835,396 discloses a kind of 3D-M, i.e. 3D-ROM.As shown in Figure 1A, 3D-M chips 20 contain one
Substrate circuitry layer 0K and multiple it is stacked in accumulation layer 16A, 16B on substrate circuitry layer 0K and being stacked with.Substrate circuitry layer 0K
Contain transistor 0t and its interconnection line 0i.Transistor 0t is formed in semiconductor substrate 0.Substrate interconnection line 0i is transistor 0t real
Now it is connected with each other.In this example, substrate interconnection line 0i contains metal layer 0M1,0M2.
Accumulation layer 16A, 16B is stacked on substrate circuitry layer 0K, they are by contacting access opening（Such as 1av）With substrate 0
Coupling.Each accumulation layer（Such as 16A）Contain a plurality of top address line（Such as 2a）, bottom address wire（Such as 1a）With storage member（Such as 5aa）.It deposits
Diode, transistor or other device may be used in Chu Yuan.In various storages member, there is minimum using the storage member of diode
Area, only 4F2（F is minimum feature size）.Diode storage member is typically incorporated in the intersection of top address line and bottom address wire
At point, to constitute a crosspoint（cross-point）Array.Here, diode refers to any two end with the following characteristics
Device：When the numerical value of its applied voltage is opposite with read voltage less than the direction of read voltage or applied voltage, resistance is much larger than
Its resistance under read voltage.The example of diode includes semiconductor diode（Such as p-i-n silicon diodes）It is aoxidized with metal
Object diode（Such as titanium oxide diode, nickel oxide diode）Deng.
An accumulation layer 16A, 16B composition at least 3D-M arrays 16, and weeks of the substrate circuitry layer 0K then containing 3D-M arrays 16
Side circuit.Wherein, a part of peripheral circuit is located at below 3D-M arrays, they are referred to as array following peripheral circuit；Another part
Peripheral circuit is located at outside 3D-M arrays, they are referred to as array outer periphery circuit 18.Since array outer periphery circuit 18 compares 3D-
M array 16 contains less rear end（Back-end-of-line, referred to as BEOL）Layer, the sky of 18 top of array outer periphery circuit
Between 17 without containing storage member, which is actually wasted.In the present specification, BEOL layer refers to higher than one layer of substrate
Conductor wire.In figure 1A, 3D-M arrays 16 contain 6 BEOL layers（Including 2 substrate interconnection line layer 0M1,0M and accumulation layer
2 address-wire layer 1a-4a that 16A, 16B respectively contain）；And array outer periphery circuit 18 contains only 2 BEOL layers（2 substrate interconnections
Line layer 0M1,0M2）.
United States Patent (USP) 7,388,476 discloses a kind of integrated 3D-M chips, and cubical array and its peripheral circuit are all integrated
In same chip.As shown in Figure 1B, which contains cubical array region 22 and peripheral circuit area 28.Three
It ties up array region 22 and contains multiple 3D-M arrays（Such as 22aa, 22ay）And its decoder（Such as 24,24G）.These decoders 24 wrap
Include local decoder 24 and whole decoder 24G.Wherein, local decoder 24 carries out the address/data of single 3D-M arrays
Decoding, whole decoder 24G decode total address/data 25 into single 3D-M arrays.
Circuit unit in peripheral circuit area 28 enables integrated 3D-M chips 20 to complete basic store function, they can
Think cubical array region 22 and host（The equipment for directly using the chip 20）Between realize voltage, data, address conversion.
Peripheral circuit 28 contains read/write voltage generator 21 and address/data converter 29.Wherein, read/write voltage generator 21 will be electric
Source voltage 23 is converted into read voltage VROr/and it writes（Programming）Voltage VW；Address/data converter 29 by logical address/data 27 with
Physical address/data 25 are mutually converted.In the present specification, logical address/data 27 are the address/datas that host uses；And
Physical address/data 25 are the address/datas that 3D-M arrays use.
Example in Figure 1A and Figure 1B is three-dimensional lateral memory（3D-MH）, basic storage assembly is horizontal accumulation layer.
Above-mentioned introduction can be used for three-dimensional longitudinal memory（3D-MV）, basic storage assembly is vertical storage string.
United States Patent (USP) 8,638,611 discloses a kind of 3D-MV.It is a kind of longitudinal direction NAND（vertical NAND）.In addition to
Longitudinal NAND, 3D-ROM, 3D-RAM, 3D-memristor, 3D-RRAM or 3D-ReRAM, 3D-PCM, 3D-PMC, 3D-CBRAM
3D-M can also be formedV.As shown in Fig. 2, the 3D-MVChip 20 contains an at least 3D-MVArray 16 and peripheral circuit 18.3D-MV
Array 16 contains multiple vertical storage strings 16X, 16Y.Each storage string（Such as 16X）Storage member containing multiple vertical stackings（Such as
8a-8h）, these storages are first to be intercoupled by a vertical address wire.Each storage member（Such as 8f）Containing there are one longitudinal crystal
Pipe, the vertical transistor contain grid 6, storage film 7 and longitudinal channel 9.In a vertical storage string, each storage member（Such as
8f）Grid 6 constitute a BEOL layer.In fig. 2,3D-MVArray 16 contains 8 BEOL layers, i.e. accumulation layer 8a-8h.
Since vertical storage string 16X, 16Y occupies substrate 0 below（Fig. 2）, 3D-MVChip 20 cannot contain array
Following peripheral circuit, and array outer periphery circuit 18 can only be contained.This and 3D-MH（Figure 1A）Difference, 3D-MHChip 20 can contain
Array following peripheral circuit.3D-MVThe peripheral circuit 18 of array 16 contains substrate transistor 0t and its substrate interconnection line 0i.Substrate is brilliant
Body pipe 0t is formed in semiconductor substrate 0, it is traditional planar ransistor.Substrate interconnection line 0i is substrate transistor 0t real
Now it is connected with each other.In this example, peripheral circuit 18 contains 2 BEOL layers, i.e. substrate interconnection line layer 0M1,0M2.
The 3D-M of conventional artVIt is integrated 3D-MV.That is, 3D-MVArray 16 and peripheral circuit 18 are integrated in same
3D-MVIn chip 20.Since their manufacturing process mismatches, 3D-MVArray 16 and the needs of peripheral circuit 18 are respectively formed.Phase
3D-M in Ying Di, Fig. 2VChip 20 contains 10 BEOL layers, including 3D-MV8 BEOL layers and peripheral circuit 18 of array 16
2 BEOL layers.
The Main Viewpoints of the prior art are：Integrated level is the bigger the better, i.e., integrated to reduce cost and improve performance.Unfortunate
It is that the viewpoint is to 3D-MVIt is invalid.For first, since the BEOL layer of vertical storage string 16X, 16Y is far more than peripheral circuit
18, blindly integrated direct result must not be exactly manufactures this without manufacturing the expensive process flow of vertical storage string 16X, 16Y
Carry out very simple peripheral circuit 18, this can increase 3D-MVOverall cost.Secondly as 3D-MVChip 20 is mainly for 3D-MV
Array 16 optimize, it have to sacrifice peripheral circuit 18 performance.Such as say, peripheral circuit 18 contains a few（Such as 2）
Substrate interconnection line layer or the slower high temperature resistant interconnection material of operating speed（Such as use tungsten as conductive material, silica conduct
Insulating materials）, this can reduce 3D-MVOverall performance.
Invention content
The main object of the present invention is to reduce three-dimensional longitudinal memory（3D-MV）Overall price.
It is another object of the present invention to improve 3D-MVOverall performance.
In order to realize that these and other purpose, the present invention defer to following design principle：By three-dimensional circuit and two-dimensional circuit
Different chips are separated to, so that they are separately optimized.Such as say, by 3D-MVArray 16（Three-dimensional circuit）And voltage generator
（Two-dimensional circuit）It is separated in different chips.Correspondingly, the present invention proposes a kind of separation 3D-MV, it contains at least one three-dimensional battle array
Row chip and at least an address/data converter chip.Three-dimensional array chip（Three-dimensional circuit）It builds in three dimensions and contains
There are multiple functional layers（Multiple accumulation layers being stacked with）, address/data converter chip（Two-dimensional circuit）Structure is two-dimentional empty
Between in and containing only there are one functional layers（That is converter containing address/data）.
In separation 3D-MVIn, since three-dimensional array chip and address/data converter chip can be separately designed and be made
It makes, they can have different rear ends（BEOL）Structure.Firstly, since address/data converter chip contain it is less
BEOL layer, wafer cost are far below three-dimensional array chip（Or integrated 3D-MVChip）.In one embodiment, cubical array
The first number of storage in chip contained by vertical storage string is much larger than the interconnection line number of plies of address/data converter chip.Correspondingly,
Detach 3D-MVOverall cost be less than integrated 3D-MV.Secondly as the rear end structure of address/data converter chip can be single
Solely optimization, the performance of address/data converter are better than integrated 3D-MVIn address/data converter（Or three-dimensional array chip
In peripheral circuit）.In one embodiment, the interconnection line number of plies of address/data converter chip is more than in three-dimensional array chip
Peripheral circuit.In another embodiment, high-performance interconnection wire material may be used in address/data converter chip（As used
Copper is as conductive material, and high-g value is as insulating materials；The peripheral circuit of three-dimensional array chip uses slow high temperature resistant
Interconnection material）.Correspondingly, 3D-M is detachedVOverall performance be better than integrated 3D-MV。
Correspondingly, the present invention proposes a kind of longitudinal memory of the three-dimensional of separation（3D-MV）(50), it is characterised in that including：
One contains an at least 3D-MVThe three-dimensional array chip (30) of array (36), the 3D-MV arrays (36) contain multiple vertical storage strings
(16X, 16Y), the storage that each vertical storage string contains multiple vertical stackings are first (8a-8h)；One contains at least partly address/number
According to the address/data converter chip (40*) of converter, the address/data converter is in host and the three-dimensional array chip
(30) into row address and/or data conversion between；The three-dimensional array chip (30) is free of the partial address/data conversion
Device, first (8a-8h) number of storage in the three-dimensional array chip (30) contained by vertical storage string (16X) be more than described address/
The interconnection line number of plies of data converter chip (40*), the three-dimensional array chip (30) and described address/data converter chip
(40*) is two different chips.
The present invention also proposes a kind of longitudinal memory of the three-dimensional of separation（3D-MV）(50), it is characterised in that including：One contains
An at least 3D-MVThe three-dimensional array chip (30) of array (36) and a peripheral circuit (38), the 3D-MVArray (36) is containing multiple
Vertical storage string (16X, 16Y), the peripheral circuit (38) are located at the 3D-MVExcept array (36)；One containing at least partly address/
The address/data converter chip (40*) of data converter, the address/data converter is in host and the three-dimensional array chip
(30) into row address and/or data conversion between；The three-dimensional array chip (30) is free of the partial address/data conversion
Device, the interconnection line number of plies of described address/data converter chip (40*) are more than the interconnection line number of plies of the peripheral circuit (38),
The three-dimensional array chip (30) is two different chips with described address/data converter chip (40*).
The present invention also proposes a kind of longitudinal memory of the three-dimensional of separation（3D-MV）(50), it is characterised in that including：One contains
An at least 3D-MVThe three-dimensional array chip (30) of array (36) and a peripheral circuit (38), the 3D-MVArray (36) is containing multiple
Vertical storage string (16X, 16Y), the peripheral circuit (38) are located at the 3D-MVExcept array (36)；One containing at least partly address/
The address/data converter chip (40*) of data converter, the address/data converter is in host and the three-dimensional array chip
(30) into row address and/or data conversion between；The three-dimensional array chip (30) is free of the partial address/data conversion
Device, the peripheral circuit (38) and described address/data converter chip (40*) contain different interconnection materials, described three
It is two different chips that array chip (30), which is tieed up, with described address/data converter chip (40*).
Description of the drawings
Figure 1A is a kind of 3D-M（The prior art）Sectional view；Figure 1B is a kind of integrated 3D- chips（The prior art）Be
System framework.
Group 2 is a kind of integrated 3D-MVChip（The prior art）Sectional view.
Fig. 3 A- Fig. 3 C indicate three kinds of separation 3D-MV。
Fig. 4 A are a kind of separation 3D-MVThe sectional view of middle three-dimensional array chip；Fig. 4 B are separation 3D-MVMiddle address/data
The sectional view of converter chip.
Fig. 5 A- Fig. 5 B indicate the first peripheral circuit component chip chamber the method for salary distribution.
The method of salary distribution of Fig. 6 A- Fig. 6 B second of peripheral circuit component of expression in chip chamber.
Fig. 7 A- Fig. 7 C indicate the third peripheral circuit component chip chamber the method for salary distribution.
Fig. 8 A- Fig. 8 B indicate the 4th kind of peripheral circuit component chip chamber the method for salary distribution.
Fig. 9 A- Fig. 9 B indicate two kinds of address/data converter chips for supporting multiple three-dimensional array chips.
Figure 10 A- Figure 10 C are the sectional views of three kinds of separation 3D-M encapsulation or component.
Figure 11 A- Figure 11 C are the circuit block diagrams of three kinds of voltage generators.
Figure 12 A are a kind of circuit block diagrams of address translator；Figure 12 B are a kind of circuit block diagrams of data converter.
It is noted that these attached drawings are only synoptic diagrams, their nots to scale (NTS) are drawn.For the sake of obvious and is convenient, in figure
Portion size and structure may zoom in or out.In different embodiments, identical symbol typicallys represent corresponding or similar
Structure.
Specific implementation mode
In the present invention, "/" indicate " and " or "or" relationship.For example, read/write voltage indicate read voltage or write voltage,
Or read voltage and write voltage；Address/data indicates address or data or address and voltage.
Fig. 3 A- Fig. 3 C indicate the longitudinal memory of the three-dimensional of three kinds of separation（3D-MV）50.It can be with various hosts including one
Realize physical connection and according to the interface of a kind of communication standard communication 54.Interface 54 includes multiple contact jaw 52a, 52b, 54a-
54d, they can contact jaw coupling corresponding with host socket.Wherein, power end 52a is coupled with the electrical power contacts end of host, main
Machine is referred to as supply voltage V by the power end 52a power supplys providedDD；Ground terminal 52b is separation 3D-MV50 provide ground voltage
VSS；Signal end 54a-54d is host and separation 3D-MV50 provide signal exchange, these signals include address/data.Due to
These address/datas are directly used by host, they are logical address/data.
Detach 3D-MV50 contain an at least three-dimensional array chip 30（Three-dimensional circuit）With an address/data converter chip
40*（Two-dimensional circuit）.In these embodiments, at least one address/data converter is located at address/data converter chip
In 40*, rather than in three-dimensional array chip 30.Since address/data converter is to realize 3D-MVThe required component of function,
Three-dimensional array chip 30 without address/data converter is not a storage chip that can be worked independently.
Separation 3D-M in Fig. 3 AV50 be a storage card, it contains an individual three-dimensional array chip（Three-dimensional circuit）30
With an individual address/data converter chip（Two-dimensional circuit）40*.Address/data converter chip 40* contain an address/
Data converter, including address translator and data converter.Wherein, address translator its by external bus 54（Including coming from
Signal on contact jaw 52a-52d）On logical address mutually converted with the physical address on internal bus 58；Data conversion
Device mutually converts the logical data on external bus 54 with the physical data on internal bus 58.Here, address/data is converted
Device can only realize address conversion or only realize data conversion or realize address and data conversion simultaneously.
Separation 3D-M in Fig. 3 BV50 be also a storage card.It is containing there are two peripheral circuit chips：Voltage generator
Chip 40 and address/data converter chip 40*.Voltage generator chip 40 contains a voltage generator；Address/data is converted
Device chip 40* contains an address/data converter.Voltage generator obtains supply voltage V from hostDD, convert thereof into reading/
Voltage is write, and read/write voltage is provided to three-dimensional array chip 30 by power bus 56.Here, read/write voltage can be merely
Read voltage VROr it is only to write voltage VWOr including read voltage VRWith write voltage VW, it is with supply voltage VDDWith different numerical value.
In the present embodiment, read/write voltage includes a read voltage VRVoltage V is write with twoW1、VW2.In other embodiments, read/write
Voltage may include that more than one read voltage or two write voltage.
Separation 3D-M in Fig. 3 CV50 be a large-capacity memory card or a solid state disk.It contains multiple cubical array cores
Piece 30a, 30b ... 30w.These three-dimensional array chips form two channels：A and B.In the A of channel, internal bus 58A is three-dimensional battle array
Row chip 30a, 30b ... 30i provides physical address/data, in the B of channel, internal bus 58B be three-dimensional array chip 30r,
30s ... 30w provide physical address/data.Meanwhile power bus 56 provides read/write for dimension array chip 30a, 30b ... 30w
Voltage.Although only there are two channels for the present embodiment, for the personage for being familiar with this profession, large-capacity memory card and solid state disk
More multichannel can be contained.
Fig. 4 A are separation 3D-MVThe sectional view of three-dimensional array chip 30 in 50.It contains an at least 3D-MVArray 36 and one
Peripheral circuit 38.3D-MVArray 36 is formed in three dimensions, and contains multiple vertical storage strings 16X, 16Y.Each deposit vertically
Storage string（Such as 16X）Storage member containing multiple vertical stackings（Such as 8a-8h）.These storage members are mutual by a vertical address wire
Coupling.Each storage member（Such as 8f）Containing there are one vertical transistor, which contains grid 6, storage film 7 and longitudinal ditch
Road 9.One 3D-MVExample be longitudinal NAND（vertical NAND）.For 3D-MVFor array 36, BEOL layer number etc.
Storage member number in vertical storage string, the storage member number that can also be more than in vertical storage string.3D-M in Fig. 4 AVBattle array
Row 36 contain 8 BEOL layers, the 3D-M of practical volume productionVArray 36 contains 24 or more BEOL layers.
Peripheral circuit 18 is located at 3D-MVExcept array 36.It contains substrate transistor 0t and substrate interconnection line 0i.Substrate is brilliant
Body pipe 0t is formed in semiconductor substrate 0, it is traditional planar ransistor.Substrate interconnection line 0i is substrate transistor 0t real
Now it is connected with each other.In this example, peripheral circuit 18 contains 2 BEOL layers, i.e. substrate interconnection line layer 0M1,0M2.Another party
Face, although the sectional view of peripheral circuit 38 is similar with peripheral circuit in Figure 1B 18 in Fig. 4 A, in Fig. 4 A contained by peripheral circuit 38
Peripheral circuit 18 is few in peripheral circuit component ratio Figure 1B.Particularly, peripheral circuit 38 at least lacks a voltage generator.Periphery
The details of circuit 38 further discloses in Fig. 5 A- Figure 10 B.
Fig. 4 B are separation 3D-MVThe sectional view of address/data converter chip 40* in 50.Address/data converter core
Piece 40* is formed in two-dimensional space, and containing only there are one functional layers, i.e. substrate circuitry layer 0K '.Substrate circuitry layer 0K ' includes crystalline substance
Body pipe 0t ' and its interconnection line 0i '.Transistor 0t ' is formed on voltage generator substrate 0 ', and interconnection line 0i ' is transistor 0t '
It realizes and is connected with each other.The address/data converter chip 40 is containing there are four BEOL layers, i.e. interconnection line layer 0M1 ' -0M4 '.
The understanding for being familiar with this profession is both known about, and the production cost of integrated circuit is substantially directly proportional to its BEOL layer number.Due to
Address/data converter chip 40* contains less BEOL layer, and wafer cost is far below three-dimensional array chip 30.Because extremely
Small part detaches 3D-MV50（That is address/data converter chip 40）Production cost be far below integrated 3D-MVChip 20（Ground
Location/data converter is located in chip 20）, detach 3D-MV50 overall cost is less than integrated 3D-MV 20。
Further, since address/data converter chip 40* is an individual chips, it can be than integrated 3D-MVChip 20
Peripheral circuit 18 has more substrate interconnection line layers（Such as increase to four layers from two layers）, therefore address/data converter chip
The address/data converter design in 3D-M chips 20 is more simple, performance than integrating for address/data converter in 40*
Preferable and shared chip area is smaller.Although noticing that the interconnection line number of plies of address/data converter chip 40* is more than periphery
Circuit 18, BEOL layer number are still much smaller than three-dimensional array chip 30（4 vs. 8）.
In addition, since address/data converter chip 40* need not undergo high-temperature technology, interconnection line 0i ' may be used
High-performance interconnection wire material such as uses copper（Cu）As conductive material, high-g value as insulating materials.These materials can carry
The function of high address/data converter chip 40*, to improve separation 3D-MV50 overall performance.
For traditional two dimensional memory（2D-M, such as flash memory）Although can be by its peripheral circuit component from two-dimensional array
Chip is separated in a peripheral circuit chip, but do so can increase cost and reduce performance, this is because two-dimensional array chip
It is similar with the rear end structure of peripheral circuit chip, there is similar wafer cost and circuit performance；In addition extra lead cost
And delay, cost and the performance for detaching 2D-M are all poorer than integrated 2D-M.This and 3D-MVIt is entirely different.Three-dimensional array chip and week
The rear end structure difference of side circuit chip is very big（Such as there is different BEOL layer number, the different substrate interconnection line numbers of plies, different
Substrate interconnection wire material etc.）, detach 3D-MVCost and performance be better than integrated 3D-MV。
Detach 3D-MV50 and integrated 3D-MV20 the difference is that：At least one peripheral circuit component be located at address/
Data converter chip 40, rather than it is located at three-dimensional array chip 30.That is, 3D-MVPeripheral circuit component be assigned to
Between three-dimensional array chip 30 and address/data converter chip 40.Fig. 5 A- Fig. 9 B illustrate a variety of in chip（30、40）Between
Distribution method.
Fig. 5 A- Fig. 5 B indicate the first peripheral circuit component chip chamber the method for salary distribution.In fig. 5, storage array
Chip 30 contains multiple 3D-M arrays（Such as 22aa, 22ay）And its decoder.It also contains voltage generator 41, but does not contain
Address/data converter 49.In figure 5B, address/data converter chip 40 turns containing the address/data be free of in Fig. 5 A
Parallel operation 49.Due to not containing address/data converter 49, storage array chip 30 has higher array efficiency.
The method of salary distribution of Fig. 6 A- Fig. 6 B second of peripheral circuit component of expression in chip chamber.In fig. 6, storage array
Chip 30 contains multiple 3D-M arrays（Such as 22aa, 22ay）And its decoder, but do not contain voltage generator 41 and address/data
Converter 49.In fig. 6b, peripheral circuit chip 40 contains voltage generator 41 and address/data converter 49.Due to being free of
There are voltage generator 41 and address/data converter 49, storage array chip 30 that there is very high array efficiency.
Fig. 7 A- Fig. 7 C indicate the third peripheral circuit component chip chamber the method for salary distribution.In fig. 7, storage array
Chip 30 contains multiple 3D-M arrays（Such as 22aa, 22ay）And its decoder, but do not contain voltage generator 41 and address/data
Converter 49.Voltage generator 41 and address/data converter 49 are located in different peripheral circuit chips：Voltage generator 41
Positioned at voltage generator chip 40（Fig. 7 B）In；Address/data converter 49 is located at address/data converter chip 40*（Figure
7C）In.Voltage generator 41 is based on analog circuit, and address/data converter 49 is based on digital circuit.Since they are located at
Different peripheral circuit chip 40,40*, can be separately optimized them：It is right to 40 Optimized Simulated performance of voltage generator chip
The digital performance of address/data converter chip 40* optimizations.
Fig. 8 A- Fig. 8 B indicate the 4th kind of peripheral circuit component chip chamber the method for salary distribution.It is with Fig. 6 A- Fig. 6 B classes
Seemingly, only three-dimensional array chip 30 also contains the first parallel-to-serial conversion circuit 47（Fig. 8 A）, it will be parallel inside chip 30
Digital signal（Such as address/data/instruction）The serial digital signals being converted into outside chip 30.Address/data converter chip
40* also contains the second parallel-to-serial conversion circuit 47 '（Fig. 8 B）, it also by inside address/data converter chip 40* and
Line number code signal（Such as address/data/instruction）The serial digital signals being converted into outside chip 40*.Turned by parallel-to-serial
Change, the lead between three-dimensional array chip 30 and address/data converter chip 40*（Or soldered ball）Number can greatly be subtracted
It is few, therefore can reduce due to using separation 3D-MVAdditional feedthrough caused by encapsulation（Or soldered ball）Cost.
Fig. 9 A- Fig. 9 B indicate two kinds of address/data converter chip 40* for supporting multiple cubical arrays.Ground in Fig. 9 A
Location/data converter chip 40* contains multiple address/data converter 49a, 49b ... 49w.Each address/data converter
（Such as 49a）For corresponding three-dimensional array chip（Such as the 30a in Fig. 3 C）Address/data conversion is provided.Address/data in Fig. 9 B
Converter chip 40 also contains multiple voltage generator 41a, 41b ... 41w.Each voltage generator（Such as 41a）It is corresponding three
Tie up array chip（Such as the 30a in Fig. 3 C）Read/write voltage is provided.
Figure 10 A- Figure 10 C are three kinds of separation 3D-MVSectional view.Separation 3D-M in Figure 10 A- Figure 10 BVIt is that one kind is more
Chip package（MCP）.Separation 3D-M in Figure 10 CVIt is a kind of multi-chip module（MCM）.These MCP and MCM can be used for depositing
Card storage or solid state disk.
3D-M in Figure 10 AVEncapsulation 60 is containing there are two individual chips：One three-dimensional array chip 30 and an address/data
Converter chip 40*.Chip 30,40 is stacked on a package substrate（interposer）On 63 and in same encapsulating shell 61.
Lead（bond wire）65 provide electrical connection for chip 30,40*.In addition to lead, soldered ball can also be used（solder bump）
Deng.In order to guarantee data security, chip 30,40* are preferably enclosed in a moulding compound（molding compound）In 67.In this reality
It applies in example, three-dimensional array chip 30 is stacked on address/data converter chip 40*.In other embodiments, address/data
Converter chip 40* can be stacked in three-dimensional array chip 30 or three-dimensional array chip 30 and address/data converter chip
40* is stacked Face to face or three-dimensional array chip 30 and address/data converter chip 40* are placed side by side.
3D-M in Figure 10 BVMulti-chip package 60 contains at least two three-dimensional array chip 30a, 30b and an address/number
According to converter chip 40*.These chips 30a, 30b and 40* are three individual chips.They are located in same encapsulating shell 61.
Wherein, three-dimensional array chip 30a is stacked on three-dimensional array chip 30b, and three-dimensional array chip 30b is stacked on address/data
On converter chip 40*.Lead 65 provides electrical connection for chip 30a, 30b and 40*.
Separation 3D-M in Figure 10 CVComponent 60 contains a component framework 76.The frame 76 contains to be encapsulated there are two individual：
Cubical array encapsulation 72 and peripheral circuit encapsulation 74.Wherein, cubical array encapsulation 72 containing there are two three-dimensional array chip 30a,
30b, and peripheral circuit encapsulation 74 contains address/data converter chip 40*.Frame 76 is also cubical array encapsulation 72 and periphery
Circuit package 74 provides electrical connection（It is not shown here）.
Figure 11 A- Figure 11 C are the circuit block diagrams of three kinds of voltage generators.DC-DC change is preferred in voltage generator
Parallel operation（DC-DC converter）.DC-DC converter includes booster and reducing transformer.The output voltage of booster is than defeated
Enter voltage height, the input voltage of reducing transformer is lower than input voltage.The example of booster includes charge pump（Charge pump, figure
11A）And Boost（Boost converter, Figure 11 B）Deng.The example of reducing transformer includes low dropout voltage regulator（low
Dropout, Figure 11 C）With Buck converters（Buck converter）Deng.
Voltage generator in Figure 11 A includes a charge pump 71, output voltage VoutMore than input voltage Vin.Generally
Come, charge pump 71 also contains one or more capacitances.Voltage generator in Figure 11 B includes a high frequency Boost 73,
Output voltage VoutMore than input voltage Vin.Boost 73 also contains inductance.The inductance is preferably a thin inductance, to meet
The requirement of storage card or solid state disk to thickness.Voltage generator in Figure 11 C includes a low dropout voltage regulator 75, output electricity
Press VoutLess than input voltage Vin.It is, in general, that low dropout voltage regulator 75 also contains one or more capacitances.
Figure 12 A- Figure 12 B indicate two components of address/data converter 49 respectively：Address translator 43 and data turn
Parallel operation 45.Figure 12 A indicate a kind of address translator 43.The logical address 54A of host is converted into 3D-M nucleus 22 by it
Physical address 58A.Address translator 43 is containing there are one processor 92 and a memories 94.Memory 94 stores an address mapping table
82, a trouble block table 84 and a wear management table 86.These state tables 82,84,86 are stored in read-only memory when flat（ROM）
In.It is loaded into random access memory when in use（RAM）In.Here, read-only memory can a kind of non-volatile memories
Device（NVM）, such as flash memory.More three-dimensional array chips are supported for one（Such as 30a, 30b ... 30w in Fig. 3 C）Ground
For location/data converter chip 40*, memory 94 be all three-dimensional array chip 30a, 30b ... 30w storage states tables 82,
84,86, it is shared by all three-dimensional array chip 30a, 30b ... 30w.
In the various state tables 82,84,86 of memory 94, address mapping table 82 store logical address and physical address it
Between mapping；Trouble block table 84 stores the address of faulty memory block in three-dimensional memory array；Wear management table 86 is noted down often
The number of a memory block read/write.Here, " memory block " refers to the allocation unit of memory, and size can be from a storage member
To all storages member in a three-dimensional memory array.
In read procedure, once processor 92 receives the logical address 54A for the memory block for needing to read, it is reflected from address
Corresponding physical address 58A is obtained in firing table 82.During writing, once processor 92 receive need the memory block that is written it
Logical address 54A, it selected from address mapping table 82, trouble block table 84 and wear management table 86 a vacant, fault-free with
And data are written in the less memory block used.The address of the selected memory block is physical address.
Figure 12 B indicate a kind of data converter 45.The logical data 54D of host is converted into the object of three-dimensional memory array by it
Data 58D is managed, or the physical data 58D of three-dimensional memory array is converted into the logical data 54D of host.Data converter 45
It is corrected containing an error checking（ECC）Encoder 96 and an ECC decoder 98.ECC encoder 96 is by the logical data 54D of input
It is converted into storing the physical data 58D of three-dimensional memory array.The object that ECC decoder 98 will be read from three-dimensional memory array
Reason data 58D is converted into logical data 54D to be output.In this process, the error bit in physical data 58D be examined and
Correction.It includes Reed-Solomon codes, Golay codes, BCH code, multidimensional parity code and Hamming code to be suitble to the ECC encryption algorithms of 3D-M
Deng.
It should be appreciated that under the premise of not far from the spirit and scope of the present invention, it can be to the form and details of the present invention
It is modified, this does not interfere the spirit of their application present invention.Therefore, in addition to the spirit according to appended claims,
The present invention does not answer any way limited.
Claims (7)
1. a kind of longitudinal memory of the three-dimensional of separation（3D-MV）(50), it is characterised in that including：
One three-dimensional array chip (30) containing at least one three-dimensional longitudinal storage array (36), three-dimensional longitudinal direction storage array (36)
Containing multiple vertical storage strings (16X, 16Y), the storage that each vertical storage string contains multiple vertical stackings is first (8a-8h)；
The one address/data converter chip (40*) containing at least partly address/data converter, the address/data converter
Into row address and/or data conversion between host and the three-dimensional array chip (30)；
The three-dimensional array chip (30) is free of the partial address/data converter, is erected in the three-dimensional array chip (30)
First (8a-8h) number of storage contained by straight storage string (16X) is more than the interconnection line of described address/data converter chip (40*)
The number of plies, the three-dimensional array chip (30) and described address/data converter chip (40*) are two different chips.
2. a kind of longitudinal memory of the three-dimensional of separation（3D-MV）(50), it is characterised in that including：
One three-dimensional array chip (30) containing at least one three-dimensional longitudinal storage array (36) and a peripheral circuit (38), the three-dimensional
Longitudinal storage array (36) contains multiple vertical storage strings (16X, 16Y), which is located at the three-dimensional and longitudinally stores
Except array (36)；
The one address/data converter chip (40*) containing at least partly address/data converter, the address/data converter
Into row address and/or data conversion between host and the three-dimensional array chip (30)；
The three-dimensional array chip (30) is free of the partial address/data converter, described address/data converter chip
The interconnection line number of plies of (40*) is more than the interconnection line number of plies of the peripheral circuit (38), the three-dimensional array chip (30) and described
Address/data converter chip (40*) is two different chips.
3. memory according to claim 1 or 2, it is further characterized in that：Three-dimensional longitudinal memory is one longitudinal
NAND。
4. memory according to claim 1 or 2, it is further characterized in that：Three-dimensional longitudinal memory is three-dimensional read-only
Memory（3D-ROM）Or three-dimensional random reads memory（3D-RAM）.
5. memory according to claim 1 or 2, it is further characterized in that：The three-dimensional longitudinal memory of the separation is storage
At least one of card, solid state disk, multi-chip package and multi-chip module.
6. memory according to claim 1 or 2, it is further characterized in that：Containing another three-dimensional array chip, the address/
Data converter chip (40*) contains the address/data converter of another three-dimensional array chip.
7. memory according to claim 1 or 2, it is further characterized in that：The address/data converter contains address conversion
Device (43) and/or data converter (45).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510228946.8A CN106206587B (en) | 2015-05-06 | 2015-05-06 | The longitudinal memory of three-dimensional of address/data converter separation |
| CN201810904548.7A CN109119413A (en) | 2015-05-06 | 2015-05-06 | The longitudinal memory of the three-dimensional of address/data converter separation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510228946.8A CN106206587B (en) | 2015-05-06 | 2015-05-06 | The longitudinal memory of three-dimensional of address/data converter separation |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810904548.7A Division CN109119413A (en) | 2015-05-06 | 2015-05-06 | The longitudinal memory of the three-dimensional of address/data converter separation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106206587A CN106206587A (en) | 2016-12-07 |
| CN106206587B true CN106206587B (en) | 2018-10-19 |
Family
ID=57459784
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510228946.8A Active CN106206587B (en) | 2015-05-06 | 2015-05-06 | The longitudinal memory of three-dimensional of address/data converter separation |
| CN201810904548.7A Pending CN109119413A (en) | 2015-05-06 | 2015-05-06 | The longitudinal memory of the three-dimensional of address/data converter separation |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810904548.7A Pending CN109119413A (en) | 2015-05-06 | 2015-05-06 | The longitudinal memory of the three-dimensional of address/data converter separation |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN106206587B (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100508196C (en) * | 2004-11-05 | 2009-07-01 | 张国飙 | Chip for three-dimensional memory system |
| CN101236780B (en) * | 2008-02-26 | 2012-07-04 | 中国科学院上海微系统与信息技术研究所 | Circuit design standard and implementation method for 3-D solid structure phase change memory chip |
| US8921991B2 (en) * | 2011-09-01 | 2014-12-30 | Chengdu Haicun Ip Technology Llc | Discrete three-dimensional memory |
| DE102012109612A1 (en) * | 2011-10-13 | 2013-04-18 | Samsung Electronics Co., Ltd. | Method for programming non-volatile memory e.g. programmable ROM, involves changing threshold voltage of first memory cell transistor via first peripheral |
| CN103632699B (en) * | 2012-08-22 | 2016-09-28 | 成都海存艾匹科技有限公司 | Three-dimensional storage containing address/data converter chip |
-
2015
- 2015-05-06 CN CN201510228946.8A patent/CN106206587B/en active Active
- 2015-05-06 CN CN201810904548.7A patent/CN109119413A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206587A (en) | 2016-12-07 |
| CN109119413A (en) | 2019-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103632699B (en) | Three-dimensional storage containing address/data converter chip | |
| US8218346B2 (en) | Multi-chip packages including extra memory chips to define additional logical packages and related devices | |
| CN103765516B (en) | The three-dimensional storage be separated | |
| CN102210022B (en) | Solid state drive or other storage apparatus that includes a plurality of encapsulated semiconductor chips | |
| US20140036566A1 (en) | Discrete Three-Dimensional Memory Comprising Dice with Different BEOL Structures | |
| US9123393B2 (en) | Discrete three-dimensional vertical memory | |
| US9093153B2 (en) | Three-dimensional memory comprising discrete read/write-voltage generator die | |
| US9305604B2 (en) | Discrete three-dimensional vertical memory comprising off-die address/data-translator | |
| US11355485B2 (en) | Semiconductor die and semiconductor package | |
| US20160035394A1 (en) | Discrete Three-Dimensional Memory | |
| US9024425B2 (en) | Three-dimensional memory comprising an integrated intermediate-circuit die | |
| US9558842B2 (en) | Discrete three-dimensional one-time-programmable memory | |
| US20150332734A1 (en) | Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator | |
| US9299390B2 (en) | Discrete three-dimensional vertical memory comprising off-die voltage generator | |
| US9508395B2 (en) | Three-dimensional one-time-programmable memory comprising off-die read/write-voltage generator | |
| CN106206587B (en) | The longitudinal memory of three-dimensional of address/data converter separation | |
| CN106206589B (en) | The longitudinal memory of three-dimensional of voltage generator separation | |
| CN106205669A (en) | Three-dimensional longitudinal memorizer that address/data transducer separates | |
| CN106206590A (en) | Three-dimensional longitudinal memorizer that voltage generator separates | |
| CN107046036B (en) | Electrical programming memory of three-dimensional containing separation voltage generator | |
| WO2014134865A1 (en) | Three-dimensional memory comprising independent intermediate circuit chip | |
| CN105990352A (en) | Separated three-dimensional vertical memory | |
| CN105990351A (en) | Separated three-dimensional vertical memory | |
| CN107689377A (en) | Electrical programming memory of three-dimensional containing separation address/data converter | |
| US20160189791A1 (en) | Discrete Three-Dimensional One-Time-Programmable Memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |