DE102012109612A1 - Method for programming non-volatile memory e.g. programmable ROM, involves changing threshold voltage of first memory cell transistor via first peripheral - Google Patents

Abstract

The method involves determining tendency for change of threshold voltage of first memory cell transistor from program state. A first inspection voltage of several verification voltages is selected in responsive to the determination. A check is made whether the threshold voltage of first memory cell transistor is sufficiently changed using first verification voltage. The threshold voltage of the first memory cell transistor is changed via first peripheral. An independent claim is included for non-volatile memory device.

Description

Cross-reference to related applications

This application claims under 35 USC § 119 the priority of Korean Patent Application No. 10-2011-0104753 , filed October 13, 2011, the entirety of which is incorporated herein by reference.

Background of the invention

The inventive concept described here relates to a semiconductor memory device, and more particularly relates to a programming method of a nonvolatile memory device and a memory system including the nonvolatile memory device.

A semiconductor memory device can be manufactured by using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and the like. Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices.

Volatile memory devices may lose stored data when turned off or otherwise powered off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. Non-volatile memory devices can retain stored contents even when turned off or otherwise powered down. Non-volatile memory devices include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), Resistor RAM (RRAM), ferroelectric RAM (FRAM) and the like. The flash memory device includes NOR type flash memory and NAND type flash memory.

Recently, a semiconductor memory device having a three-dimensional memory array structure has been developed.

Summary of the invention

Exemplary embodiments provide a non-volatile memory device programming method, comprising receiving program data to be programmed into memory cells; reading the memory cells to judge an erasure state and at least one program state; performing a state read operation in which the at least one program state is read using a plurality of state read voltages; and programming the program data in the memory cells using a plurality of check voltages having different levels in accordance with a result of the state read operation.

In exemplary embodiments, programming the program data in the memory cells includes programming memory cells that are programmed into a program state using at least two verify voltages that have different levels consistent with the result of the state read operation.

In exemplary embodiments, in the state read operation, the at least one program state is read using a first state read voltage and a second state read voltage higher than the first state read voltage.

In exemplary embodiments, the first state read voltage has the same level as a verify voltage that is used when programming the at least one program state.

In exemplary embodiments, among the memory cells programmed in the same program state, first memory cells read out in the state read operation as memory cells each having a threshold voltage higher than the second state read voltage are programmed using a first verify voltage, second memory cells. which are read out as memory cells each having a threshold voltage higher than the first state read voltage and lower than the second state read voltage are programmed using a second verify voltage higher than the first verify voltage and third memory cells read out as memory cells , which each have a threshold voltage lower than the first state read voltage, are programmed using a third verify voltage higher than the second verify voltage ngsspannung is.

In exemplary embodiments, when the memory cells are programmed with the program data, a first verify voltage, a second verify voltage, and a third verify voltage are sequentially applied to a wordline associated with the Memory cells is connected, applied after a programming voltage is applied to the word line.

In exemplary embodiments, the programming method further comprises programming the result of the state read operation into memory cells of a supplemental memory area.

In exemplary embodiments, the programming method further comprises receiving second program data to be programmed in the memory cells; reading out the result of the state read operation programmed in the memory cells of the supplemental memory area; and programming the memory cells with the second program data using a plurality of check voltages different in level in accordance with the result of the state read operation read out from the memory cells of the supplemental memory area.

In exemplary embodiments, the programming method further comprises outputting the result of the state read operation to the outside.

Exemplary embodiments also provide a programming method of a nonvolatile memory device, comprising receiving program data to be programmed in the memory cells; reading the memory cells to judge an erasure state and at least one program state; performing a state read operation in which, using a plurality of first state read voltages, the at least one program state is read out and the erase state is read using a plurality of second state read voltages; and programming the memory cells with the program data using a plurality of verify voltages having different levels in accordance with a result of the state read operation.

Exemplary embodiments also provide a programming method of a nonvolatile memory device, comprising receiving program data to be programmed in the memory cells; judging whether the program data corresponds to an MSB programming operation; and when the program data corresponds to an MSB programming operation, reading out the memory cells for judging an erasure state and at least one program state, performing a state read operation in which at least one program state is read using a plurality of read voltages, and programming the memory cells with the program data using a plurality of monitor voltages having different levels in accordance with a result of the state read operation, wherein in the state read operation, each program state is read using at least two state read voltages having different levels.

Exemplary embodiments also provide a programming method of a nonvolatile memory device comprising a plurality of cell strings provided on a substrate, each cell row comprising a plurality of cell transistors stacked in a direction perpendicular to the substrate, and wherein each cell transistor has an information storage film that is an isolator, the programming method comprising receiving program data to be programmed in the memory cells; reading the memory cells to judge an erasure state and at least one program state; performing a state read operation in which the at least one program state is read using a plurality of state read voltages; and programming the program data in the memory cells using a plurality of check voltages having different levels in accordance with a result of the state read operation.

Exemplary embodiments also provide a programming method of a nonvolatile memory device comprising a plurality of cell strings provided on a substrate, each cell row comprising a plurality of cell transistors stacked in a direction perpendicular to the substrate, and wherein each cell transistor comprises an information storage film that is an isolator, the programming method comprising receiving program data to be stored in the memory cells; reading data from second memory cells connected to at least one wordline immediately adjacent to a wordline connected to the first memory cells; and programming the first memory cells with the program data using a plurality of verify voltages having different levels in accordance with the readout data from the second memory cells, wherein memory cells programmed into a program state are programmed using verify voltages that coincide with the read-out data have different levels.

In exemplary embodiments, the programming method further comprises receiving second program data to be programmed in the memory cells connected to at least one other wordline immediately adjacent to a wordline connected to the memory cells, wherein memory cells include programmed into the program state may be programmed using the verify voltages having different levels in accordance with the read-out data and the second program data.

Exemplary embodiments also provide a nonvolatile memory device comprising a memory cell array including a plurality of memory cells connected to bitlines and wordlines; an address decode unit configured to apply read voltages to a selected wordline, apply state read voltages, and apply a program voltage and verify voltages in a program operation; and a page buffer unit comprising a plurality of page buffers, each page buffer including a data latch and a rearrangement latch, the data flip-flop being program data stores which are to be programmed and stores a readout result when the read voltages are applied to the selected word line, and the reordering flip-flop stores a state read result when the state read voltages are applied; and wherein each page buffer, in accordance with data stored in the data flip-flop and data stored in the reordering flip-flop, takes a bit line when the programming voltage and the verify voltages are applied.

In exemplary embodiments, at least two state read voltages of the state read voltages have levels lying between the levels of two read voltages immediately adjacent to the read voltages.

In exemplary embodiments, each page buffer occupies the bit line with a power supply voltage or a ground voltage in accordance with data stored in the data flip-flop before the program voltage is applied.

In exemplary embodiments, when the verify voltages are applied, each page buffer is configured to select a valid verify voltage in accordance with data stored in the reorder flip-flop.

In exemplary embodiments, the memory cell array is divided into a user data area and a supplemental domain, wherein the state read result stored in the reordering flip-flop is programmed into the supplemental area.

In exemplary embodiments, when second program data corresponds to the same address, the address decode unit applies second read voltages to the selected word line of the user data area, third read voltages to a selected word line of the supplemental area, and a second program voltage and second verify voltages to the selected word line of the user data area the program data is programmed; wherein the data flip-flop stores the second program data and stores a second read-out result when the second read voltages are applied; the reordering flip-flop stores a third readout result when the third read voltages are applied; and when the second programming voltage and the second verify voltages are applied, each page buffer occupying the bit line in accordance with data stored in the data flip-flop and data stored in the reordering flip-flop.

Exemplary embodiments also provide a nonvolatile memory device comprising a memory cell array having a Comprises a plurality of memory cells connected to bitlines and wordlines; an address decode unit configured to apply read voltages, state read voltages, and a program voltage and verify voltages in a program operation of MSB data to a selected word line; and a page buffer unit comprising a plurality of page buffers, each page buffer comprising a data flip-flop and a reordering flip-flop connected to a bit line; wherein the data flip-flop stores data to be programmed and stores a readout result when the read voltages are applied to a selected wordline, and the reordering flip-flop stores a state read result when the state read voltages are applied; and in a programming operation of the MSB data, each page buffer occupies the bit line in accordance with data stored in the data flip-flop and the reordering flip-flop when the programming voltage and the verify voltages are applied.

Exemplary embodiments also provide a nonvolatile memory device comprising a memory cell array including a plurality of memory cells connected to bitlines and wordlines; an address decode unit configured to apply first read voltages to a selected word line, to apply second read voltages to at least one word line immediately adjacent to the selected word line, and to apply a program voltage and verify voltages to the selected word line during a program operation; and a page buffer unit comprising a plurality of page buffers, each page buffer including a data flip-flop and a reorder flip-flop, the data flip-flop storing program data to be programmed and storing a first read result when the first read voltages the selected word line are applied, and the reordering flip-flop stores a second read-out result when the second read voltages are applied to the at least one word line; and wherein each page buffer occupies a bit line coincident with data stored in the data flip-flop and data stored in the reordering flip-flop when the programming voltage and the verify voltages are applied.

Exemplary embodiments also provide a memory system comprising a non-volatile memory device; and a controller configured to control the nonvolatile memory device, wherein the nonvolatile memory device comprises a memory cell array including a plurality of memory cells connected to bit lines and word lines; an address decode unit configured to apply read voltages to a selected wordline, to apply state read voltages, and to apply a program voltage and verify voltages during a program operation; and a page buffer unit comprising a plurality of page buffers, each page buffer including a data flip-flop and a reorder flip-flop, the data flip-flop storing program data to be programmed and storing a read result when the read voltages are at the selected one Word line are applied, and the reordering flip-flop stores a state read result when the state read voltages are applied; and wherein each page buffer occupies a bit line coincident with data stored in the data flip-flop and data stored in the reordering flip-flop when the programming voltage and the verify voltages are applied.

In exemplary embodiments, the controller stores the state read result output from the nonvolatile memory device to control a program, read, or erase operation of the nonvolatile memory device in accordance with the stored state read result.

In exemplary embodiments, the nonvolatile memory device and the controller form a memory card.

In exemplary embodiments, the nonvolatile memory device and the controller form a solid state drive (SSD).

Exemplary embodiments also provide programming methods of a nonvolatile memory device, comprising reading out data stored in memory cells of a buffer area to judge an erase state and at least one program state of memory cells of the user data area corresponding to the memory cells of the buffer area; judging whether a fine programming operation has been performed on memory cells of the user data area; and, if it is judged that the fine programming operation has been performed, performing a state read operation on the at least one program state of the memory cells of the user data area using a plurality of state read voltages to perform the fine program operation using a plurality of verify voltages coincident with one In the state read operation, each program state is read out using a plurality of state read voltages having different levels.

Exemplary embodiments also provide programming methods of a nonvolatile memory device, comprising receiving program data to be programmed in the memory cells; reading the memory cells to judge an erasure state and at least one program state; reading memory cells of a test data area corresponding to the memory cells; and programming the memory cells with the program data using a plurality of verify voltages having different levels in accordance with a read result of the memory cells of the test data area, wherein programming the memory cells with the program data includes programming memory cells that use verify voltages that match have different voltages with a readout result of memory cells of the test data area, are programmed into a program state.

Exemplary embodiments also provide programming methods of a nonvolatile memory device, comprising receiving program data to be programmed into memory cells; approximating a first program loop in which a program voltage and a check voltage are respectively applied once to the memory cells until a threshold condition is satisfied, and if the threshold condition is satisfied, performing a state read operation on memory cells having a middle state higher than an erasure state using at least two state read voltages having different levels; and performing a second program loop in which a program voltage and at least two check voltages having different levels are applied to the memory cells using a plurality of check voltages having different levels in accordance with a result of the state read operation.

In exemplary embodiments, the threshold condition includes a condition indicating that memory cells that have first undergone a program of the memory cells are detected.

In exemplary embodiments, the threshold condition includes a condition indicating that the number of memory cells that have first passed through the memory cells from the program is above a certain value.

In exemplary embodiments, the threshold condition includes a condition indicating that an approximate number of the first program loop is above a particular value.

Exemplary embodiments also provide a method of programming a nonvolatile memory device, comprising: determining a tendency of a threshold voltage of a first memory cell transistor to change from a programmed state, and selecting a first verify voltage from a plurality of verify voltages in response to the determination and programming the first memory cell transistor to change the threshold voltage of the first memory cell transistor, the programming comprising checking that the threshold voltage of the first memory cell transistor has been sufficiently changed using the first verify voltage.

Exemplary embodiments also include a method of programming a series of memory cells, comprising selecting a first row of memory cells from a plurality of rows, selecting a first subset of the memory cells of the first row to within a first program state extent, a detectable property of the first subset of Memory cells, wherein the first program state extent represents a value of at least a first bit of the data, programming the first subset of the memory cells to change the property of each of the first subset of the memory cells, verifying the change of the characteristic of some the first subset of the memory cells having a first check level, and checking others of the first subset of the memory cells with a second check level different from the first check level.

Exemplary embodiments also include a method of programming a memory cell device, comprising programming a first plurality of memory cells into a first program state of a plurality of program states, each program state representing a unique set of values of a plurality of data bits, wherein the first plurality of memory cells includes a first wordline, the programming comprising a plurality of program loops, each of which program loops comprises: (a) applying a programming voltage to the wordline; (b) applying a first verify voltage to the wordline to verify that a first subset of the first plurality of memory cells has at least a first threshold voltage; and (c) applying a second verify voltage different from the first verify voltage to the wordline to verify that a second subset of the first plurality of memory cells has at least a second threshold voltage.

Exemplary embodiments also include a method of programming a non-volatile multi-bit memory cell, comprising programming a first bit of the data into the memory cell so that the memory cell exhibits a first property within a first perimeter, the property shown being the first bit of the data represents; reading the first bit of the date from the memory cell; determining a change in the characteristic exhibited by the memory cell; and programming the memory cell to store the first bit of the data and a second bit of the data such that the memory cell displays a property within a second perimeter, wherein the second perimeter is selected based on the determined change.

Exemplary embodiments also include a method of programming a nonvolatile memory cell, comprising: changing a threshold voltage of a memory cell transistor within a first extent; determining a change in the threshold voltage of the memory cell with respect to the first circumference; changing the threshold voltage of the memory cell transistor to a second perimeter, wherein the second perimeter is selected in response to the determining step.

Exemplary embodiments also include a nonvolatile memory device comprising an array of memory cells sequentially arranged in columns, rows of memory cells connected to respective wordlines, and columns of memory cells connected to corresponding bitlines; a page buffer including data flip-flops and second flip-flops connected to respective bit lines, wherein data flip-flops are configured to store data; a voltage generator configured to generate a programming voltage; a row decoder configured to decode an address and select a word line; a control unit configured to control a programming operation comprising executing a plurality of program loops, each program loop having application of a program pulse to a word line selected by the row decoder, and a plurality of sequential check operations check respective program levels of a first row of memory cells connected to the selected word line, wherein the data buffers of the page buffer are adapted to perform a programming operation on respective first row memory cells connected to bit lines connecting the data Flip-flops correspond to block or allow, and wherein the second flip-flops are configured to select one of a plurality of check results each corresponding to the plurality of check operations of a program loop.

Exemplary embodiments also include a non-volatile memory device comprising an array of memory cells sequentially arranged in columns, rows of the memory cells connected to corresponding word lines, and columns of the memory cells connected to corresponding bit lines; a voltage generator configured to generate a programming voltage; a page buffer comprising data flip-flops and second flip-flops connected to respective bit lines, data flip-flops adapted to temporarily store data to be stored in a row of the memory cells to be programmed; a row decoder configured to decode an address and select a word line; a controller configured to control a programming operation comprising executing a plurality of program loops, each program loop having application of a program pulse to a wordline selected by the row decoder and a plurality of sequential check operations check respective voltage threshold levels of a first row of the memory cells connected to the selected wordline; wherein the page buffer data flip-flops are configured to inhibit a programming operation on respective first-row memory cells connected to bit lines corresponding to the data flip-flops; wherein the control unit is adapted to control a coarse programming operation to program the first row of the memory cells into a plurality of coarse program states, each of the plurality of coarse program states corresponding to a fine program state, the control unit being configured to have one Conditional reading of the first row of memory cells during a coarse program state to determine a tendency to vary a threshold voltage of each memory cell, and wherein the second flip flops are configured to store information of the result of the state read and are configured to respond in response to the Selecting information stored in the second flip-flops from among a plurality of check results corresponding to each of the plurality of check operations of a program loop.

Exemplary embodiments also contemplate devices in which both the disclosed methods described herein and methods of operation are implemented with the devices described herein.

Brief description of the drawings

The above and other objects and features will be better understood from the following description with reference to the accompanying drawings, wherein like reference numerals refer to like parts throughout the several figures, unless otherwise specified, and where:

1 FIG. 10 is a block diagram schematically illustrating a nonvolatile memory device according to an embodiment. FIG.

2 is a diagram showing a memory cell array in 1 according to one embodiment.

3 is a plan view of a portion of a memory block in FIG 1 according to one embodiment.

4 is a perspective view taken along a line IV-IV 'in 3 according to one embodiment.

5 is a cross-sectional view taken along a line IV-IV 'in 3 according to one embodiment.

6 is an enlarged diagram illustrating one of the cell transistors in FIG 5 represents.

7 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to one embodiment.

8A to 8D represent exemplary charge-reordering phenomena.

9 FIG. 10 is a flowchart for describing a programming method according to an embodiment. FIG.

10 FIG. 13 is a diagram illustrating threshold voltage distributions of a memory cell when programming LSB data in a memory cell. FIG.

11 FIG. 14 is a flow chart for fully describing a process S150 for performing a state read operation in FIG 9 ,

12 FIG. 15 is a diagram illustrating a procedure for performing a state read operation in FIG 11 represents.

13 FIG. 14 is a flowchart for fully describing a process S160 of programming memory cells with program data in FIG 9 ,

14 FIG. 15 is a diagram illustrating a threshold voltage distribution of the memory cells generated according to a programming method in FIG 13 are programmed.

15 FIG. 12 is a diagram illustrating a threshold voltage deviation due to charge rearrangement generated on memory cells generated according to a method of FIG 14 programmed procedures are programmed.

16 FIG. 10 is a timing diagram illustrating voltages that are determined according to an in. FIG 14 described programming method can be applied to selected word lines.

17 FIG. 11 is a timing diagram illustrating voltages generated according to the 13 and 14 described programming method can be applied to selected word lines.

18 FIG. 12 is a diagram illustrating an application of threshold voltage distributions of the memory cells generated according to a programming method in FIG 13 are programmed.

19 FIG. 12 is a diagram illustrating another application of threshold voltage distributions of the memory cells generated according to a programming method in FIG 13 are programmed.

20 FIG. 12 is a block diagram illustrating a nonvolatile memory device according to yet another embodiment.

21 FIG. 10 is a flowchart illustrating a programming method according to another embodiment. FIG.

22A FIG. 15 is a diagram illustrating a threshold voltage distribution of the memory cells according to a programming method in FIG 21 represents.

22B represents an alternative to the embodiment of 22A can be applied.

23 FIG. 12 is a block diagram illustrating a nonvolatile memory device according to yet another embodiment.

24 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment.

25 FIG. 12 is a block diagram illustrating a nonvolatile memory device according to yet another embodiment.

26 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment.

27 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment.

28 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment.

29 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment.

30A is a timing diagram illustrating voltages generated according to a programming method in FIG 29 be applied to a selected word line.

30B is a graph showing a deviation of the threshold voltage distribution of the memory cells according to a program in 29 as well as a kind of. Voltage application off 30A represents.

31 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment.

32 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment.

33 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment.

34 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment.

35 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment.

36 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment.

37 is a perspective view along a line IV-IV 'in 3 according to another embodiment.

38 is a cross-sectional view taken along a line IV-IV 'in 3 according to another embodiment.

39 is a perspective view along a line IV-IV 'in 3 according to yet another embodiment.

40 is a cross-sectional view taken along a line IV-IV 'in 3 according to yet another embodiment.

41 is a perspective view taken along a line IV-IV 'in 3 according to yet another embodiment.

42 is a cross-sectional view taken along a line IV-IV 'in 3 according to yet another embodiment.

43 is a plan view showing a memory block in FIG 2 according to another exemplary embodiment.

44 is a perspective view taken along a line XXXXIV-XXXXIV 'in 43 ,

45 is a cross-sectional view along a line XXXXIV-XXXXIV 'in 43 ,

46 is a plan view that forms part of a memory block in FIG 2 according to yet another embodiment.

47 is a perspective view along a line XXXXVII-XXXXVII 'in 46 ,

48 is a cross-sectional view along a line XXXXVII-XXXXVII 'in 46 ,

49 is a plan view that forms part of a memory block in FIG 2 according to yet another embodiment.

50 is a perspective view taken along a line XXXXX-XXXXX 'in 49 ,

51 is a plan view that forms part of a memory block in FIG 2 according to yet another embodiment.

52 is a perspective view along a line XXXXXII-XXXXXII 'in 51 ,

53 is a cross-sectional view along a line XXXXXII-XXXXXII 'in 51 ,

54 is a plan view that is part of a memory block in 2 according to yet another embodiment.

55 is a perspective view taken along a line XXXXXIV-XXXXXIV 'in 54 ,

56 is a cross-sectional view along a line XXXXXIV-XXXXXIV 'in 54 ,

57 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 54 according to one embodiment.

58 is a perspective view taken along a line XXXXXV-XXXXXV 'in 54 ,

59 is a cross-sectional view along a line XXXXXV-XXXXXV 'in 54 ,

60 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 54 represents according to another embodiment.

61 FIG. 10 is a block diagram illustrating a memory system according to an embodiment. FIG.

62 FIG. 10 is a flowchart for describing a programming method of a memory system according to an embodiment. FIG.

63 FIG. 10 is a flowchart for describing a state read method of a memory system according to an embodiment. FIG.

64 is a block diagram illustrating an application of a memory system in FIG 61 represents.

65 FIG. 10 is a diagram illustrating a memory card according to an embodiment. FIG.

66 FIG. 10 is a diagram illustrating a solid state drive according to an embodiment. FIG.

67 FIG. 10 is a block diagram illustrating a computer system according to an embodiment. FIG.

Detailed description

Hereinafter, various exemplary embodiments will be described in more detail with reference to the accompanying drawings, in which some example embodiments are shown. However, the present invention can be embodied in many different forms and should not be construed as limited to the exemplary embodiments preceding it. These exemplary embodiments are just examples - and many implementations and variations are possible that do not require the details provided herein. It should also be emphasized that the disclosure provides details of alternative examples, but an enumeration of alternatives is not exhaustive. Furthermore, true matches of details between different examples should not be interpreted to be necessary details - it would not be practical to enumerate every possible departure for each feature described herein. The language of the claims should be referenced in determining the requirements of the invention. In the drawings, the size and relative size of layers and regions may be exaggerated for the sake of clarity. Like reference numerals refer to like elements throughout.

It will be understood that although the terms first, second, third, etc. are used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections are not limited to these Expressions should be limited. These terms are used only to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or portion discussed below could also be referred to as a second element, component, region, layer or portion without departing from the teachings.

Spatially relative terms, such as "below," "below," "below," "above," "above, and the like," will be used herein to simplify the description to describe one element or the relationship of one feature to another ( Elements) or feature (features) to describe, as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, the elements described as "below" or "beneath" or "below" other elements or features would thereafter be aligned "above" the other elements or features. Thus, the exemplary terms "below" and "below" may include both an orientation above and below. The device may be reversed (rotated 90 ° or in other orientations) and the spatial references used herein should be construed accordingly. To this it is also understood that if a layer is referred to as lying "between" two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

The terms used herein are used for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the forms of the singular "on" and "the" are to be understood to embrace the plural as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprise,""comprise,""include,"" when used herein, specify the presence of the specified features, numbers, steps, acts, elements and / or components, but not the presence or addition of one or more other features, numbers, Exclude steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the enumerated items.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it is directly on the other element or layer, may be connected to, coupled to or adjacent to it, or intervening elements or layers may be present. Conversely, when an element is referred to as "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It is also to be understood that such terms, such as those defined in commonly used dictionaries, should be construed as having a meaning consistent with meaning in the context of the related art and / or present invention Description and not in an idealized or overly formal manner unless expressly so defined.

The term "selected memory block" may be used to indicate a memory block selected for a process such as programming, erasure, or readout among a plurality of memory blocks. The term "selected sub-block" may be used to indicate a sub-block that is selected for a process such as programming, erasure or triggering among a plurality of sub-blocks in a memory block. The term "selected bit line" or "selected bit line" may be used to indicate, among a plurality of bit lines, a bit line or bit lines connected to a cell transistor to be programmed or read out. The term "unselected bit line" or "unselected bit lines" may be used to indicate, among a plurality of bit lines, a bit line or bit lines connected to a cell transistor for being program inhibited or read locked.

The term "selected row select line" may be used to indicate, among a plurality of row select lines, a row select line connected to a row of cells comprising a cell transistor to be programmed or read. The term "unselected row select line" or "unselected row select lines" may be used to indicate, among a plurality of row select lines, a remaining row select line or remaining row select lines other than the selected row select line. The term "selected row select transistors" may be used to indicate row select transistors connected to a selected row select line. The term "non-selected row select transistors" may be used to indicate row select transistors connected to a non-selected row select line or unselected row select lines.

The term "selected ground select line" may be used to indicate, among a plurality of ground select lines, a ground select line connected to a row of cells including a cell transistor for being programmed or read. The term "unselected mass select line" may be used to indicate among a plurality of ground select lines a remaining ground select line or remaining ground select lines other than the selected ground select line. The term "selected ground select transistors" may be used to indicate selected ground select transistors connected to a selected ground select line. The term "non-selected ground selection transistors" may be used to indicate ground selection transistors connected to an unselected ground select line or unselected ground select lines.

The term "non-selected word line" may be used to indicate, among a plurality of word lines, a word line connected to a cell transistor to be programmed or read. The term "non-selected word line" or "unselected word lines" may be used to indicate a remaining word line or remaining word among a plurality of word lines Indicate wordlines that are other than a selected wordline.

The term "selected memory cell" or "selected memory cells" may be used to determine memory cells to be programmed or read from a plurality of memory cells. The term "non-selected memory cell" or "non-selected memory cells" may be used to indicate from a plurality of memory cells a remaining memory cell or remaining memory cells other than a selected memory cell or selected memory cells.

Embodiments will be described with reference to a NAND flash memory. However, the inventive concept is not limited thereto. The inventive concept can be applied to other nonvolatile and volatile memory types such as electrically erasable and programmable ROM (EEPROM), NOR flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM ( FRAM) and the like.

1 FIG. 10 is a block diagram schematically illustrating a nonvolatile memory type according to an embodiment. FIG. Regarding 1 can be a non-volatile storage device 100 a memory cell array 110 an address decoding unit 120 , a side buffer unit 130 , a data input output unit 140 , a voltage generating unit 150 and a control unit 160 include.

The memory cell array 100 may comprise a plurality of cell rows arranged on a substrate in the manner of a field, the field extending in the direction of a row and the direction of a column. Each cell row may include a plurality of memory cells stacked along a direction perpendicular to the substrate. That is, memory cells may be provided within arrays in rows and columns on a substrate, and may be stacked in a direction perpendicular to the substrate to form a three-dimensional memory cell array structure. The memory cell array 110 may comprise a plurality of memory cells, each comprising one or more bits of the data. Otherwise, structures such as two-dimensional memory cell arrays are also possible.

The address decoding unit 120 can with the memory cell array 110 via word lines WL, row selection lines SSL and ground selection lines GSL. The address decoding unit 120 may be configured to in response to the control of the control unit 160 to be operated. The address decoding unit 120 For example, an address may receive ADDR from an external device.

The address decoding unit 120 may be configured to decode a series of addresses of the input addresses ADDR. The address decoding unit 120 may be configured to select a word line corresponding to the decoded row address among the plurality of word lines WL. The address decoding unit 120 may be configured to select a row select line and a ground select line corresponding to the decoded row address among the row select lines SSL and the ground select lines GSL.

The address decoding unit 120 may in response to the decoded row address and the control of the control unit 160 supply voltages to the word lines WL from the voltage generation 150 be transmitted. The address decoding unit 120 Specifically, at the word lines WL, an upper verify voltage VFYU, a normal verify voltage VFYN, a lower verify voltage VFYL, a normal state read voltage VSRN, an upper state read voltage VSRU, a pass voltage VPASS, a program voltage VPGM, a check voltage VFY, a read voltage Vrd, and a non-selected one Supply reading voltage Vread.

The address decoding unit 120 may be configured to decode a column address among the input addresses ADDR. The address decoding unit 120 The decoded column address DCA can be sent to the page buffer unit 130 transfer.

The side buffer unit 130 can be connected to the memory cell array via the bit lines BL 110 be coupled. The side buffer unit 130 can in response to the control of the control unit 160 operate. The side buffer unit 130 may be the decoded column address DCA from the address decoding unit 120 receive. The side buffer unit 130 may select the bit lines BL in response to the decoded column address DCA.

The side buffer unit 130 may include a plurality of page buffers PB. Each page buffer PB may be coupled to a bit line BL. Each page buffer PB may comprise a data flip-flop DL and a reordering flip-flop RL.

Data to be programmed in memory cells and data programmed in memory cells may be stored in the data flip-flops DL. For example, data that previously programmed in memory cells, and data to be programmed in the memory cells are stored in the data flip-flops DL.

Information related to a charge reassembly of the memory cells may be stored in the reordering flip-flops RL. For example, a state read result of memory cells may be stored in the reordering flip-flop RL. This will be described later in more detail.

The address decoding unit 120 and the side buffer unit 130 can program and read operations according to the control of the control unit 160 carry out. Reading and programming can be done on the memory cell arrays 110 by controlling the row selection lines SSL of the word lines WL and the ground selection lines GSL via the address decoding unit 120 and control of the bit lines BL via the page buffer unit 130 be made. During programming, a verify read operation can be performed. The read memory unit 130 can to the control unit 160 output a result of the check read operation.

The side buffer unit 130 can receive data via the data lines DL. The entered data in the page buffer unit 130 can in the memory cell array 110 be enrolled. The side buffer unit 130 can read data from the memory cell array 110 read to output via the data lines DL. The side buffer unit 130 can store data from a first memory area of the memory cell array 110 be read out. The data in the page buffer unit 130 can be stored in a second memory area of the same. That is, a copyback operation can be performed.

The address decoding unit 120 and the side buffer unit 130 may coincide with the control of the control unit 160 perform a state read. This will be described later in more detail. The address decoding unit 120 and the side buffer unit 130 can be under the control of the control unit 160 perform a programming operation taking into account a reorganization. This will be described later in more detail.

The data input / output unit 140 can via the data lines DL with the page buffer unit 130 be connected. The data input / output unit 140 may be configured to exchange data with an external device. The data input / output unit 140 can take data from the page buffer unit 130 be transmitted via the data lines DL to the external device. The data input / output unit 140 For example, data input from the external device can be sent to the page buffer unit via the data lines DL 130 transfer.

The voltage generation unit 150 may have different voltages in accordance with the control of the control unit 160 produce. The voltage generation unit 150 For example, an upper verify voltage VFYU, a normal verify voltage VFYN, a lower verify voltage VFYL, a normal state read voltage VSRN, a top state read voltage VSRU, a pass voltage VPASS, a program voltage VPGM, a verify voltage VFY, a read voltage Vrd, a non-selected read voltage Vread may be generated. Each of these voltages can be at the address decoding unit 120 fed.

The upper verify voltage VFYU, the normal verify voltage VFYN, and the lower verify voltage VFYL may be verify voltages used to program the memory cells into a program state in consideration of charge reassembly.

The normal state read voltage VSRN and the upper state read voltage VSRU may be read voltages used in a state read operation for detecting the charge reassembly.

Each of the upper verify voltage VFYU, the normal verify voltage VFYN, the lower verify voltage VFYL, the normal state read voltage VSRN, and the upper state read voltage VSRU may be formed as a set of voltages. For example, the upper verify voltage VFYU may indicate a set of voltages at different levels, each corresponding to a least significant bit (LLSB), a middle weighted bit (CSB), and a highest order bit (MSB). These bits can also with different names, such as. For example, the second highest order bit (2SB). In general, the terminology with these "weighted bits" is used in this application to distinguish programming of different bits of information in a multi-level cell. Typically, in flash memory programming, a first bit to be programmed in a multi-level cell (from the erased state) is designated as a least significant bit and the last bit of information to be programmed in a multi-level cell is a bit highest value (MSB). If the multi-level cell has more than two bits, intermediate bits may be referred to as medium-valued (CSB), second-valued (2SB), and so on. For convenience of explanation, this application describes programming in the same way. However, it should be pointed out that the significance of the bits of the information relative to other bits does not depend on the order of storage in the multi-level cells. The significance of the bits relative to each other, if any, may be determined by their use by a user, by later data manipulation by the memory device (eg, by an input / output circuit of the memory device), or by an external device (eg, a memory controller ). Thus, data referred to as LSB data may in fact be subordinated to MSB data, and MSB data may actually be LSB data. Each of the normal verify voltage VFYN, the lower verify voltage VFYL, the normal state read voltage VSRN and the upper state read voltage VSRU may indicate a set of voltages at different levels. A particular voltage of a set of voltages may be indicated by a reference numeral following a reference symbol.

The pass voltage VPASS, the program voltage VPGM, the verify voltage VFY, the read voltage Vrd, and the non-selected read voltage Vread may be voltages used in programming and readout.

The control unit 160 may be configured to an overall operation of the nonvolatile memory device 100 to control. The control unit 160 may be operated in response to control signals CTRL and a command CMD provided by the external device. The control unit 160 may judge a program pass or a program error based on a check read result from the page buffer unit 130 provided. The control unit 160 can the non-volatile storage device 100 so as to perform a program, a read, a delete, a state read and reorder program operations.

The control unit 160 can be a reorder control 161 include. The reorder control 161 may control a state read operation for detecting (or predicting) a charge reordering property of a programmed memory cell and a program operation in consideration of rearrangement according to the state read result.

2 is a diagram showing a memory cell array in 1 according to one embodiment. With reference to the 1 and 2 , includes a memory cell array 110 a plurality of memory blocks BLK1 to BLKz. In this example, each of the memory blocks BLK1 to BLKz may have a three-dimensional memory cell array structure (or a vertical memory cell array structure). For example, each memory block BLK1 to BLKz may comprise a memory cell array extending in the first, second and third directions. Although not in 2 As shown, each of the memory blocks BLK1 to BLKz may include a plurality of rows of cells extending along the second direction. Although not in 2 As shown, a plurality of rows of cells may be spaced apart along the first and third directions.

Cell rows (not shown) within a memory block may be coupled to a plurality of bit lines BL, a plurality of row select lines SSL, a plurality of word lines WL, one or more ground select lines GSL and a common source line. Cell rows in the plurality of memory blocks BLK1 to BLKz may share a plurality of bit lines. For example, the plurality of bit lines may extend along the second direction so as to be shared by the plurality of cell blocks BLK1 to BLKz.

The plurality of memory blocks BLK1 to BLKz may be controlled by an address decoding unit 120 in 1 to be selected. For example, the address decoding unit 120 be configured to select among the plurality of memory blocks BLK1 to BLKz a memory block corresponding to an input address ADDR. It can be made a deletion, programming and reading on a selected memory block. The plurality of memory blocks BLK1 to BLKz will be described with reference to FIGS 3 to 6 described in more detail.

3 is a plan view of a portion of a memory block in FIG 1 according to one embodiment. 4 is a perspective view taken along a line IV-IV 'in 3 according to one embodiment. 5 is a cross-sectional view along a line IV-IV 'in 3 according to one embodiment.

With reference to the 3 to 5 For example, three-dimensional memory cell arrays may be provided that extend along first to third directions.

It can be a substrate 111 be provided. The substrate 111 For example, it may be a drain having a first conductive type. The substratum 111 may be a p-type well in which the group III element such as boron is injected. The substrate 111 may be a p-type pocket sink provided within an n-type well. Below it can be assumed that the substrate 111 a p-doped well (or a p-doped pocket sink). However, the substrate is 111 not limited to a p-doped type.

A plurality of common source portions CSR extending along the first direction may be formed in the substrate 111 be provided. The common source sections CSR may be spaced apart along the second direction. The common source sections CSR may be connected together to form a common source line.

The common source sections CSR may have a second conductive type extending from the substrate 111 different. For example, the common source sections CSR may be an n-doped type. It will be assumed below that the common source sections CSR are of the n-doped type. However, the common source sections CSR are not limited to the n-doped type.

Between two adjacent portions of the common source portions CSR, a plurality of insulating materials 112 and 112a on the substrate 111 successively along the third direction (ie, a direction perpendicular to the substrate 111 ) be provided. The insulation materials 112 and 112a may be spaced apart along the third direction. The insulation materials 112 and 112a may extend along the first direction. For example, the insulation materials 112 and 112a an insulating material such as a semiconductor oxide film. The insulation material 112a that with the substrate 111 Being in contact can be thinner in thickness than other insulation materials 112 be.

Between two adjacent portions of the common source portions CSR, a plurality of pillars PL may be arranged with each other along the first direction such that they are the plurality of insulating materials 112 and 112a penetrate along the second direction. For example, the supports PL with the substrate 111 through the insulation materials 112 and 112a stay in contact.

In one embodiment, the pillars PL between two adjacent common source sections CSR may be spaced apart along the first direction. The pillars PL may be arranged along the first direction in a line.

In one embodiment, the pillars PL may each be formed from a plurality of materials. Each of the pillars PL may have a channel layer 114 and an inner material 115 that within the channel layer 114 is provided include.

The channel layer 114 may comprise a semiconductor material (eg, silicon) having a first conductive type. For example, the channel layer 114 a semiconductor material (eg, silicon), the same type as the substrate 111 having. The channel layer 114 may include an intrinsic semiconductor, which is a nonconductor.

The inner materials 115 may have an insulating material. For example, the inner materials 150 an insulating material such as silicon oxide. Otherwise, the inner materials 115 Include air gaps.

Between two adjacent portions of the common source sections CSR may be on exposed surfaces of the insulating materials 112 and 112a and the supports PL information storage films 116 be provided. The information storage films 116 can store information by trapping or releasing charges.

Between two adjacent common source sections CSR and between the insulation materials 112 and 112a may be on exposed surfaces of the information storage films 116 conductive materials CM1 to CM8 be provided. The conductive materials CM1 to CM8 may extend along the first direction. The conductive materials CM1 to CM8 on the common source sections CSR may be separated by word line cutouts. The common source sections CSR may be exposed by the word line cutouts. The wordline cutouts may extend along the first direction.

In an embodiment, the conductive materials CM1 to CM8 may comprise a metallic conductive material. The conductive materials CM1 to CM8 may comprise a non-metallic conductive material such as polysilicon.

In one embodiment, an information storage movie 116 provided on an upper surface of an insulating material, at the uppermost layer of the insulating layers 112 and 112a is positioned to be removed. For example, information storage films stored on opposite sides of the supports PL from the Sides of the insulation materials 112 and 112a are intended to be removed.

A plurality of manholes 320 may be provided on the plurality of pillars PL, respectively. The shafts 320 may comprise a semiconductor material (eg, silicon) having a second conductivity type. The shafts 320 may comprise an n-doped type semiconductor material (eg, silicon). Below it is assumed that the shaft 320 includes an n-type silicon. However, the present invention is not limited thereto. The shafts 320 can become the top of the channel layers 114 extend the supports PL.

The bit lines BL extending in the second direction may be so on the wells 320 be provided that they are spaced apart along the first direction. The bit lines BL can with the shafts 320 be coupled. In this embodiment, the wells 320 and the bit lines BL are connected via contact plugs (not shown). The bit lines BL may comprise a metallically conductive material. In part, the bitlines BL may comprise a non-metallic conductive material such as polysilicon.

Below, the conductive materials CM1 to CM8 may be in conformity with a distance from the substrate 111 have a first height up to an eighth height.

The plurality of pillars PL may be used together with the information storage films 116 and the plurality of conductive materials CM1 to CM8 form a plurality of cell rows. Each of the pillars PL can film a cell row with information storage films 116 and adjacent conductive materials CM1 to CM8.

The supports PL can be on the substrate 111 be provided along row and column directions. The eighth conductive material CM8 may form rows. Supports connected to the same eighth conductive material CM8 can form a row. The bit lines BL can form columns. Supports connected to the same bit line BL can form one column. The pillars PL may form a plurality of lines which together with the information storage films 116 and the plurality of conductive materials CM1 to CM8 extend in row and column directions. Each cell row may comprise a plurality of cell transistors CT in a direction perpendicular to the substrate 111 are stacked.

6 is an enlarged diagram illustrating one of the cell transistors in FIG 5 represents. With reference to the 3 to 6 , cell transistors CT may be made of conductive materials CM1 to CM8, pillars PL, and information storage films 116 formed between the conductive materials CM1 to CM8 and the pillars PL.

The information storage films 116 may extend to the upper surfaces and lower surfaces of the conductive materials CM1 to CM8 of regions between the conductive materials CM1 to CM8 and the pillars PL. Each of the information storage films 116 may be first to third sub-insulation films 117 . 118 and 119 include.

The cell transistors CT and the channel layers 114 The pillars PL may comprise the same p-type silicon as the substrate. The channel layers 114 may serve as the body of the cell transistors CT. The canal layer 114 can be in a direction perpendicular to the substrate 111 be educated. The channel layers 114 the supports PL can serve as vertical bodies. At the channel layers 114 vertical channels can be formed.

The first underinsulation films 117 which are adjacent to the pillars PL may serve as tunnel insulating films of the cell transistors CT. For example, the first sub-insulation films 117 each comprise a thermal oxide film. The first underinsulation films 117 each may comprise a silicon oxide film.

The second sub-insulation films 118 may serve as charge storage films of the cell transistors CT. For example, the second sub-insulation films 118 each serve as a charge trapping film. For example, the second sub-insulation films 118 each comprise a nitride film or a metal oxide film.

The third sub-insulation films 119 which are adjacent to the conductive materials CM1 to CM8 may serve as the blocking insulating film of the cell transistors CT. In this embodiment, the third sub-insulation films 119 be formed of a single layer or multiple layers, the third sub-insulation film 119 may be a high dielectric film (eg, an alumina film, a hafnium oxide film, etc.) having a dielectric constant larger than those of the first and second sub-insulation films 117 and 118 is. The third sub-insulation films 119 each may comprise a silicon oxide film.

In this embodiment, the first to third sub-insulation films 117 to 119 as ONA (oxide-nitride-aluminum-oxide) or as ONO (oxide-nitride-oxide). The majority of Conductive materials CM1 to CM8 can each serve as a grid (or control grid).

That is, the plurality of conductive materials CM1 to CM8 serving as grids (control gratings) are the third among insulating films 119 which serve as block insulation films, the second under insulation films 118 serving as charge storage films, the first under insulation films 117 , which serve as tunnel insulating films, and the channel layers 114 serving as vertical bodies may form a plurality of cell transistors CT stacked in a direction perpendicular to the substrate. For example, the cell transistors CT may be cell traps of charge trapping type.

The cell transistors CT can be used for various purposes according to the height. For example, among the cell transistors CT, those cell transistors having at least one height and arranged at an upper part may be used as row selection transistors. The row select transistors are used. The row select transistors may be configured to perform switching between cell rows and bit lines. Among the cell transistors CT, those cell transistors having at least one height and arranged at a lower part may be used as ground selection transistors. The ground selection transistors may be configured to perform switching between cell rows and a common source line formed of common source sections CSR. Cell transistors between cell transistors used in series and ground selection transistors can be used as memory cells and dummy cells.

The conductive materials CM1 to CM8 may extend along the first direction and be connected to the plurality of pillars PL. The conductive materials CM1 to CM8 may form conductive lines connecting the cell transistors CT of the pillars PL with each other. In this embodiment, the conductive materials CM1 to CM8 may be used according to the height as a row selecting line, ground selecting line, word line or dummy word line (dummy).

Conductive lines connecting cell transistors and used as row select transistors can be used as row select lines. Conductive lines connecting cell transistors and used as ground selection transistors can be used as ground select lines. Conductive lines connecting cell transistors and used as memory cells can be used as word lines. Conductive lines connecting cell transistors and used as dummy memory cells can be used as dummy word lines.

7 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to one embodiment. Regarding 3 to 7 , cell rows CS11, CS12, C21 and CS22 may be provided between bit lines BL1 and BL2 and a common source line CSL. Cell rows CS11 and CS21 may be connected between the first bit line BL1 and the common source line CL, and cell rows CS12 and CS22 may be connected between the bit line BL2 and the common source line CSL.

Common source sections CSR may be connected together to bind a common source line CSL.

The cell rows CS11, CS12, CS21 and CS22 can be four supports of a part EC of a plan view in 3 correspond. The four supports can be used together with conductive materials CM1 to CM8 and information storage films 116 four cell rows form CS11, CS12, CS21 and CS22.

In this embodiment, the first conductive material CM <b> 1 may be associated with the information storage films 116 and pillars PL form mass selection transistors GST. The first conductive material CM1 may form a ground selection line GSL. The first conductive materials CM1 may be connected together to form a ground selection line GSL.

The second to seventh conductive materials CM2 to CM7 may be used with the information storage films 116 and the pillars PL form a first to sixth memory cell MC1 to MC6. The second to seventh conductive materials CM2 to CM7 may be used as second to sixth word lines WL2 to WL6.

The second conductive material CM2 may be connected to each other to form the first word line WL1. The third conductive material CM3 may be connected to each other to form the second word line WL2. The fourth conductive material CM4 may be connected to each other to form the third word line WL3. The fifth conductive material CM5 may be connected to each other to form the fourth word line WL4. The sixth conductive material CM6 may be connected to each other to form the fifth word line WL5. The seventh conductive material CM7 may be connected to each other to form the sixth word line WL6.

The eighth conductive material CM8 may be connected to the information storage films 116 and form the columns PL row select transistors SST. The eighth conductive material CM8 may form row select lines SSL1 and SSL2.

Memory cells of the same height may be commonly connected to a wordline. Accordingly, when a voltage is applied to a word line of a certain level, it can be applied to all cell lines CS11, CS12, CS21 and CS22.

Cell rows in different rows may each be connected to different row select lines SSL1 and SSL2. The cell lines CS11, CS12, CS21 and CS22 can be selected or not selected by selecting or not selecting the row selection lines SSL1 and SSL2 by the row. For example, cell lines (CS11 and CS12) or (CS21 and CS22) connected to an unselected row selection line SSL1 or SSL2 may be electrically disconnected from the bit lines BL1 and BL2. Cell lines (CS21 and CS22) or (CS11 and CS12) connected to a selected row selection line SSL2 or SSL1 can be electrically connected to the bit lines BL1 and BL2.

The cell rows CS11, CS12, CS21 and CS22 may be connected through the column with the bit lines BL1 and BL2. The cell lines CS11 and CS21 may be connected to the bit line BL1, and the cell lines CS12 and CS22 may be connected to the bit line BL2. The cell rows CS11, CS12, CS21 and CS22 can be selected or not selected by selecting or not selecting the bit lines BL1 and BL2 through the column.

8A FIG. 12 is a diagram of an exemplary memory cell transistor showing a plurality of electrons that are in an electron capture layer. FIG 118 ' are trapped under the grid of the memory cell transistor. The charge trapping layer 118 ' may be a nitride film or a metal oxide film. The charge trapping layer 118 ' is between isolation films 119 ' and 117 ' , which may be, for example, silica films. A channel of a memory cell transistor may be in one layer 114 ' formed in or out of a semiconductor substrate such as silicon germanium, gallium arsenide or indium phosphide crystal in wafer.

8B Fig. 12 illustrates an exemplary Vth (voltage threshold) distribution amount R of a plurality of memory cell transistors immediately after programming the plurality of memory cell transistors. The plurality of memory cell transistors may be connected to the same word line and may be programmed at the same time. The Vth distribution amount R may represent a value of one bit in SSLC memory cell transistors (eg, a "0") or values of bits stored in MLC memory cell transistors (eg, "0/1"). Otherwise, Vth distribution amounts (not shown) may represent other values of one bit (for SSLC memory cell transistors) or bits (for MLC memory cell transistors). The Vth scope of 8B may extend from a program verify voltage VFY to a second voltage value VFY + Δ.

8C FIG. 12 illustrates an exemplary V th distribution of the plurality of memory cell transistors after charge reassembly within each memory cell transistor of the plurality of memory cell transistors. As indicated by the arrows in FIG 8A As shown, electrons may be within a charge trapping layer 118 ' during a programming move after being initially in the charge trapping layer 118 ' have been captured. Electrons migrating down from the grid to the channel (in layer 114 ' ) can help to increase the voltage threshold Vth of the memory cell transistor, and electrons flowing horizontally (left to right in FIG 8A ) can help lower the voltage threshold Vth of the memory cell transistor. Thus, a voltage threshold Vth of a memory cell transistor may naturally increase or decrease after a period of time after programming beyond the voltage threshold R, although initially programmed within the range R. An exemplary amount of stress after a charge reorganization is in 8C for the plurality of memory cell transistors described above with reference to FIG 8B are shown. As in 8C As can be seen, the Spannungsschwellwertumfang is greater than a perimeter R after a charge reordering 8B , including memory cell transistors having voltage thresholds greater than the circumference R (at C - an example of "top end" or "excess end" memory cell transistors) and memory cell transistors having voltage thresholds smaller than the circumference R (at A - an example of memory cell transistors of the "lower end"). If a margin between adjacent Vth circumferences representing different values of one bit (or bits) is small, such charge re-ordering may result in misinterpretations (or inability to interpret) a threshold value of a memory cell transistor. For example, memory cell transistors at A or C may have voltage thresholds of an extent that is consistent with a different data bit value (or different values of bits).

8D FIG. 10 is an enlarged diagram of a right portion of a cell transistor in FIG 6 , Regarding 8D is an information storage movie 116 shown, the first to third sub-insulation films 117 to 119 , a fifth conductive material CM5 and a channel layer 114 includes.

When a cell transistor CT in the 6 and 8D can be programmed, charges of the channel layer 114 the first sub-insulation film 117 through, and through the second sub-insulation film 118 be captured. When charges through the second sub-insulation film 118 can be adjusted, a threshold voltage of the cell transistor CT can be adjusted.

Charges passing through the second insulation film 118 can be in an unstable state. Charge reassembly may occur when trapped charges within the second sub-insulation film 118 can change to achieve a stable state.

Electric fields under the fifth conductive material CM5, the trapped charges and the channel layer 114 can be varied before and after a charge reorganization. That is, a threshold voltage of the cell transistor CT may be varied before and after a charge reassembly. Although the cell transistor CT is programmed to have a target threshold voltage, the threshold voltage due to the charge reassembly may become higher or lower than the target threshold voltage.

Programming may be done in consideration of charge reordering to reduce or avoid the problem described above.

9 FIG. 10 is a flowchart for describing a programming method according to an embodiment. FIG. With reference to the 1 . 7 and 9 At step S110, program data to be stored in memory cells may be received. For example, program data can be received. The received program data may be determined to be stored in memory cells in accordance with a selected row select line and a selected word line. The program data may first be stored in data flip-flops DL before being stored in memory cells.

At operation S120, it may be determined whether the program data corresponds to MSB programming. If it is determined that the program data does not correspond to MSB programming, the program data may be stored in the memory cells in a conventional manner at operation S140. For example, the program data may be stored under the condition that a charge reordering is disregarded.

If it is determined that the program data corresponds to MSB programming, read operations S130 and Si 50 may be performed before the MSB programming in step S160. At operation S130, a read operation may be performed on the memory cells to determine an erasure state and at least a program state. For example, if MSB programming is to program a word line of memory cells previously programmed with LSB data, a read from that word line may be performed on the memory cells to determine the LSB data of the word line. The LSB data of the memory cells may be indicative of an erase state (eg, LSB data of "1") and a program state (eg, LSB data of "0"). A readout result can be stored in the data flip-flops DL.

At operation S150, a state read operation may be performed on at least one program state using a plurality of state read voltages. For example, a state read operation may be performed on at least one program state for each memory cell. In the example of MSB programming a word line of memory cells and reading out LSB data from that word line in step S130, the state read operation of S150 may perform one or more state readings of memory cells having LSB data of "0", i. h., to those memory cells of the wordline previously programmed during the LSB programming process. A state read result may be stored in reorder flip-flops RL.

At operation S160, MSB program data may be programmed according to the state read result using a plurality of check voltages having different levels in the memory cells. For example, in MSB programming, some of the memory cells of a wordline may be oriented to change from a Vth level of the memory cells to a particular Vth size to indicate particular MSB / LSB data (eg, a Vth size) indicating "0/0" data for LSB data and MSB data). These "0/0" data memory cells can be programmed using different verify voltages.

The state read operation and the program operation in response to the state read result must be limited for programming the MSB data. The state read operation and the program state in response to the state read result may also be applied to program data other than MSB data.

10 FIG. 12 is a diagram illustrating a threshold voltage distribution of memory cells when programming LSB data in certain memory cells, such as certain EEPROM memory cells, NOR flash memory cells, and NAND flash memory cells. In 10 For example, a horizontal axis indicates a threshold voltage, and a vertical axis indicates the number of memory cells. The illustrated memory cells may be memory cells connected to a wordline of the memory array, such as a physical page of memory cells in a NAND flash memory.

Before LSB data is programmed, memory cells may be in an erase state E. In this embodiment and in other embodiments described herein, an erase operation is not described, but may be any known operation. If the memory device is a flash memory device, the erase operation may erase a block of memory cells by lowering their threshold voltages to an erase state E at the same time. Thereafter, if memory cells having the erasure state E are subsequently programmed with LSB data, they may thereafter either have an erase state or an LSB program state LP (e.g., depending on whether the LSB data of the memory cell is to be stored) an erasure state represents "1" LSB data, and the LSB program state LP may represent "0" LSB data). The memory cells programmed into the LSB program state LP may be programmed to have a threshold voltage higher than a verify voltage VFY1.

Memory cells programmed into the LSB program state LP may undergo charge reassembly. The charge reordering can bring threshold voltages of the memory cells to deviations. The threshold voltages of the memory cells may be varied by mechanisms other than charge reassembly, such as charge dissipation, read disturbance (e.g., charge injection due to readout), or charge coupling to adjacent memory cells. This may mean that a threshold voltage distribution of memory cells having the LSB program state LP expands.

11 FIG. 14 is a flowchart illustrating exemplary details of the process S150 for performing a state read operation in FIG 9 are provided. With reference to the 1 . 9 and 11 In operation S151, program states of the memory cells may be read out using a normal state read voltage to designate lower-end memory cells. For example, memory cells programmed in the LSB program state LP and read out as memory cells having a threshold voltage lower than the normal state read voltage may be judged to be lower-end memory cells.

At operation S153, program states of the memory cells may be read out using an upper state read voltage to designate upper-end memory cells. For example, memory cells programmed in the LSB program state LP and read out as memory cells having a threshold voltage higher than the normal state read voltage may be judged to be upper-end memory cells. The upper state read voltage may have a higher level than the normal state read voltage.

At operation S155, a state read result may be stored in reordering flip-flops RL. The state read result may indicate which of the memory cells programmed in the LSB program state LP are the lower-end memory cells, the upper-end memory cells, and which are neither lower-end nor upper-end memory cells (eg, normal memory cells) ,

12 FIG. 12 is a diagram illustrating an exemplary method of performing a state read operation. FIG 11 shows. With reference to the 1 . 11 and 12 For example, a state read operation may be performed for each program state (e.g., each Vth extent representing data previously programmed into the memory cells). In 12 if there is only one program state, one LSB program state LP, and thus this example describes the state read operation with respect to the LSB program state LP.

A read voltage Vrd1 may be a voltage used to discriminate such memory cells having an erase state E from those memory cells having an LSB program state LP. For example, the read voltage Vrd1 may be applied to a selected word line, while a non-selected word line may be applied with a through voltage (to ensure that memory cell transistors that are not connected to the non-selected word lines) selected word line are turned on). After or during application of charges to bit lines respectively connected to the selected memory cells, application of the read voltage Vrd1 to the selected word line, to those memory cells of the selected word line, having a threshold voltage lower than Vrd1 (such memory cells that are turned on) that the charge (voltage) on a corresponding bit line is derived to ground (ground), whereas those memory cells of the selected word line having a threshold voltage higher than Vrd1 remain off, and a charge on corresponding ones Keep bitlines. Therefore, detection of the charge or voltage on a bit line can be used to determine a voltage threshold (Vth) level of a corresponding memory cell connected to the selected word line, and thus used to represent corresponding data.

A state read operation may be performed using a normal state read voltage VSRN1. Such memory cells having an LSB program state LP and having a threshold voltage lower than the normal state read voltage VSRN1 may be judged to be lower-end memory cells LPL.

A state read operation may be performed using an upper state read voltage VSRU1. Such memory cells having an LSB program state LP and having a threshold voltage higher than the upper state read voltage VSRU1 may be judged to be upper-end memory cells LP_U. If there is no program state that is higher than an LSB program state LP previously programmed in the memory cells (eg, the page or word line of the memory cells), each memory cell of the memory cells (eg, the page or word line of FIG Memory cells) having a threshold voltage higher than the upper state read voltage VSRU1 can be judged as the upper-end memory cell LP_U.

Memory cells having a threshold voltage higher than the normal state read voltage VSRN1 and lower than the upper state read voltage VSRU1 may be judged to be normal memory cells LP_N.

When no charge reassembly is generated, in one embodiment, the normal state read voltage VSRN1 and the upper state read voltage VSRNU1 may have a level corresponding to an amount of threshold voltage distribution of the memory cells having the LSB program state LP. The normal state read voltage VSRN1 may have the same level as a verify voltage VFY1 (see FIG. 10 ) used when memory cells are programmed to have the LSB program state LP. The upper state read voltage VSRU1 may have a level equal to the upper end of the perimeter of the LSB program state LP estimated during construction of the memory device, an estimate being based on testing similar memory devices or testing the memory device during a test A process downstream of manufacture, based, or regularly determined and adapted during a lifetime of the memory device by performing a series of stepwise reads on data of the LSB program state LP shortly after programming (eg, corresponding to the highest Vth of the memory cells programmed into the LSB program state LP, immediately or shortly after programming these memory cells).

The lower-end memory cells LP_L may have a threshold voltage level lower than the normal state read voltage VSRN1. That is, the lower-end memory cells LP_L may be memory cells whose threshold voltages are lower due to the charge reassembly or other factors.

The upper end memory cells LP_U may have a threshold voltage level higher than the upper state read voltage VSRU1. That is, the upper-end memory cells LP_U may be memory cells whose threshold voltages become higher due to the charge reordering or other factors. When the state read operation is performed, it is possible to determine the lower-end memory cells LP_L whose threshold voltages are lower due to the charge reassembly and the upper-end voltage cells LP_U whose threshold voltages become higher due to the charge reordering. That is, it is possible to distinguish characteristics of the threshold voltages of the memory cells that vary due to the charge rearrangement or other factors.

13 FIG. 14 is a flow chart for describing exemplary details of the process S160 of programming memory cells with program data in FIG 9 , With reference to the 1 . 9 and 13 At step S161, bit lines BL may be taken. For example, the bit lines BL may be occupied in accordance with data stored in the data flip-flops DL. For example, the Bit lines BL coincide with program data and data stored in advance in memory cells are taken. In response to a level of sense voltage applied to the bitlines (eg, a logic high or a logic low voltage), memory cells connected to the bitline may be selected to be programmed or prevented from programming to become. See, for example, B. U.S. Patent No. 5,473,563 for exemplarily taking bitlines to prevent or allow memory cells to be programmed in a programming step. The U.S. Patent No. 5,473,563 is incorporated herein by reference to its teachings of programming operations on flash memories and related structures, as well as providing exemplary details as to the structure, shape, and operations of a two-dimensional NAND flash memory.

At operation S162, a program voltage VPGM may be supplied to the selected word line, and a continuity voltage VPASS may be supplied to the unselected word lines. The programming voltage VPGM may be a voltage sufficient to allow a Fowler signal to be selected at the memory cells of the selected wordline selected for programming (eg, in response to the sense voltage applied to the bitlines). Nordheim tunneling is generated. The pass voltage VPASS may be a voltage sufficient to turn on such memory cells connected to unselected word lines (eg, memory cells of a memory cell row not connected to the selected word line) to channels in those memory cells to build.

In operations S163, S164, S165, S166, S167 and S168, a check of the programming of the memory cells of the selected word line is performed at different verify voltages. The verify voltage used to verify programming depends on whether the memory cell was previously designated as an upper-end memory cell LP_U, a normal memory cell LP_N, or a lower-end memory cell LP_L. At operation S163, a lower verify voltage may be applied to the selected word line, and a non-selected read voltage may be applied to the unselected word lines. The level of the lower verify voltage may be lower than a normal verify voltage. The unselected read voltage may be a voltage sufficient to turn on those memory cells connected to the unselected word lines (eg, memory cells of a memory cell row not connected to the selected word line) in these memory cells To form channels.

At operation S164, a check result may be stored in data flip-flops DL corresponding to upper-end memory cells LP_U. A lower verify voltage may be applied to the selected wordline to verify programming of the upper-end memory cells LP_U. In this example, a lower verify voltage may be used to verify normal memory cells LP_N and lower-end memory cells LP_L.

At operation S165, a normal check voltage may be provided to the selected word line to check programming of the normal memory cells LP_N, and a non-selected read voltage may be provided to the unselected word lines. The normal verify voltage may be higher than the normal verify voltage and lower than an upper verify voltage. At process 166 For example, a check result may be stored in data flip-flops DL corresponding to the normal memory cells. In this example, the normal verify voltage may be used to verify the normal memory cells LP_N, whereas it may not be used to verify upper-end memory cells LP_U and lower-end memory cells LP_L.

At operation S167, an upper verify voltage may be applied to the selected word line, and a non-selected read voltage may be applied to the unselected word lines. The level of the upper verify voltage may be higher than the normal verify voltage. In process Si 68, a check result may be stored in data flip-flops DL corresponding to the lower-end memory cells LP_L. That is, the upper verify voltage may be used to verify the lower-end memory cells LP_L, whereas it may not be used to verify normal memory cells LP_N and upper-end memory cells LP_U.

At operation S169, a program run can be judged. The programming operation may end when it is determined that all the memory cells to be programmed have been checked for being programmed to their Vth level after their corresponding verify voltage (as described above with respect to steps S163, S165, and S167 ) and as shown by the results stored in the corresponding data flip-flops, is reproduced (as described above with respect to steps S164, S166 and S168). The wordline programming may thus either end completely for this data or for that record (eg, "0/1") at step S169 and continue at the next record (eg, "0/0"). If it is determined that some of the memory cells have not been programmed to the Vth level after their corresponding verify level, the process may return to the beginning and repeat the programming and verification. Steps S161 through S169 may be repeated until programming of all the selected memory cells is confirmed by step S169 (run), or with a predetermined (eg, predetermined) number of repetitions (which may indicate an error in programming the word line, and can indicate a faulty set of memory cells or a "bad block" of memory cells requiring an exchange).

14 FIG. 13 is a diagram illustrating a threshold voltage distribution of memory cells consistent with a programming method in FIG 13 are programmed. In this example, memory cells of a selected wordline are to be programmed with a second-order 2SB bit. Prior to programming the memory cells of the selected second-order 2SB wordline, the memory cells of the selected wordline have been programmed with LSB least significant bit data and either have an erasure state E Vth (represents a binary logical value of LSB data such as "1 Or are programmed from the erase state E to the LSB program state LP (representing the other binary logical value of the LSB data, such as "0").

With reference to the 1 . 9 and 14 For example, memory cells having an LSB program state LP may be programmed into a second program state P2 or a third program state P3. Memory cells with an erasure state E can maintain the erase state E or can be programmed into a first program state P1. The resulting states (erasure state and program states P1, P2 and P3) may each represent two bits of the data (LSB data and 2SB data). For example, the erasure state and the program states P1, P2 and P3 may represent 2SB / LSB data bits such as "1/1", "0/1", "1/0" and "0/0", respectively.

When memory cells previously programmed in the LSB program state LP are programmed by increasing a threshold voltage value of the memory cells to either the P2 program state or the P3 program state having 2SB data, memory cells LP_N having the LSB program state LP may be used normal verify voltage VFYN1 or VFYN2 to a second normal program state P2_N or a third normal program state P3_N. Upper-end memory cells LP_U having the LSB program state LP may be programmed into a second lower program state P2_L or a third lower program state P3_L using a lower verify voltage VFYN1 or VFYN2. Lower-end memory cells LP_L having the LSB program state LP may be programmed into a second upper program state P2_U or a third upper program state P3_U using an upper verify voltage VFYU1 or VFYU2. For each of these memory cells in the LSB program state (LP_L, LP and LP_U), the 2SB data bit to be programmed into the memory cell may determine whether the memory cell is programming to the second normal program state P2 (P2_U, P2_N or P2_L, respectively) is programmed, or in the third normal program state P3 (P3_U, P3_N or P3_L respectively) is programmed.

The second lower program state P2_L, the second normal program state P2_N and the second upper program state P2_U may design the second program state P2. The third lower program state P3_L, the third normal program state P3_N and the third upper program state P3_U may configure the third program state P3.

The lower verify voltage VFYL1 or VFYL2 may each have a lower level than the normal verify voltage VFYN1 or VFYN2, and the upper verify voltage VFYU1 or VFYU2 may each have a higher level than the normal verify voltage VFYN1 or VFYN2.

15 FIG. 12 is a diagram illustrating a threshold voltage deviation due to charge reassembly generated on memory cells generated in accordance with a 14 programmed procedures are programmed. With reference to the 1 . 9 and 15 For example, a charge reassembly may be generated on memory cells programmed in the first to third program states P1 to P3.

Upper-end memory cells LP_U whose threshold voltages become higher due to the charge reordering can be programmed in a second or third lower program state P2_L or P3_L. Upper-end memory cells LP_U had previously been determined to have charge re-ordering characteristics which result in a higher threshold voltage (Vth) of the memory cell after a charge reassembly (e.g., state reads as described herein, such as those described with respect to FIGS 9 to 12 are described). By programming the upper-end memory cells LP_U to a lower extent of the second or third program state P2 or P3 (ie, P2_L or P3_L), threshold voltages of the memory cells having the second or third lower program state P2_L or P3_L during future charge reordering with respect to these memory cells is increased so that a threshold voltage distribution varies to a second or third normal program state P2_N or P3_N.

For lower end memory cells LP_L whose threshold voltages are lowered by the charge reassembly, P2_U or P3_U may be programmed into a second or third upper program state. Lower-end memory cells LP_L have previously been determined to have charge-reground characteristics that result in a lower threshold voltage (Vth) of the memory cell after charge reassembly (e.g., state reads such as those described herein with respect to FIGS 9 to 12 are described). By programming the lower-end memory cells LP-L to a higher extent of the second or third program state P2 or P3 (ie, P2_H or P3_H), the threshold voltages of these memory cells may be related to the second or third upper program state P2_U or P3_U during a future charge reassignment are lowered to these memory cells, so that a threshold voltage distribution varies to the second or third normal program state P2_N or P3_N.

In this example, memory cells whose threshold voltages are increased due to charge reassembly may be programmed using a verify voltage that is lower than a normal verify voltage. Memory cells whose threshold voltages are lowered due to charge reassembly may be programmed using a verify voltage that is higher than the normal verify voltage. If programming is performed using check voltages determined in consideration of charge reordering, a threshold voltage distribution of the memory cells may be narrowed due to charge reordering, whereby data reliability can be improved, with smaller spans between program states and / or an increased number of program states (or bits / cell) of the memory cells are enabled.

When memory cells are programmed with multi-bit data, a read can be performed to determine the data previously stored in the memory cells. The 14 and 15 show read voltages of Vrd1, Vrd2, Vrd3 that can be applied to select a wordline in a read operation to determine the program state (E, P1, P2 or P3) of the memory cells connected to the selected wordline, and thus the Read out data of the memory cells. Depending on the data to be read (eg LSB or MSB), one or more readings may be required with one or more read voltages Vrd1, Vrd2, Vrd3. In addition to the read-out for determining the stored data, state read operations for determining a charge reassembly, a Vth change and / or upper and lower-end memory cells of each program state may be performed.

A case where a state read operation is performed for each program state using two state read voltages will be described. However, the inventive concept is not limited thereto. For example, a resolution may be desired in determining the tendency of a change in the Vth of the memory cell. In such a case, four state read voltages may be used to determine large upper-end memory cells, upper-end small memory cells, normal memory cells, lower-end small memory cells, and lower-end large memory cells (each memory cell having a tendency to have a large Vth Increase, a small Vth increase, a small or no Vth change, a small Vth decrease, and a relatively large Vth decrease). In this case, five verify voltages may be used during programming that correspond to this memory cell classification. Other modifications are also provided. For example, if it is determined that a Vth varies in a direction (higher or lower) that may tend to be greater than in another direction, more state read voltages in that direction than in the other direction may be used to surround the memory cells to classify. Otherwise, state read voltages can be used to determine only upper end memory cells, and no distinction can be made between lower end memory cells and normal memory cells. Otherwise, state read voltages can be used to determine only upper end memory cells, and no distinction can be made between lower end memory cells and normal memory cells.

16 FIG. 5 is a timing diagram illustrating voltages that are determined according to an in. FIG 14 described programming method can be applied to a selected word line. In one embodiment, in 16 Represent voltages that are used to program memory cells into a second program state P2. With reference to the 13 . 14 and 16 For example, a programming voltage VPGM may be applied to select a word line. Thereafter, successively, a lower verify voltage VFYL1, a normal verify voltage VFYN1, and an upper verify voltage VFYU1 may be applied to the selected word line. The application of the program voltage VPGM and the verify voltages VFYL1, VFYN1 and VFYU1 may form a program loop.

After a program loop is executed, a control unit can 160 a nonvolatile memory device 100 (see 1 ) evaluate a program run or a program error. Programming can be ended during a program run. If a program error is determined, a next program loop can be performed.

In the next program loop, a programming voltage VPGM with an increased level can be applied. Thereafter, the verify voltages VFYL1, VFYN1 and VFYU1 may be sequentially applied. The programming voltage VPGM can be increased each time the program loops are repeated. Otherwise or additionally, the length of application of the programming voltage VPGM can be increased with each repetition of the program loops.

Page buffers PB may conform to data stored in reordering flip-flops RL (compare 1 ) select a valid verify voltage of the verify voltages VFYL1, VFYN1 and VFYU1. For example, when data stored in a reordering flip-flop RL indicates an upper end memory cell, the page buffer PB may select the lower verify voltage VFYL1 as a valid verify voltage and may ignore other verify voltages VFYN1 and VFYU1. For example, the page buffer PB for upper-end memory cells may take a bit line such that a value of a data flip-flop is not changed when the verify voltages VFYN1 and VFYU1 are applied.

Similarly, when data is stored in a reordering flip-flop RL indicating a normal memory cell, the page buffer PB may select the normal verify voltage VFYN1 as the valid verify voltage, and reads using other verify voltages VFYL1 and VFYU1 may be ignored (not performed). When data is stored in a reordering flip-flop RL indicating an upper end memory cell, the page buffer PB may select the lower verify voltage VFYL1 as a valid verify voltage, and it may ignore reads using other verify voltages VFYN1 and VFYU1.

17 FIG. 11 is a timing diagram illustrating voltages generated in accordance with a programming method similar to those in FIG 13 and 14 described details may be applied to a selected word line. In one embodiment, there are mapped voltages used to program memory cells into second and third program states P2 and P3. Regarding the 13 . 14 and 17 For example, a programming voltage VPGM may be applied to a selected word line. Thereafter, a lower verify voltage VFYL1, a normal verify voltage VFYN1, and an upper verify voltage VFYU1, a lower verify voltage VFYL2, a normal verify voltage VFYN2, and an upper verify voltage VFYU2 may be successively applied to the selected word line. The application of the program voltage VPGM and the verify voltages VFYL1, VFYN1, VFYU1, VFYL2, VFYN2, and VFYU2 may form a program loop.

After the program loop is executed, a control unit can 160 a nonvolatile memory device 100 (see 1 ) determine a program run or a program error. In the case of a program run, a programming can be completed. In the case of a program error, an additional program loop can be executed. In a next program loop, a programming voltage VPGM having an increased level may be applied to the selected word line. Thereafter, successively, the verify voltages VFYL1, VFYN1, VFYU1, VFYL2, VFYN2 and VFYU2 may be applied to the selected word line to check programming of corresponding word line memory cells. A level of the programming voltage VPGM may be increased in each successive repetition of the program loops.

Page buffers PB can select a valid verify voltage in accordance with data found in data flip-flops DL (compare 1 ) and reordering flip-flops RL are stored. For example, if data is in a data flip-flop DL indicate a second program state P2, the page buffer PB may ignore a check of reads using the verify voltages VFYL2, VFYN2 and VFYU2. If data stored in a reordering flip-flop RL indicates a lower-end memory cell, the page buffer PB may select the upper verify voltage VFYU1 as a valid verify voltage and ignore verify reads using the verify voltages VFYN1 and VFYU1. When a non-selected check voltage is applied, the page buffer PB may take a bit line BL such that data of the data flip-flop DL does not deviate.

If data stored in the data flip-flop DL indicates the second program state P2 and data stored in the reordering flip-flop RL indicates a normal memory cell, the page buffer BP may select the normal verify voltage VFYN1 as a valid voltage it can ignore verify reads using the verify voltages VFYL1, VFYU1, VFYL2, VFYN2, and VFYU2.

If data stored in the data flip-flop DL indicates the second program state P2 and data stored in the reordering flip-flop RL indicates an upper-end memory cell, the page buffer BP may set the lower verify voltage VFYL1 as a valid voltage and it can ignore verify reads using the verify voltages VFYN1, VFYU1, VFYL2, VFYN2, and VFYU2.

If data stored in the data flip-flop DL indicates a third program state P3, and data stored in the reordering flip-flop RL indicates a lower-end memory cell, the page buffer BP may set the upper verify voltage VFYU2 as select valid voltage and can ignore verify reads using the verify voltages VFYL1, VFYN1, VFYU1, VFYL2, and VFYN.

If data stored in the data flip-flop DL indicates the third program state P3 and data stored in the reordering flip-flop RL indicates a normal memory cell, the page buffer BP may select the normal verify voltage VFYN2 as a valid voltage. and it can ignore verify reads using the verify voltages VFYL1, VFYN1, VFYU1, VFYL2 and VFYU2.

If data stored in the data flip-flop DL indicates the third program state P3 and data stored in the reordering flip-flop RL indicates an upper end memory cell, the page buffer BP may select the lower verify voltage VFYL2 as a valid voltage and ignore verify reads using the verify voltages VFYL1, VFYN1, VFYU1, VFYN2 and VFYU2.

18 FIG. 15 is a diagram illustrating application of a threshold voltage distribution of the memory cells generated according to a programming method in FIG 13 are programmed. In comparison with threshold voltage distributions in 14 For example, a state read operation may be performed with respect to memory cells having an erase state E, and lower-end memory cells, normal memory cells, and upper-end memory cells in the erase state E may be determined.

Lower-end memory cells having an erase state E may be programmed into a first upper program state P1_U during programming of a second bit 2SB. Normal memory cells having the erasure state E may be programmed into a first normal program state P1_N, and lower-end memory cells having the erase state E may be programmed into a first lower program state P1_L. The first lower program state P1_L, the first normal program state P1_N and the first upper program state P1_U may form a first program state P1.

In addition, a state read operation may be performed with respect to an erase state E, and a program operation may be performed in consideration of a charge reordering determined from the state read operation. For a future charge reordering threshold value distributions of the first to third program states P1 to P3 can be narrowed.

19 FIG. 12 is a diagram illustrating another application of the threshold voltage distribution of the memory cells incorporated in the FIG 10 and 13 are programmed. A state read operation may be performed before performing LSB programming with respect to the memory cells having an erase state E, and lower-end memory cells, normal memory cells, and upper-end memory cells may be determined.

Memory cells having an erase state E may maintain the erase state or be programmed into a LSB program state LP by programming a least significant bit. For those memory cells to be programmed into the LSB program state LP, lower-end memory cells having the erase state E may be programmed into a first upper program state LP1_U; normal memory cells having the erasure state E can be programmed into a first normal program state LP1_N; and upper-end memory cells having the erase state E may be programmed into a first lower program state LP1_L. The first program state LP1_L, the first normal program state LP1_N and the upper program state LP1_U may form an LSB program state LP. Different verify voltages may be used to confirm programming into the various LSB program substates (the first lower program state LP1_L in normal program state LP1_N and the first upper program state LP1_U).

In addition, a state read operation may be performed with respect to an erase state E before LSB programming is performed, and a program operation may be performed in consideration of rearrangement.

A state read operation and a program operation considering a charge reordering for programming a second bit 2SB in the memory cells is described with reference to FIGS 14 to 19 been described. However, the inventive concept is not limited thereto. For example, a state read operation and a program operation may be performed again in consideration of rearrangement to program a third bit, a fourth bit, etc. (which may be a most significant bit). This may be in addition to consideration of charge reordering when programming the second bit 2SB or the second bit 2SB (or other bits) may be programmed without consideration of charge reassembly.

20 FIG. 12 is a block diagram schematically illustrating a nonvolatile memory device according to yet another embodiment. Regarding 20 can be a non-volatile storage device 200 , a memory cell array 210 an address decoding unit 220 , a side buffer unit 230 , a data input / output unit 240 , a voltage generating unit 250 and a control unit 260 include. As with all embodiments, the memory device 200 a semiconductor chip or a group of chips (such as a stack of chips) within a semiconductor chip.

The memory cell array 210 includes a user data area 211 and a buffer area 213 , The nonvolatile storage device 200 can with those in 1 be substantially identical, except that a three-step programming using the buffer area 213 is carried out. The buffer area 213 can be formed integrally with the memory cell array. If the storage device 200 For example, a semiconductor memory chip, the memory area 213 may be formed as a part of the semiconductor chip, and may be of the same memory cell types as the memory cells of the user data area 211 be formed. The storage area 213 may be at a predetermined physical position of the memory cell array 210 be formed by a block management system (which is a modification of the blocks of the memory, which the buffer area 213 and the user data area 211 make possible).

21 FIG. 10 is a flowchart illustrating a programming method according to another embodiment. FIG. With reference to the 20 and 21 For example, in operation S210, an erasure state and at least a program state of the memory cells of the user data area may be selected 311 by reading out memory cells of a buffer area 213 be determined. The buffer area 213 may store the currently stored data (eg, LSB and 2SB data) of the memory cells (eg, a wordline) to be programmed with an additional bit of data (eg, MSB data). Data (eg, LSB and 2SB data) can be programmed either by reading out the memory cells (eg, a wordline) before they are programmed with a succeeding bit (eg, before coarse programming involving an MSB data bit adds) to be stored in advance in the buffer area. Otherwise, data (eg, LSB and 2SB data) may advance in the buffer area 213 while programming the word line with this data (eg, the LSB and 2SB data) before programming the succeeding bit (eg, MSB data). Otherwise, the buffer area 213 store all data to be stored in the memory cell (eg LSB, 2SB and MSB data).

In operation S220, it may be judged whether a fine programming operation should be performed. If not, the process continues at operation S230, which is one-step programming or rough programming. A 1-step and a rough programming can be programming at high programming voltage VPGM or for a longer pulse duration of programming voltage VPGM in Compared to a fine programming include. The rough program state (eg CP1 to CP7 off 22A ) may have a Vth distribution amount greater than the program states resulting from fine programming. The 1-step programming may include only a single programming cycle or multiple programming cycles.

If the fine programming operation is to be performed, the process proceeds to operation S240 where a state read operation using a plurality of state read voltages in a manner as described elsewhere in this disclosure is performed on at least one program state (one or more program states) several of the coarse program states CP1 to CP7 off 22A ). Thereafter, at operation S240, a fine programming operation using a plurality of check voltages having different levels may be performed according to the state read result. The US Patent Laid-Open No. 2011/0222342 is incorporated herein by reference to its teachings of 1-step programming, coarse programming and fine programming, and the use of a buffer area in connection with memory cell programming.

22A FIG. 15 is a diagram illustrating a threshold voltage distribution of memory cells according to a programming method in FIG 21 represents. With reference to the 20 to 22A For example, a one-step programming with respect to the memory cells can be made. The 1-step programming can be performed without a state read operation and a program operation using a state read result. 1-bit or 2-bit data can be stored in a memory cell of a user data area 211 programmed by the 1-step programming. Upon execution of the 1-step programming, program data may further be in a buffer area 213 get saved. For example, the program data may be in single level cells (SSLC) of the buffer area 213 get saved.

If the 1-step programming is performed, memory cells of the user data area 211 which have an erasure state E, maintain an erasure state E, or may be programmed into one of the first to third program states OP1 to OP3. When the 1-step programming results in four states (eg, erasure state E and the first to third program states OP1 to OP3), the 1-step programming may designate the memory cells based on two-bit data (or two data pages for one physical side of the memory). such as programming an LSB and a 2SB bit (and thus selecting each of the memory cells for one of these four states).

Charge reassembly may occur after 1-step programming is completed. If a charge reassembly occurs, a threshold voltage distribution of the first to third program states OP1 to OP3 can be expanded.

Coarse programming can be performed after 1-step programming on 1-step programmed memory cells. Coarse programming may add to each memory cell an additional bit of information (eg, an MSB bit). Rough programming may include reading out the state of the memory cell in the user data area 211 to determine the existing data (eg, two-bit data) to which the additional bit of information is to be added, or the two-bit data can be obtained by reading memory cells of the buffer area 213 (which continue to store the two-bit data until programming is completed). Otherwise, the previously stored data (eg, two-bit data) may be from a source other than the buffer area 213 be obtained, such as a buffer memory in a memory controller, the operations of the memory device 300 controls. The rough programming may be performed in accordance with the determination of the two-bit data previously stored and program data (eg, the additional bit of data for each memory cell) to be programmed. If the rough programming is performed, memory cells may maintain an erase state E, or they may be programmed into a first to seventh coarse program state CP1 to CP7. Further, when the rough programming is performed, the program data may be stored in memory cells of the buffer area 213 get saved. For example, the program data may be in single level cells (SLC) of the buffer area 213 get saved.

After the rough programming is done, a charge reassembly may occur. This can lead to an expansion of threshold voltage distributions of the first to seventh coarse program states CP1 to CP7. In some examples, the threshold voltage distributions of the first to seventh coarse program states CP1 to CP7 may partially overlap one another.

Fine programming can be done in relation to roughly programmed memory cells. As in 21 is shown, the fine programming can be a state read operation and accompany a programming operation using a state read result.

An erasure state and at least a program state of the memory cells of the user data area 211 can by reading out memory cells of the buffer area 213 be determined. The buffer area 213 may store all data (eg, three data pages) of the memory cells being programmed, and this data may be used to determine the erase and program state of each of the memory cells being programmed. A state read operation may be performed with respect to the at least one program state (or an erasure state). If the state read operation is performed, lower-end memory cells, normal memory cells and upper-end memory cells of each program state (or an erasure state) may be determined. For example, memory cells may be determined by being programmed in a coarse programming state CP1 by storing information in the memory area 213 be referenced. When one or more adjacent coarse program states CP1 to CP7 overlap, it may be impractical to determine the coarse program state in which a memory cell has been previously programmed by reading the memory cell. For example, if a memory cell has a Vth value in a Vth distribution range shared by coarse program states CP1 and CP2 (after a charge reorder), it may be impractical to determine whether the memory cell was previously in coarse program state CP1 or coarse Program state CP2 has been programmed. Reference to information (eg, the original three-bit data of the memory cell) may be referenced to determine the coarse program state in which the memory cell was previously programmed.

Memory cells may be programmed according to a state read result using a plurality of verify voltages. The lower end memory cells may be programmed using an upper verify voltage, the normal memory cells may be programmed using a normal verify voltage, and the upper end memory cells may be programmed using a lower verify voltage. Memory cells can be programmed into a first to seventh program state P1 to P7. In an alternative embodiment, the upper end memory cells can not be programmed into the fine programming process. The fine programming operation may be performed on lower end memory cells and normal memory cells, and the Vth levels of the upper end memory cells may remain at the levels resulting from the coarse programming process (although additional charge reassembly, coupling with other memory cells, etc whose Vth level can change). 22B illustrates an example of this alternative with respect to the fine programming of the coarse programming state CP1, it represents upper end memory cells UT in a coarse program state CP1 which remain in their coarse program state, and normal memory cells N which in the fine programming process with a low verify voltage of VFYN, and lower end memory cells LT verified in the fine program with an upper verify voltage VFYU. In this example, the threshold voltage ranges are shown separated from a coarse programming state after fine programming of the lower-end memory cells, the normal and the upper-end, but they may overlap, as in FIG 22A is shown. Although also the alternative 22B the use of a test voltage for upper end memory cells in connection with a modification of the embodiment 22A It is intended that this alternative be equally applicable to other embodiments described herein.

After the fine programming is done, a charge reassembly can be generated. In this case, threshold charge distributions of the first to seventh program states P1 to P7 may become narrower. Ie. the data reliability of the nonvolatile memory device 200 can be improved. Read voltages of Vrd1, Vrd2, ... Vrd7 can be applied to a selected word line in a readout state to determine the program state (E, P1, P2, ... P7) of the memory cells connected to the selected word line, and thus reading the data of the memory cells. Depending on the data to be read (eg LSB or MSB), one or more reads may be required with one or more read voltages Vrd1, Vrd2, ... Vrd7. Read voltages Vrd1, Vrd2, ... Vrd7 may be designed to be centered between adjacent threshold ranges representing the program states (E, P1, P2, ... P7). The read voltages of this and other embodiments shown are outside the scope of the majority of verify voltages associated with a single program state (eg, they are not inserted in the verify voltages associated with a single program state, such as a program state) one of E, P1, P2, ... P7). However, it may be appropriate to allow the read voltages to be within the values Have scope of verification voltages associated with a single program state.

23 FIG. 12 is a block diagram illustrating a nonvolatile memory device according to yet another embodiment. Regarding 23 can be a non-volatile storage device 300 a memory cell array 310 , an address decoding unit 320 , a side buffer unit 330 , a data input / output unit 340 , a voltage generating unit 350 and a control unit 360 include.

The memory cell array 310 can be a user data area 311 and a supplementary area 313 include. The nonvolatile storage device 300 can with those in 1 be substantially identical, except that a state reading result in the supplementary area 313 is programmed. The complementary area 313 can be formed integrally with the memory cell array. If the storage device 300 z. B. is a semiconductor memory chip can be a complementary area 313 may be formed as a part of the semiconductor chip, and may be of the same memory cell type as the memory cells of the user data area 311 be educated. The complementary area 313 may be at a predetermined physical position of the memory cell array 310 be formed or determined by a block management system.

24 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment. Regarding 24 At step S310, the first program data may be programmed into memory cells. For example, the first program data may be received, data previously programmed in memory cells may be read, a state read operation may be performed, and first program data may be stored in accordance with the first program data, the readout result, and the state read result.

At operation S320, the state read result may be in a supplementary area 313 get saved.

At operation S330, second program data to be programmed in the memory cells can be received. For example, the second program data may be upper bit data to be subsequently programmed to the first program data. Otherwise, second program data may be low bit data to be programmed after memory cells are cleared.

At operation S340, an erasure state and at least one program state may be judged by reading memory cells. The process S340 may flow to the process S120 in FIG 9 correspond.

At process S350 may be from the supplementary area 313 a state reading result is read out. A state read result, which at operation S320 enters the supplementary area 313 is programmed, can be read in process S350. The state read result thus read out can be stored in reordering flip-flops RL.

In operation S360, the second program data may be stored in memory cells using a plurality of check voltages having different levels in accordance with the state read result. The process S360 may flow to the process S150 in FIG 9 correspond.

As described above, a reordering characteristic of memory cells may be judged via a state read operation, and a state read result may be in the supplementary area 313 a memory cell array 310 be programmed. Thereafter, when the data is programmed in the respective memory cells, a reordering characteristic according to a state read result included in the supplementary area 313 is programmed, and a programming operation can be performed. The use of state reading results in a supplementary area 313 In a variety of programming operations, use of state results may be enabled without requiring a plurality of state reads (eg, for each memory cell of a physical page of the memory cells, a plurality of programming operations on the memory cell may use a state read result that in the complementary area 313 is stored, and that is obtained by a single state read operation of the memory cell). It may also be possible to modify the state read results programmed in the supplemental area with future state read results. Thus, it is possible to use a nonvolatile memory device 300 to provide improved data reliability and programming methodology.

25 FIG. 12 is a block diagram schematically illustrating a nonvolatile memory device according to yet another embodiment. Regarding 25 can be a non-volatile storage device 400 a memory cell array 410 , an address decoding unit 420 , one Page buffer unit 430 , a data input / output unit 440 , a voltage generating unit 450 and a control unit 460 include.

The memory cell array 410 can be a user data area 411 and a test data area 413 include. The nonvolatile storage device 400 can with those in 1 be substantially identical, except that a reading in relation to the test data area 413 is performed without performing a state read operation.

The test data area 413 may store information associated with a reordering characteristic of memory cells in the user data area 411 related. In another embodiment, memory cells of the user data area 411 in the nonvolatile memory device 400 be tested, and a test result can be in the test data area 413 be programmed.

26 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment. With reference to the 25 and 26 At operation S410, data is received in memory cells of a user data area 411 should be saved. The process S410 may be the process S110 in 9 correspond.

In operation S420, memory cells in the user data area can be read out so that an erasure state and at least one program state can be judged. The process S420 may flow to the process S120 in FIG 9 correspond.

At operation S430, a read operation may be made with respect to memory cells of a test data area 413 , the memory cells of the user data area 411 be executed. For example, a read operation may be performed with respect to memory cells storing information associated with a reordering characteristic of memory cells of the payload area 411 related.

At operation S440, program data may be acquired using a plurality of check voltages based on a readout result of memory cells of the test data area 413 have different levels, in memory cells of the payload area 411 get saved.

How to relate to the 25 and 26 10, a reordering characteristic of memory cells may be detected by testing, and information indicating the reordering characteristic may be included in the test data area 413 be programmed. Testing may occur as part of a manufacturing process (eg, prior to packaging the storage device or after packaging the storage device, however, prior to determining packaging damage or before sending it to a third party after packaging). Otherwise or in addition, testing may be performed as a background operation, e.g. B. when the storage device is not accessed. For example, blocks in a NAND flash memory device (eg, free blocks) may have test data written into physical pages of the blocks, which are then read out with state reads to determine reordering characteristics of physical page memory cells. Test data may be stored for each memory cell, or it may be stored for a group of memory cells (eg, for all memory cells within a particular physical domain). A programming operation on the user data area 411 may be performed in terms of rearrangement based on information associated with the reordering characteristic present in the test data area 413 programmed, are related.

27 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment. With reference to the 25 and 27 At step S510, first data may be received and programmed into first memory cells connected to a first wordline.

In operation S520, second data may be received and programmed into second memory cells connected to a second wordline adjacent to the first wordline connected to the first memory cells.

The process S530 may perform state reading on program states from the data programmed in the first memory cells using a plurality of state read voltages. The state reading may be similar to that in relation to 12 . 22A described or with respect to others described herein.

At operation S540, third data may be received and programmed using a plurality of verify voltages for each program state (or for one or less than all program states) in the first memory cells connected to the first wordline. The resulting program states may represent the combination of first and third data. For example, the first data may be LSB data and 2SB data leading to program states E, OP1, OP2, and OP3, as in FIG 22A after programming at operation S510 is shown. The third data can be MSB Being data and programming in operation S540 may result in program states E and P1 through P7, as in 22A is shown (rough programming, relating to 22A described, may or may not be performed). In operation S540, in the selection of the verify voltage for each memory cell, both the result of the state read operation in operation S530 and the second data programmed in the second memory cells may be considered. The second data may either be read out of the second wordline prior to step S540, or may remain in page buffer flip-flops such as the reordering flip-flop RL upon operation of the second data in the second memory cells at operation S520. Second data of the second word line may be used when determining a verify voltage used for programming the third data in the memory cells of the first word line. For example, a check voltage for programming a particular memory cell of the first memory cells with third data may be decided at step S540 according to a difference between the threshold voltage of the particular memory cell after programming first data into the particular memory cell and threshold voltages of one or more second memory cells adjacent to the particular memory cell. Otherwise, or in addition, a check voltage for programming a particular memory cell of the first memory cells with third data may be decided in step S540 according to an increase in the threshold voltage of an adjacent second memory cell (or increase of threshold voltages of a plurality of adjacent memory cells) after programming the first data in FIG the first memory cells in operation S510 is caused by programming the second data into the second memory cells in operation S520.

Charges may be trapped on information storage films of the particular memory cell when programming the first program data. Charges that are trapped on certain memory cells may be affected by an electric field of charges trapped on adjacent memory cells. Rearrangement of charges trapped at the particular memory cell may be affected by the electric field. When a difference between a threshold voltage of the particular memory cell and threshold voltages of the adjacent memory cells becomes large, the strength of the electric field may become strong. That is, an impact on the adjacent second memory cell of rearrangement may increase. In addition, the adjacent second memory cell may affect a Vth level of the particular memory cell through other mechanisms, such as a parasitic coupling due to an increase in the Vth of the second memory cell from the programming of the second memory cell at step S520. Thus, a Vth change of the particular memory cell (eg, a first memory cell of the first word line) may be considered as a Vth change due to reordering characteristics of the particular memory cell and as a Vth change due to various influences of (an) adjacent memory cell (FIG. n) (such as a Vth difference and / or a Vth change of the second memory cell due to subsequent programming after programming the first data on operation 510 ). By analyzing a Vth change and / or a Vth difference of an adjacent second memory cell (or of several adjacent second memory cells) with the particular memory cell, an estimate of the influence of the second memory cell on the Vth variation of the particular memory cell after programming can be made of the first data and removed as a factor of results of the state reading in operation S530 to determine reorder characteristics of the particular memory cell. If the estimated change in the influence of the adjacent memory cells is consistent with a Vth change determined from the state read in operation S530, the particular memory cell may be designated as a normal memory cell, and a normal verify voltage may be used in the subsequent program operation S540 (FIG. in the checking substep of one or more program loops). If the estimated change from the influence of the adjacent memory cells does not detect a Vth change determined from the state read in operation S530 (eg, a Vth of an upper end portion or a lower end portion of a program state), in the subsequent program operation S540 may use a different verify voltage than the normal verify voltage (eg, a lower end memory cell upper cell verify voltage and a lower end memory cell verify voltage in the one or more program loop verify sub-step). In addition, an estimated change in the influence of the adjacent memory cells may be determined to counteract a Vth change in the reordering. In this case, the particular Vth change of reordering may be used to select a verification voltage for use in future programming, even if no or no significant Vth change from an execution of the state reading appears obvious at step S530. A programming of third data in operation S540 may be made in consideration of rearrangement in accordance with the determined (or predicted) reordering characteristics as described with respect to FIG 13 and 14 is described.

In one embodiment, a lower state read voltage VSRL, a normal state read voltage VSRN, and an upper state read voltage VSRU may be generated and output from a nonvolatile memory device 400 in 25 used when programming a 27 is performed.

28 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment. With reference to the 25 and 28 At operation S610, first program data to be programmed into first memory cells of a first word line may be received. The first program data can be stored in data flip-flops DL.

At operation S620, second program data to be stored in second memory cells connected to a second word line adjacent to a word line connected to the first memory cells may be received. The second program data may also include, in addition to the second word line, data from one or more other word lines adjacent to the first word line. The second program data may be data to be programmed after the first program data is programmed in the first word line. The second data may be stored in data flip-flops DL or in reordering flip-flops RL.

At operation S630, the first program data may be programmed in the first memory cells using a plurality of verify voltages having different levels based on the second program data. Memory cells programmed with the first program data may undergo a threshold voltage change that may be caused by charge reassembly or may be caused by other parasitic influences, may be caused by electric field effects, and / or other factors when the second program data be programmed. Thus, it is possible to increase the data reliability of the nonvolatile memory device 400 considering an effect on a Vth caused by data to be subsequently programmed in adjacent memory cells. As will be understood herein, predicting the effect of subsequently programmed adjacent memory cells on a Vth change of the first memory cells may be the only factor for selecting one of the plurality of verify voltages for each program state, or it may be one of several factors. For example, other factors may also be used to select one of several verify voltages, such as: For example, performing a state read of a previous program and / or deletion states (eg, as in relation to FIGS 12 and 22A and / or prior to programming of adjacent memory cells (eg, as described with respect to FIG 27 is described).

In one embodiment, a bottom state blank voltage VSRL and a normal state read voltage VSRN and a top state read voltage VSRU may be generated and output from a nonvolatile memory device 400 out 25 used when programming a 28 is performed.

29 FIG. 10 is a flowchart illustrating a programming method according to yet another embodiment. Regarding 29 At operation S810, program data to be programmed in memory cells may be received. For example, LSB data may be received as program data, two SB data may be received as program data, MSB data may be received as program data, and so on.

At operation S820, the data may be loaded on data flip-flops DL (see FIG. 1 ). Bit lines BL may be taken in the data flip-flops DL according to the program data.

At operation S830, a program loop may be executed in which a program voltage and a verify voltage are applied. For example, at operation S830, a program voltage may be applied once to a selected wordline, and thereafter a verify voltage may be applied once to the selected wordline. Every time process 830 is performed, only a check voltage (with a check voltage) can be performed.

At operation S840, it may be judged whether a threshold condition is satisfied. A threshold condition may, for. May be a number of program loops in which the process S830 is performed. If a loop count is above a certain value, the threshold condition may be met. Additionally or otherwise, a threshold condition may include a first program pass. When the first time is detected, that any of Memory cells undergo programming (as determined by the verify operation of operation S830), the threshold determination may be satisfied. The threshold determination can be fulfilled by a certain number of program runs of the memory cells. If the number of memory cells detected to have undergone programming (as determined by the verify operation of S830) is above a certain value, the threshold determination may be satisfied. Various conditions other than threshold condition can be used. If the threshold condition is satisfied, the method continues at operation S850. If the threshold condition is not satisfied, the process returns and repeats operation S830. In this case, a programming voltage can be increased.

If the threshold condition is satisfied, the method continues at operation S850. At operation S850, a state read operation to memory cells that have been programmed (memory cells whose threshold voltages are matched) may be performed using a plurality of state read voltages. Between steps S830 and S850, a delay time may be provided to provide sufficient time for charge reassembly. See for example U.S. Patent No. 7,813,183 in view of providing an exemplary delay time between application of a programming pulse (or erase voltage) and a subsequent readout or verify operation, the contents of which are incorporated herein by reference. When a program loop is executed, a program voltage may be applied once in operation S860, while a plurality of check voltages each having different levels may be applied to check programming of different memory cells having different check levels (eg, as shown in FIG in relation to other embodiments described herein). Which memory cells are checked by which of the plurality of verify voltages can be determined in accordance with a state read result, as discussed elsewhere herein. Otherwise, other factors described here, such as. B. adjacent memory cells, as with respect to the 27 and 28 may be used in addition to or instead of the state read of S850 to determine which of the plurality of verify voltages should be used for a particular memory cell of the memory cells to be programmed. The programming voltage applied across the memory cells to be programmed at operation S860 may be in accordance with the programming voltages applied to the memory cells to be programmed at operation S830 (eg, the same programming voltage, or a new program voltage, which is increased in the same way as between subsequent program voltages of operation S830). Otherwise, the programming voltage applied across the memory cells to be programmed in operation S860 may be a soft program voltage that is less than one that might otherwise have been applied in a subsequent operation S830. See, for example, B. US Patent Publication 2012/010374 , which is incorporated herein by reference for the sake of exemplary soft programming of the memory cells, as well as other exemplary programming features. For example, the US Patent Publication 2012/010374 also rechecking a cell that has already been determined to be programmed, and applying (a) programming voltage (s) to that cell if such a check fails, which can also be used by the method and apparatus described herein.

At operation S870, a program run can be judged. The process can be ended with a program run. In the event of a program error, the method returns and repeats the process S860. At this time, a programming voltage can be raised. Although not in 29 shown, the method may end after a certain number of bugs, and it may be determined that an error such. As a defective memory exists. The procedure of 29 can be performed without interruption by other side-by-side programming of those memory cells that receive programming data at operation S810. If the procedure off 29 is applied to a word line (ie, the program data received at operation S810 is for a selected word line), the method may be off 29 without interrupting programming of adjacent word lines.

30A FIG. 10 is a timing diagram illustrating voltages applied to selected word lines according to a programming method in FIG 29 be created. 30B FIG. 15 is a graph showing a deviation of a threshold voltage distribution of memory cells according to a programming method in FIG 29 as well as a way of applying a voltage in 30A represents.

With reference to the 30A and 30B For example, during execution of each of the plurality of program loops, a program voltage VPGM may be applied once to the word line to which the memory cells are connected, and a verify voltage VFY1 may be applied once to check the programming of the memory cells. The programming voltage VPGM can be increased with each repetition of these program loops. When the program loop is repeated, threshold voltages of programmed memory cells may be increased from an erase state E or from a program state resulting from a previous program operation (to the 29 and 30A not shown). Memory cells with increased threshold voltages (or memory cells that have been programmed) may have a middle state IS.

If a threshold determination is satisfied, a state read operation can be performed. A state read operation may be performed with respect to memory cells having a middle state IS. The state read operation may be performed by applying a normal state read voltage VSRN and an upper state read voltage VSRU to the memory cells having the middle state. The normal state read voltage VSRN may have a higher level than the upper state read voltage VSRU. The upper state read voltage VSRU may have a level equal to the verify voltage VFY1. The state read operation may be performed as described herein with respect to other embodiments.

If the state read operation is performed, upper-end memory cells LP_U, normal memory cells LP_N, and lower-end memory cells LP_L may be discriminated. In certain memory devices (eg, those with very small memory cells), charge reassembly or other factors causing a threshold change may occur in a short period of time. Thus, rearrangement may occur and / or substantially reflect reordering characteristics of the memory cell between program loops during programming. If a state read operation is performed when a threshold condition is satisfied, upper-end memory cells LP_U, normal memory cells LP_N, and lower-end memory cells LP_L may be discriminated. Here, threshold voltages of the upper-end memory cells LP_U may be increased due to the rearrangement, threshold voltages of the normal memory cells LP_N may not deviate significantly although the rearrangement is generated, and threshold voltages of the lower-end memory cells LP_L may be lowered due to the rearrangement.

Thereafter, a program loop may be performed that takes into account detected reordering characteristics of the memory cells. The upper-end memory cells LP_U may be programmed using a low verify voltage VFYL, the normal memory cells LP_N may be programmed using a normal verify voltage VFYN, and the lower-end memory cells LP_L may be programmed using an upper verify voltage VFYU. Memory cells having the middle state IS can be programmed by programming in a program state LP. When a reordering operation is performed, a threshold voltage distribution of the memory cells may become narrow when the reordering is generated.

In an alternative embodiment, a state read result may be stored in a supplemental area of a memory cell array so that it can be read out if necessary. A state read result may be output to an external device. If a reordering characteristic of the memory cells is stored in advance in a test area or a supplementary area of a memory cell array, a programming operation may be performed based on the reordering characteristic read out from the test area without the state read operation of operation S850.

31 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 represents according to another embodiment. An equivalent circuit, BLKa2 in 31 can be different from those in 7 differ in that lateral transistors are added in each row of cells.

With reference to the 3 to 6 and 31 For example, lateral transistors LTR may be connected between a ground selection transistor GST and a common source line CSL in each cell row. The gates of the lateral transistors LTR in each cell row can be connected together with a gate (or control gate) of a ground selection transistor GST to a ground selection line GSL.

channel layers 114 may serve as vertical bodies of a first conductive material CM 1. That is, the first conductive materials CM1 may be used together with the channel layers 114 form vertical transistors. The first conductive materials CM1 may be used together with the channel layers 114 vertically to a substrate 111 form extending ground selection transistors GST.

Store movies 116 can be between the substrate 111 and the first conductive materials CM1. The substrate 111 may serve as a horizontal body of the first conductive materials CM1. That is, the first conductive materials CM1 may be used together with the substrate 111 form the lateral transistors LTR.

When a voltage is applied to the first conductive materials CM1, an electric field may be interposed between the first conductive materials CM1 and the channel layers 114 be formed. The electric field may allow for the channel layers 114 Channels are formed. When a voltage is applied to the first conductive materials CM1, between the first conductive materials CM1 and the substrate 111 an electric field are formed. The electric field may allow for on the substrate 111 Channels are formed. Channels attached to the substrate 111 can be formed with common source sections CSR and the channel layers 114 be connected. When a voltage is applied to the ground select line GSL, the ground select transistors GST and the lateral transistors LTR can be turned on. This may allow the cell rows CS11, CS12, CS21 and CS22 to be connected to a common source line CSL.

32 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view of a 3 according to yet another embodiment. An equivalent circuit BLKa3 in FIG 32 can be different from those in 7 in that ground select transistors GST are connected to first and second ground select lines GSL1 and GSL2. With reference to the 3 to 6 and 32 For example, first conductive materials CM1 may constitute first and second ground selection lines GSL1 and GSL2.

As for the 1 to 28 described, reordering characteristics of the memory cells MC1 to MC6 can be detected by reading out (or predicting). As for the 1 to 28 described, the memory cells MC1 to MC8 can be programmed with respect to the detected (or predicted) reordering characteristics.

As for 31 Lateral transistors LTR may be provided on the equivalent circuit BLKa3.

33 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment. With reference to the 3 to 6 and 33 a plurality of sub-blocks is provided. In this embodiment, second and third conductive materials CM2 and CM3 may constitute first and second memory cells MC1 and MC2 used as a first sub-block. Sixth and seventh conductive materials CM6 and CM7 may form third and fourth memory cells MC3 and MC4 used as a second sub-block. Fourth and fifth conductive materials CM4 and CM5 may form first and second dummy memory cells (dummies) DMC1 and DMC2 provided between the first and second sub-blocks. The first and second sub-blocks can be independently programmed, read and deleted.

As for the 1 to 28 described, reordering characteristics of the memory cells MC1 to MC4 can be detected (or predicted) by readout. As for the 1 to 28 described, the memory cells MC1 to MC4 can be programmed with respect to the detected (or predicted) reordering characteristics.

As with respect to 31 Lateral transistors LTR may be provided on the equivalent circuit BLKa3.

34 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment. With reference to the 3 to 6 and 34 For example, first and second conductive materials CM1 and CM2 may form ground selection transistors GSTa and GSTb, each having first and second levels. Seventh and eighth conductive materials CM7 and CM8 may constitute row selection transistors SSTa and SSTb each having a seventh and an eighth height. Third to sixth conductive materials CM3 to CM6 may constitute first to fourth memory cells MC1 to MC4.

The first and second conductive materials CM1 and CM2 may be commonly connected to form a grounding lead GSL. Cell lines CS11, CS12, CS21 and CS22 may be commonly connected to a row select line GSL.

The cell rows CS11 and CS12 may be connected to two row selection lines SSL1a and SSL1b, each having a seventh and eighth height, formed by seventh and eighth conductive materials CM7 and CM8. The cell lines CS21 and CS22 may be connected to two row selection lines SSL2a and SSL2b each having the seventh and eighth levels formed by the seventh and eighth conductive materials CM7 and CM8.

Conductive materials, each corresponding to at least three heights, may form row select transistors. Conductive materials, each corresponding to at least three heights, may form row select transistors.

As for the 1 to 28 described, reordering characteristics of the memory cells MC1 to MC4 can be detected by reading (or predicting). As for the 1 to 28 described, the memory cells MC1 to MC4 can be programmed with respect to the detected (or predicted) reordering characteristics.

As with an equivalent circuit BLKa2, with respect to 31 Lateral transistors LTR may be provided on the equivalent circuit BLKa5. As with an equivalent circuit BLKa3 with respect to 32 cell rows CS11 and CS12 may be connected to a ground select line (not shown), and cell rows CS21 and CS22 may be connected to another ground select line (not shown). As with an equivalent circuit BLKa4 with respect to 33 is described, memory cells MC1 to MC4 may form a plurality of sub-blocks.

35 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment. An equivalent circuit BLKa6 in FIG 35 can be different from those in 34 in that row select transistors SSTa and SSTb in cell rows of the same row share a row select line. Row select transistors SSTa and SSTb in cell rows CS11 and CS12 may be commonly connected to a first row select line SSL1, and row select transistors SSTa and SSTb in cell rows CS21 and CS22 may be commonly connected to a second row select line SSL2.

As for the 1 to 28 described, reordering characteristics of the memory cells MC1 to MC4 can be detected by reading (or predicting). As for the 1 to 28 described, the memory cells MC1 to MC4 can be programmed with respect to the detected (or predicted) reordering characteristics.

As with an equivalent circuit BLKa2 with respect to 31 Lateral transistors LTR may be provided on the equivalent circuit BLKa6. As with an equivalent circuit BLKa3 with respect to 32 cell rows CS11 and CS12 may be connected to a ground select line (not shown), and cell rows CS21 and CS22 may be connected to another ground select line (not shown). As with an equivalent circuit BLKa4 with respect to 33 is described, memory cells MC1 to MC4 may form a plurality of sub-blocks.

36 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 3 according to yet another embodiment. Regarding the 3 to 6 and 36 For example, second conductive materials CM2 may form first dummy memory cells DMC1, and seventh conductive materials CM7 may form second dummy memory cells DMC2.

In one embodiment, conductive materials corresponding to two or more heights may form dummy memory cells (not shown) disposed between memory cells and ground selection transistors GST. Conductive materials corresponding to two or more heights may form dummy memory cells (not shown) disposed between memory cells and row selection transistors SST. Blind memory cells (not shown) may be arranged adjacent to any of the ground and row select transistors GST and SST. As with respect to FIGS 1 to 28 described, reordering characteristics of memory cells MC1 to MC4 can be detected (or predicted) by readout. As for the 1 to 28 described, the memory cells MC1 to MC4 can be programmed with respect to the detected (or predicted) reordering characteristics.

Similar to an equivalent BLKa2 in terms of 31 Lateral transistors LTR may be provided on the equivalent circuit BLKa7. As for an equivalent circuit like BLKa3 in terms of 32 cell rows CS11 and CS12 may be connected to a ground select line (not shown), and cell rows CS21 and CS22 may be connected to another ground select line (not shown). As with an equivalent circuit BLKa4 with respect to 33 is described, memory cells MC1 to MC4 may form a plurality of sub-blocks.

As for 34 described, conductive materials of two or more heights may form row selection transistors SSTa and SSTb. Conductive materials of two or more heights may constitute ground selection transistors GSTa and GSTb. As for 35 Row select transistors SSTa and SSTb of the same row may be connected to a row select line SSL1 or SSL2.

37 is a perspective view along a line IV-IV 'on 3 according to another embodiment. 38 is a cross-sectional view taken along a line IV-IV 'in 3 according to another embodiment. Regarding the 3 . 37 and 38 can first store information movies 116a be provided under the conductive materials CM1 to CM8 and insulation materials 112 and 112a , and supports PL and second information storage films 116b can be provided on the inside of the supports PL.

The first information storage movies 116a may block insulating films such as third sub-insulation films 119 include (compare 4 and 5 ). The first information storage movies 116 can be at the same location as information storage movies 116 that in the 4 and 5 are shown, are formed. The second information storage films 116b For example, charge trapping films and tunnel insulating films such as first and second sub-insulation films may be used 117 and 118 include.

An equivalent circuit of a memory block relating to 3 . 37 and 38 may be one of the above-described equivalent circuits BLKa1 to BLKa7.

39 is a perspective view taken along a line IV-IV 'in 3 according to another embodiment. 40 is a cross-sectional view taken along a line IV-IV 'in 3 according to yet another embodiment. Regarding the 3 . 39 and 40 Lower Supported PLa and upper supports PLb may be provided to move in a direction perpendicular to a substrate 111 to be stacked on top of each other.

The lower supports PLa can use the insulation films 112 and 112a penetrate along a third direction to connect with the substrate 111 to be in contact. Each of the lower pillars PLa may have a lower channel layer 114a and a lower inner material 115a include. The lower channel layers 114a may comprise a semiconductor material which is the same conductive type as the substrate 111 or an intrinsic semiconductor. The lower channel layers 114 may each serve as vertical bodies of the first to fourth conductive materials CM1 and CM4. The lower inner materials 115a may include an insulating material.

The upper pillars PLb may be respectively provided on the lower pillars PLa. The upper supports PLb can use the insulation films 112 penetrate along a third direction to be in contact with an upper surface of the lower support PLa. Each of the upper supports PLb may have an upper channel layer 114b and an upper inner material 115b include. The upper channel layers 114b may comprise a semiconductor material of the same conductive type as the lower channel layers 114a or an intrinsic semiconductor.

The upper channel layers 114b may each serve as vertical bodies of the fifth to eighth conductive materials CM5 and CM8. The upper inner materials 115b may include an insulating material.

The lower channel layers 114a and the upper channel layers 114b may be interconnected to serve as a vertical body. For example, semiconductor pads SP can be provided on the lower supports PLa. The semiconductor pads SP may comprise a semiconductor material having the same conductive type as the lower channel layers 114a or an intrinsic semiconductor. The lower channel layers 114a and the upper channel layers 114b can be connected via the semiconductor pads SP between.

In this embodiment, conductive materials among the first to eighth conductive materials CM1 to CM8 adjacent to the semiconductor pads SP may form dummy word lines and dummy memory cells (dummies). For example, the fourth conductive material CM4 adjacent to the semiconductor pads SP, the fifth conductive material CM5 or the fourth and fifth conductive materials CM4 and CM5 may be dummy word lines and dummy memory cells.

An equivalent circuit of a memory block relating to 3 . 39 and 40 may be identical to the above-described equivalent circuits BLKa1 to BLKa7.

41 is a perspective view taken along a line IV-IV 'in 3 according to yet another embodiment. 42 is a cross-sectional view taken along a line IV-IV 'in 3 according to yet another embodiment. Regarding the 3 . 41 and 42 lower supports PLa and upper supports PLb may be provided (cf. 39 and 40 ). First information storage films 116a may be provided under the conductive materials CM1 to CM8, and insulation materials 112 and 112a , Supports PLa and PLb and second information storage films 116 may be provided on inner sides of the supported PLa and PLb (cf. 37 and 38 ).

An equivalent circuit of a memory block relating to 3 . 41 and 42 can be identical to one of the above-described equivalent circuits BLKa1 to BLKa7.

43 is a plan view showing a memory block in FIG 2 represents according to another embodiment. 44 is a perspective view taken along a line XXXXIV-XXXXIV 'in 43 , 45 is a cross-sectional view along a line XXXXIV-XXXXIV 'in 43 ,

In comparison with a memory block BLKa, in relation to the 3 to 6 a line select line cutout SSL Cut and a word line cutout WL Cut extending along a first direction may be provided in turn in a second direction. The word line cutout WL Cut can be formed by the conductive materials CM to CM8 and insulation material 112 and 112a penetrate to expose portions of the common source sections CSR. The line selection line cutout SSL Cut may be formed by one or more conductive materials (eg, CM8) and isolation materials 112 penetrate. The row select line section SSL Cut may separate an eighth conductive line CM8 that configures line select transistors SST. When conductive lines of the two or more highs form row select transistors SST, the SSL cut line select section may separate conductive materials of the two or more highs.

Part of a top view EC 43 may be identical to one of the above-described equivalent circuits BLKa1 to BLKa7.

In this embodiment, pillars PL may be formed of lower pillars and upper pillars, as in FIGS 39 and 40 is described.

In one embodiment, first information storage films 116a and second information storage films 116b be provided, as regards the 37 and 38 is described.

46 is a plan view that forms part of a memory block in FIG 2 according to yet another embodiment. 47 is a perspective view along a line XXXXVII-XXXXVII 'in 46 , 48 is a cross-sectional view along a line XXXXVII-XXXXVII 'in 46 ,

In comparison with a memory block BLKa inserted in the 3 to 6 described, supports provided between adjacent common source portions may be arranged in a zigzag shape along a first direction.

As in the 39 and 40 supports PL can be formed of lower supports and upper supports. As in the 37 to 38 described, first information storage films 116a and second information storage films 116b be provided. As for the 43 to 45 described, a line selection line section SSL cut may be provided. A line of the columns arranged in a zigzag along the first direction may be provided between a word line, row selection line cutouts WL Cut, and an SSL Cut adjacent to each other.

A part EC of a top view in 46 may correspond to one of the above-described equivalent circuits BLKa1 to BLKa7.

49 is a plan view that forms part of a memory block in FIG 2 according to yet another embodiment. 50 is a perspective view taken along a line XXXXX-XXXXX 'in 49 , A cross-sectional view along a line XXXXX-XXXXX 'in 49 can with those in 5 be identical and a description of the same is omitted.

In comparison with a memory block BLKa inserted in the 3 to 6 a memory block BLKd may comprise quadrangular pillars PL. Insulation materials IM can be provided between the supports PL. The pillars PL may be arranged aligned along a first direction between adjacent common source sections CSR. The insulating materials IM may extend along the third direction to connect to a substrate 111 stay in contact.

Each of the pillars PL may have a channel layer 114 and an inner material 115 include. For example, the channel layer 114 be provided under four sides of a corresponding support on two sides which are adjacent to conductive material CM1 to CM8, without surrounding the corresponding support.

A channel layer on one side of each support may be used together with conductive materials CM1 to CM8 and information storage films 116 form a cell row. A channel layer on the other side of each pillar may be used together with conductive materials CM1 to CM8 and information storage films 116 form another cell row. That is, a column can be used to form two rows of cells.

In one embodiment, pillars PL may be formed of lower pillars and upper pillars, as in FIGS 39 and 40 is described. As in the 37 and 38 described, first information storage films 116a and second information storage films 116b be provided. As for the 43 to 45 described, a line selection line section SSL cut may be provided. One of the pillars PL arranged in a zigzag along a first direction may be provided between a word line cutout WL Cut and a line selection line cutout SSL Cut arranged adjacent to each other.

A part EC of a top view in 49 corresponds to one of the above-described equivalent circuits BLKa1 to BLKa7.

51 is a plan view that forms part of a memory block in FIG 2 according to yet another embodiment. 52 is a perspective view along a line XXXXXII-XXXXXII 'in 51 , 53 is a cross-sectional view along a line XXXXXII-XXXXXII 'in 51 ,

Regarding the 51 to 53 For example, the first to eighth conductive materials CMU1 to CMU8 extending along a first direction may be formed on a substrate 111 be provided. The first to fourth upper conductive materials CMU1 to CMU4 may be in a direction perpendicular to the substrate 111 be stacked and spaced apart in a direction perpendicular to the substrate. The fifth to eighth conductive materials CMU5 to CMU8 may be in a direction perpendicular to the substrate 111 be stacked and in a direction perpendicular to the substrate 111 be spaced apart. A group of the first to fourth upper conductive materials CMU1 to CMU4 may be spaced apart from a group of the fifth to eighth upper conductive materials CMU5 to CMU8 along a second direction.

Lower conductive materials CMD1a, CMD1b and CMD2 to CMD4 extending along the first direction may be provided between the first to fourth upper conductive materials CMU1 to CMU4 and the fifth to eighth conductive materials CMU5 to CMU8. The lower conductive materials CMD2 to CMD4 may be stacked in a direction perpendicular to the substrate and spaced apart in a direction perpendicular to the substrate. The lower conductive materials CMD1a and CMD1b may be provided on the lower conductive material CMD2. The lower conductive materials CMD1a and CMD1b may be spaced apart along the second direction.

A plurality of upper pillars PLU may be configured to have the first to fourth upper conductive materials CMU1 to CMU4 or the fifth to eighth upper conductive materials CMU5 to CMU8 in a direction perpendicular to the substrate 111 to penetrate. The upper supports PLU can work with the substrate 111 stay in contact. In the first upper conductive material CMU1, the upper pillars may be arranged in a line along the first direction and spaced apart along the first direction. In the eighth upper conductive material CMU8, the upper pillars may be arranged in a line along the first direction and spaced apart along the first line.

Each of the upper pillars PLU includes an information storage film 116 and a channel layer 114 , The information storage movie 116 can store information by trapping or repelling charges. The information storage movie 116 may include a tunnel insulating film, a charge trapping film and a blocking insulating film.

The channel layers 114 can serve as vertical bodies of the upper supports PLU. The channel layers 114 each may comprise an intrinsic semiconductor. The channel layers 114 For example, semiconductors of the same conductive type (eg, p-type) as the substrate 111 include.

A plurality of lower pillars PLD may be formed. The plurality of lower pillars PLD may include the lower conductive materials CMD2 to CMD4 and the lower conductive materials CMD1a or CMD1b in a direction perpendicular to the substrate 111 penetrate, so that they are with the substrate 111 stay in contact. In the lower conductive material CMD1a, lower pillars may be arranged in a line along the first direction and spaced from each other along the first direction. In the lower conductive materials CMD1b, lower pillars may be arranged in a line along the first direction and spaced apart along the first direction.

Each of the lower supports PLD may be an information storage film 116 and a channel layer 114 include. The information storage movie 116 can store information by trapping or repelling charges. The information storage movie 116 may include a tunnel insulating film, a charge trapping film and a blocking insulating film.

The channel layers 114 can serve as vertical bodies of the lower supports PLD. The channel layers 114 each may include its own semiconductor. The channel layers 114 For example, semiconductors of the same conductive type (eg, p-type) as the substrate 111 include.

On the substrate, a plurality of pipe contacts PC may be provided. The piping contacts PC may extend in a bit line direction so as to connect lower surfaces of upper pillars PLU formed on the first upper conductive material CMU1 to lower surfaces of the lower pillars PLD formed on the lower conductive material CMD1a. The piping contacts PC may extend in a bit line direction to connect lower surfaces of upper pillars PLU formed on the eighth upper conductive material CMU8 to lower surfaces of the lower pillars PLD formed on the lower conductive material CMD1b.

In this embodiment, each of the piping contacts PC may have a channel layer 114 and an information storage movie 116 include. The channel layers 114 the piping contacts PC can the channel layers 114 the upper supports PLU and interconnect channel layers of the lower supports PLD. The information storage films 116 the piping contacts PC, the information storage films 116 the upper supports PLU and the information storage films 116 Interconnect the lower support PLD.

A common source section CSR extending along the first direction may be provided on the lower pillars PLD. The common source portion may extend along a first direction to connect to the plurality of bottom pillars PLD. The common source section CSR may form a common source line CSL. The common source portion CSR may comprise a metallic material. The common source portion CSR may have a conductive type extending from the substrate 111 different.

The shafts 320 can be provided on the upper supports PLU. The shafts 320 For example, a semiconductor material may include a conductive type (eg, n-type) extending from the substrate 111 different. At the shafts 320 For example, bit lines BL may be formed. The bit lines BL may be spaced apart along the first direction. The bit lines BL may extend along the second direction so that they connect to the wells 320 are connected.

In this embodiment, the bit lines BL and the slots 320 be connected via contact plug, and the common source section CSR and the lower supports PLD can be connected to each other via contact plugs.

A cell row may be formed of a lower support and an upper support, which are connected to each other via a pipe contact.

In an exemplary embodiment incorporated in the 43 and 45 is described, the upper pillars PLU and the lower pillars PLD may be arranged in a zigzag shape along the first direction.

A part EC of a top view in 51 may correspond to one of the above-described equivalent circuits BLKa1 to BLKa7.

54 is a plan view that forms part of a memory block in FIG 2 according to yet another embodiment. 55 is a perspective view taken along a line XXXXXV-XXXXXV 'in 54 , 56 is a cross-sectional view along a line XXXXXV-XXXXXV 'in 54 ,

Regarding the 54 to 56 may be a common source CSR on a substrate 111 be educated. The common source section CSR may be formed, for example, at a doping section. The common source section CSR may form a common source line CSL.

First to eighth conductive materials CM1 to CM8 may be formed at the common source portions CSR. The first to eighth conductive materials CM1 to CM8 may be in a direction perpendicular to the substrate 111 be stacked and in a direction perpendicular to the substrate 111 be spaced apart. Among the first to eighth conductive materials CM1 to CM8, conductive materials constituting row selection transistors SST may be separated by row selection line sections SSL Cut. The row select line segments SSL Cut may extend along a first direction and be spaced along a second direction. The remaining conductive materials (which are not used for the row selection transistors) may be formed on the common source portion CSR to have a plate shape extending along the first and second directions.

For example, the first to seventh conductive lines CM1 to CM7 may have a plate shape, and the eighth conductive materials CM8 may be separated by the line selection line cutouts SSL Cut. The eighth conductive materials CM8 may extend along the first direction and be spaced along the second direction.

A plurality of pillars PL may be provided to cover the first to eighth conductive materials CM1 to CM8 in a direction perpendicular to the substrate 111 penetrate and with the substrate 111 stay in contact. In one of the eighth conductive materials CM8, pillars PL may be provided in a line along the first direction. Each of the pillars PL may be an information storage film 116 , a channel layer 114 and an inner material 115 include.

The information storage films 116 can store information by trapping or repelling charges. The information storage films 116 For example, a tunnel insulating film may include a charge trapping film and a blocking insulating film. The channel layers 114 can serve as vertical bodies of the supports PL. The channel layers 114 may include intrinsic semiconductors. The channel layers 114 For example, a semiconductor material of the same type (eg, p-type) as the substrate 111 include. The inner materials 115 may include an insulating material or an air gap.

In one embodiment, pillars PL may be formed of upper pillars and lower pillars, as in FIGS 39 and 40 is described. As in the 43 to 45, the pillars PL may be arranged in a zigzag shape along the first direction.

57 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC from a plan view in FIG 54 according to one embodiment. Regarding the 54 to 57 For example, a common source section CSR may be provided between supports PL and a substrate 111 be educated.

channel layers 114 may be of a p-type, and the common source section CSR may be an n-type. A subarea under the channel layers 114 which corresponds to ground selection transistors GST may be of p-type, and the common source section CSR may be of n-type. That is, the channel layer 114 and the common source section CSR may form a PN junction. As a result, diodes D formed of pillars PL and a common source line formed of the common source section CSR may be formed between the cell lines CS11, CS12, CS21 and CS22. An equivalent circuit BLKf1 in FIG 57 can with that out 7 be identical except for the diodes D provided therein.

The equivalent circuit BLKf1 can be used as well as the above-described equivalent circuits BLKa2 to BLKa7.

58 is a perspective view taken along a line XXXXXV-XXXXXV 'in 54 , 59 is a cross-sectional view along a line XXXXXV-XXXXXV 'in 54 ,

Regarding the 54 . 58 and 59 For example, conductive materials among the first to eighth conductive materials CM1 to CM8 forming ground selection transistors GST may extend along a first direction and be spaced apart along a second direction. The conductive materials constituting ground selection transistors GST may have the same structure as conductive materials constituting row selection transistors SST. For example, the first conductive materials CM1 may have the same structure as the eighth conductive materials CM8.

In one embodiment, in 39 and 40 supports PL can be formed of upper columns and lower columns. As in the 43 to 45 may be arranged PL columns in a zigzag shape along the first direction.

60 FIG. 12 is a circuit diagram showing an equivalent circuit of a part EC of a plan view in FIG 54 represents according to another embodiment.

Regarding the 54 and 58 to 60 For example, diodes D may be formed between cell rows CS11, CS12, CS21 and CS22 and a common source line CSL. The ground selection transistors GST may be connected to a plurality of ground selection lines GSL1 and GSL2. For example, the ground select transistors of the cell rows CS11 and CS12 may be connected to a first ground select line GSL1, and ground select transistors of the cell rows CS21 and CS22 may be connected to a second ground select line GSL2.

The equivalent circuit BLKf2 can be applied as well as the above-described equivalent circuits BLKa2 to BLKa7.

61 FIG. 10 is a block diagram illustrating a memory system according to an embodiment. FIG. Regarding 61 can be a storage system 1000 a nonvolatile storage device 1100 and a controller 1200 include.

The nonvolatile storage device 1100 may be substantially identical to that of the nonvolatile memory devices 100 to 500 according to the embodiments. Ie. the nonvolatile storage device 1100 may comprise a plurality of cell rows CS11, CS12, CS21 and CS22 disposed on a substrate 111 each comprising a plurality of cell transistors CT in a direction perpendicular to the substrate 111 are stacked. The nonvolatile storage device 1100 can perform a programming operation according to the programming method described above. The nonvolatile storage device 1100 may perform a state read operation to perform a charge reassembly programming operation in accordance with a state read result.

The controller 1200 can work with a host and the nonvolatile storage device 1100 be connected. In response to a request from the host, the controller may 1200 be designed to the non-volatile memory device 1100 access. For example, the controller 1200 to be configured to read, write, erase, state read, program in consideration of rearrangement, and background the nonvolatile memory device 1100 to control. The controller 1200 may be configured to interface between the non-volatile memory device 1100 and the host. The controller 1200 may be configured to a firmware for controlling the non-volatile memory device 1100 to drive.

The controller 1200 may be configured for the non-volatile memory device 1100 to provide a control signal CTRL, a command CMD and an address ADDR. In response to the control signal CTRL of the command CMD and the address ADDR supplied by the controller 1200 can be provided, the non-volatile memory device 1100 perform a read, a write, a state read, an erase, and a program in consideration of a charge reassembly.

In one embodiment, the controller 1200 further comprising components such as a processing unit, a host interface and a memory interface. The processing unit may be an overall process of the controller 1200 Taxes.

The host interface can use the protocol to perform a data exchange between the host and the controller 1200 include. For example, the host interface may communicate with an external device (eg, the host) via at least one of various protocols, e.g. A USB (Universal Serial Bus) protocol, an MMC (Multimedia Card) protocol, a PCI (Peripheral Component Interconnection) protocol, a PCI-E (PCI Express) protocol, an ATA (Advanced Technology Attachment) protocol, a Serial -ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol. The memory interface may interface with the nonvolatile memory device 1100 be. The memory interface may include a NAND interface or a NOR interface.

The storage system 1000 can work as a computer, a portable computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a PDA, a web tablet, a cordless phone, a mobile phone, a smartphone, an e-book, a PMP (portable multimedia player) , a digital camera, a digital audio recorder / player, a digital picture / video recorder / player, a portable game console, a navigation system, a black box, a three-dimensional television, a device capable of transmitting information under wireless conditions one of various electronic devices forming a home network, one of various electronic devices forming a computer network, one of various electronic devices forming a telematic network, RFID, or one of various electronic devices that form a computer system, be.

A non-volatile storage device 1100 or a storage system 1000 can be packaged in different types of packages, such as: For example, PoP (Package to Package), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDI2P), Waffle Pack, Die in Wafer Form , Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer Level Fabricated Package (WFP), Wafer Level Processed Stack Package (WSP), and the like.

62 FIG. 10 is a flowchart for describing a programming method of a memory system according to an embodiment. FIG. Regarding the 61 and 62 can be a controller 1200 at a process S1110, a program command and program data to a nonvolatile memory device 1100 send. At this time, addresses of memory cells in which the program data should be stored can be sent.

In operation S1120, the nonvolatile memory devices may 1100 perform a programming operation according to one of the programming methods according to the embodiments. For example, the non-volatile storage device 1100 perform a state read operation and can execute a program operation in accordance with a state read result. The nonvolatile storage device 1100 can perform a state read operation when program data is MSB data, and can execute a program operation according to a state read result. The nonvolatile storage device 1100 may perform a state read operation when program data is fine program data, and may perform a program operation according to a state read result. The nonvolatile storage device 1100 may store a state read result in a supplementary area, and may use the stored state read result if needed. The nonvolatile storage device 1100 can read out and use a state read result from a test data section, if needed. The nonvolatile storage device 1100 may capture (or predict) a reorder characteristic according to previously programmed data, and may program data to perform a program operation in accordance with a detected (or predicted) result. The nonvolatile storage device 1100 may capture (or predict) a reorder characteristic according to previously programmed data, program data, and data to be programmed next to perform a program operation in accordance with a detected (or predicted) result.

63 FIG. 10 is a flowchart for describing a state read method of a memory system according to an embodiment. FIG. With reference to the 61 and 63 can be a controller 1200 at operation S1210, a state read command to a non-volatile storage device 1100 send. At this time, addresses of memory cells at which a state read operation is to be executed may be sent.

At operation S1220, the nonvolatile memory device may 1100 perform a state read operation according to an embodiment (operations S151 to S155).

At operation S1230, the nonvolatile memory device 1100 a state read result to the controller 1200 send.

The controller 1200 can perform various operations of the nonvolatile memory device 1100 such as B. control a programming, a read-out and a deletion based on the transmitted state read result.

The controller 1200 can store previously stored data from the non-volatile memory device 1100 and receive program data and data to be programmed next from an external device, and may decide on levels of check voltages used in programming the program data to send them with the program data to the nonvolatile memory device.

64 is a block diagram illustrating an application of a memory system in FIG 61 represents. In relation to 64 can be a storage system 2000 a nonvolatile storage device 2100 and a controller 2200 include. The nonvolatile storage device 2100 may comprise a plurality of nonvolatile memory chips forming a plurality of groups. Nonvolatile memory chips in each group may be configured with the controller 2200 to communicate over a common channel. In one embodiment, the plurality of nonvolatile memory chips may communicate over a plurality of channels CH1 to CHk.

Each of the nonvolatile memory chips may be compatible with those of the nonvolatile memory devices 100 to 500 According to the embodiments, be substantially identical, ie the non-volatile memory device 2100 may comprise a plurality of cell rows CS11, CS12, CS21 and CS22 disposed on a substrate 111 each of which includes a plurality of cell transistors CT in a direction perpendicular to the substrate 111 are stacked. The nonvolatile storage device 2100 may perform a state read operation according to the embodiments, and may perform a program operation in consideration of rearrangement according to a state read result. The controller 2100 can the non-volatile storage device 2100 so that a state read operation and a program operation are performed according to the embodiments. The control device 2200 can the non-volatile storage device 2100 such that a state read operation is performed according to the embodiments, and it may perform operations of the nonvolatile memory device 3100 control according to a state read result.

In 64 For example, the case where a channel is connected to a plurality of nonvolatile memory chips is described. However, the storage system can 2000 be modified so that a channel is connected to a non-volatile memory chip.

65 FIG. 10 is a diagram illustrating a memory card according to an embodiment. FIG. Regarding 65 can the memory card 3000 a nonvolatile storage device 3100 , a controller 3200 and a connector 3300 include.

The nonvolatile storage device 3100 can with that of one of the non-volatile storage devices 100 to 500 be substantially identical according to the exemplary embodiments. That is, the nonvolatile storage device 3100 may comprise a plurality of cell rows CS11, CS12, CS21 and CS22 disposed on a substrate 111 each of which includes a plurality of cell transistors CT in a direction perpendicular to the substrate 111 are stacked. The nonvolatile storage device 3100 may perform a state read operation according to the embodiments, and may perform a program operation in consideration of rearrangement according to a state read result. The controller 3200 can the non-volatile storage device 3100 so that a state read operation and a program operation are performed according to the embodiments. The controller 3200 can the non-volatile storage device 3100 so that a state read operation is performed according to the embodiments, and it may control operations of the nonvolatile memory device 3100 control according to a state read result.

The connector 3300 can the memory card 3000 connect electrically to a host.

The memory card 3000 may be formed of memory cards, such as. A PC card (PCMCIA), a CF card, an SM (or SMC) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), a security card (SD, miniSD, microSD, SDHC) Universal Flash Storage (UFS) device, and the like.

66 FIG. 14 is a diagram showing a solid state drive according to an embodiment. FIG. In relation to 66 can be a solid state drive 4000 a plurality of nonvolatile memory devices 4100 , a controller 4200 and a connector 4300 include.

Each of the non-volatile memory devices 4100 can with that of one of the non-volatile memory devices 100 to 500 be substantially identical according to the exemplary embodiments. That is, each of the nonvolatile memory devices 4100 may comprise a plurality of cell rows CS11, CS12, CS21 and CS22 disposed on a substrate 111 each of which includes a plurality of cell transistors C extending in a direction perpendicular to the substrate 111 are stacked. The nonvolatile storage device 4100 may perform a state read operation according to the embodiments, and may perform a program operation in consideration of rearrangement according to a state read result. The controller 4200 can the non-volatile storage device 4100 so that a state read operation and a program operation are performed according to the embodiments. The controller 4200 can the non-volatile storage device 4100 so that a state read operation is performed according to the embodiments, and it may perform operations of the nonvolatile memory device 4100 control according to a state read result.

The connector 4300 can be the solid state drive 4000 connect electrically to a host.

67 FIG. 10 is a block diagram illustrating a calculation system according to an embodiment. FIG. In relation to 67 can be a calculation system 5000 a central processing unit 5100 , a ram 5200 , a user interface 5300 , a modem 5400 , a modem 5400 and a storage system 5600 include.

The storage system 5600 can with the elements 5100 to 5400 via a system bus 5500 be electrically connected. Data coming through the user interface 5300 be provided or by the central processing unit 5100 can be processed in the storage system 5600 get saved.

The storage system 5600 can be a non-volatile storage device 5610 and a controller 5620 include. The storage system 5600 can be from any of the storage systems 1000 and 2000 , a memory card 3000 or a solid state drive 4000 be formed according to the embodiments.

The above-mentioned subject matter is intended to be illustrative and not restrictive. It is intended that many alternative embodiments fall within the scope of the invention. For example, while the above embodiments are focused on a memory cell that stores data as a threshold voltage in a memory cell transistor, the application is equally applicable to other memory cell types, and the characteristics may represent data that is different. For example, a range of resistance values may represent a program state in a PRAM memory device, where multiple circumferences represent multiple program states. Other factors besides those described herein may affect the change in the storage device characteristic that represents data (eg, a change in the voltage threshold or resistance value). The appended claims are intended to cover all such modifications, improvements or embodiments that fall within the true spirit and scope. Thus, the scope is by the widest permissible Interpretation of the following claims and their equivalents to the maximum extent permitted by law, and should not be limited or limited by the foregoing detailed description.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• KR 1020110104753 [0001]
• US 5473563 [0221, 0221]
• US 2011/0222342 [0263]
• US 7813183 [0304]
• US 2012/010374 [0304, 0304]

Claims (20)

Method for programming a non-volatile memory ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) comprising: (a) determining a tendency to change a threshold voltage of a first memory cell transistor from a programming state; (b) selecting a first verify voltage from a plurality of verify voltages in response to the determination; and (c) programming the first memory cell transistor to change the threshold voltage of the first memory cell transistor, the programming comprising verifying that the threshold voltage of the first memory cell transistor has sufficiently changed using the first verify voltage, wherein step (a) of determining a A tendency to alter the threshold voltage of the first memory cell transistor comprises determining a change in the threshold voltage of the first memory cell transistor beyond a first circumference. The method of claim 1, further comprising: (d) programming the first memory cell transistor to change the threshold voltage of the first memory cell transistor within the first perimeter. The method of claim 2, wherein step (c) of programming comprises changing the threshold voltage of the first memory cell transistor to a second extent to represent at least a first bit of the data and a second bit of the data. The method of claim 3, wherein the first memory cell transistor is one of a plurality of memory transistors connected in series to form a NAND row of memory cell transistors, and wherein the step of checking the threshold value of the first memory cell transistor comprises applying the first verify voltage on a word line connected to the first memory cell transistor. Method according to claim 3, wherein the memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) comprises a word line and a second memory cell transistor, wherein the first memory cell transistor and the second memory cell transistor are connected to the word line, and the method further comprises: (e) determining a tendency to change a threshold voltage of the second memory cell transistor from a programmed state; and (f) selecting a second verify voltage different from the first verify voltage from a plurality of verify voltages in response to the determination, wherein step (c) comprises programming the second memory cell transistor to change the threshold voltage of the second memory cell transistor to a second extent to represent at least one other first bit of the data and another second bit of the data, wherein the programming comprises checking that the threshold voltage of the second memory cell has been sufficiently changed using the second verify voltage, and wherein step (e) of Determining a tendency to alter the threshold voltage of the second memory cell transistor comprises determining a change in the threshold voltage of the second memory cell transistor beyond the first circumference. The method of claim 5, wherein step (d) comprises programming the second memory cell transistor to change the threshold voltage of the second memory cell transistor within the first perimeter. The method of claim 6, wherein step (c) comprises: (i) applying a program pulse to the word line to change the threshold voltages of the first and second memory cell transistors; (ii) applying the first verify voltage to the wordline to verify that the threshold voltage of the first memory cell transistor has been sufficiently changed; and (iii) Applying the second verify voltage to the wordline to verify that the threshold voltage of the second memory cell transistor has been sufficiently changed. The method of claim 7, wherein steps (i), (ii) and (iii) are repeated at least with a number of repetitions if it is determined that the threshold voltage of at least one of the first and second memory cell transistors has not been sufficiently changed. The method of claim 3, wherein the first extent is a set of thresholds representing the first bit of the data in a state prior to programming the first memory cell with information of the second bit of the data. The method of claim 3, wherein step (c) comprises: (i) applying a program pulse to the word line to change the threshold voltage of the first memory cell transistor; (ii) applying a mean verify voltage to the wordline to verify that the threshold voltage of the first memory cell transistor has been raised to at least a middle level; and after determining the change in the threshold voltage of the first memory cell transistor beyond the first perimeter at step (a): (iii) applying a program pulse to the word line to change the threshold voltage of the first memory cell transistor; and (iv) applying the first verify voltage to the wordline to verify that the threshold voltage of the first memory cell transistor has been sufficiently changed. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ), comprising: bitlines; Word lines; a three-dimensional array of memory cells ( 110 . 210 . 310 . 410 ) having a plurality of memory cell rows, each memory cell row comprising a vertical stack of memory cells connected to a respective bitline and memory cells of different memory cell rows connected to a respective wordline; a page buffer ( 130 . 230 . 330 . 430 ) comprising data flip-flops and second flip-flops connected to respective bit lines, wherein data flip-flops are configured to store data; a voltage generator ( 150 . 250 . 350 . 450 ) configured to generate a programming voltage; a row decoder ( 120 . 220 . 320 . 420 ) configured to decode an address and select a word line; a control unit ( 160 . 260 . 360 . 460 ) configured to control a programming operation comprising programming a plurality of program loops, each program loop applying a program pulse to a word line provided by the row decoder ( 120 . 220 . 320 . 420 ), and a plurality of successive check operations for checking the respective program levels of a first row of memory cells connected to the selected word line, the data flip-flops of the page buffer (16) 130 . 230 . 330 . 430 ) are configured to suppress or allow a programming operation on respective first-row memory cells connected to bit lines of the respective data flip-flops, and wherein the second flip-flops are configured to generate a plurality of check results each of the plurality of program loop verification operations. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 11, wherein the control unit ( 160 . 260 . 360 . 460 ) is adapted to control a programming operation to modify a memory cell characteristic of each of the first-row memory cells to one of a plurality of program states, each program state representing a different one of one or more bits of the data. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 12, wherein the control unit ( 160 . 260 . 360 . 460 ) is adapted to perform a plurality of program loops each of which has a plurality of check operations for at least one of the program states. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 13, wherein the second flip-flops are reordering flip-flops and configured to store reordering data indicative of a charge reorder characteristic of the first row of the memory cells and to correspond to bitlines connected to the reordering flip-flop, one is selected from the plurality of check results based on the reorder data of the corresponding reordering flip-flops. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 14, wherein the control unit ( 160 . 260 . 360 . 460 ) is adapted to perform a state read operation on a program state of a least significant bit on the first row of memory cells for effectively generating and storing corresponding reorder data in corresponding reorder flip-flops to select one of the plurality of check results of least significant bits and additional bits are programmed into the first row of memory cells. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 14, wherein the control unit ( 160 . 260 . 360 . 460 ) is configured to perform a state read operation of a first program state that performs a first read with a first read voltage applied to the selected word line and a second read with a second read voltage higher than the first read voltage and on the selected word line wherein the first read voltage and the second read voltage have a magnitude within a threshold amount representing the first program state, wherein the reordering data of the reordering flip-flops comprises information of a result of the state read operation. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 16, wherein the control unit ( 160 . 260 . 360 . 460 ) determines that those memory cells of the first row of memory cells having an increasing threshold value of a charge reordering characteristic are those first row memory cells having a threshold voltage higher than the second read voltage and those memory cells of the first row of the memory cells having a decreasing charge reorder characteristic threshold, are first row memory cells having a threshold voltage lower than the first read voltage. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 17, wherein the control unit ( 160 . 260 . 360 . 460 ) is adapted to store data in the reordering flip-flops such that memory cells determined to have an increasing charge re-order characteristic threshold select test results of a first verify voltage of memory cells to be programmed in a second program state and in that memory cells determined to have a decreasing charge reordering threshold, select verification results of a second verify voltage that is higher than the first verify voltage of memory cells to be programmed into a second program state. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 16, wherein the control unit ( 160 . 260 . 360 . 460 ) is configured to generate the reordering data stored in the reordering flip-flops as a function of the result of the state read operation and as a function of a program operation of memory cells of a wordline adjacent to the selected wordline after the first row of the memory cells associated with the selected wordline has been programmed to include the first program state. Non-volatile memory device ( 100 . 200 . 300 . 400 . 1100 . 2100 . 3100 . 4100 ) according to claim 19, wherein the control unit ( 160 . 260 . 360 . 460 ) is adapted to generate the reordering data stored in the reordering flip-flops as a function of the result of the state read operation and as a function of a voltage threshold difference between memory cells of the selected wordline and adjacent memory cells of the adjacent wordline.

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