CN106856102B - Programming method for Nand Flash - Google Patents
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- CN106856102B CN106856102B CN201510895215.9A CN201510895215A CN106856102B CN 106856102 B CN106856102 B CN 106856102B CN 201510895215 A CN201510895215 A CN 201510895215A CN 106856102 B CN106856102 B CN 106856102B
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Abstract
The invention discloses a programming method of Nand Flash, which comprises the following steps: determining an initial programming voltage value to be applied to a current programming page based on a word line address, and performing pressure programming within a set time; determining an initial programming state of a current programming page for programming verification, and starting programming verification; if the programming verification fails, the current programming voltage is raised by a set step value, and then the programming verification is carried out; and repeating the current step until the program verification is successful, and stopping the programming operation. The invention can solve the problems of low programming speed and low programming precision of the existing programming method, greatly reduces the time consumption of the whole programming operation, greatly improves the programming speed and also effectively improves the programming precision of Nand Flash.
Description
Technical Field
The invention relates to the technical field of storage equipment hardware, in particular to a programming method of Nand Flash.
Background
The Nand Flash is one of Flash memories, has the advantages of large capacity, high rewriting speed and the like, and is suitable for storing a large amount of data. With the development of Nand Flash, the memory cells of Nand Flash gradually evolve from early Single-Level cells (SLC) to Multi-Level cells (MLC), Triple-Level cells (TLC), four-Level cells (Quad Level cells, QLC), and the like, and the increase of the memory Cell hierarchy of Nand Flash mainly results from the increase of the number of bits of the memory cells, and correspondingly, the bit states of Nand Flash particle memory cells are changed from 2 to 4, 8, or even 16.
When the Nand Flash is operated, after the Nand Flash finishes the erasing operation, if the bit of the storage unit is in the erasing state, the programming operation can be performed. For multi-bit Nand Flash particles, the programming operation can be divided into multiple steps, generally, a part of memory cells are programmed to an intermediate state in the first step, and the rest of memory cells in an erased state and memory cells in an intermediate state are programmed to corresponding programming states in the rest of steps. FIG. 1 is a schematic diagram showing the state change of a memory cell during a TLC Nand Flash particle programming operation, as shown in FIG. 1, after a first programming step, a part of the memory cell is in an erased state, and a part of the memory cell is in an intermediate state L1; after the program operation is performed again, the memory cells are in the corresponding program states, which can be referred to as P1, P2, P7.
For multi-bit Nand Flash particles, in the conventional programming method, when a selected programming page is programmed, after the selected programming page is programmed for the first time to reach an intermediate state, the selected programming page is programmed from an initial programming voltage for the second time, and after the selected programming page is programmed under pressure, the memory cell is verified from a 1 st programming state, and the programming operation seriously affects the programming speed and the programming precision, so that the correctness and the time for writing data by a user are directly affected.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a programming method for Nand Flash to improve the programming accuracy and the programming speed of a Nand Flash memory.
The embodiment of the invention provides a programming method of Nand Flash, which comprises the following steps:
determining an initial programming voltage value to be applied to a current programming page based on a word line address, and performing pressure programming within a set time;
determining an initial programming state of a current programming page for programming verification, and starting programming verification;
if the programming verification fails, the current programming voltage is raised by a set step value, and then the programming verification is carried out; and repeating the current step until the program verification is successful, and stopping the programming operation.
Further, the determining an initial program voltage value to be applied to the current program page based on the word line address specifically includes: judging whether the word line address of the current programming page and the word line address of the previous programming page belong to the same storage block or not, if so, directly applying the same initial programming voltage as the previous programming page to the current programming page; if not, determining the storage block to which the current programming page belongs, reading the information record of the storage block to which the current programming page belongs, and applying the initial programming voltage set in the information record to the current programming page.
Furthermore, the information records of all the storage blocks are stored in a logic register of Nand Flash in the form of an information table, wherein one storage block corresponds to one line of information records of the information table.
Further, the content of one line of information record corresponding to the one storage block is: the initial voltage value of the program-under-pressure and the initial program state of the program-verify.
Further, the one row of information records includes 1 initial voltage value of the press programming and n initial programming states of the program verification, where n is the number of word line segments of the memory block divided based on the word line address.
Furthermore, the number of the pages to be programmed in each word line segment is the same, and the initial programming state information of the program verification corresponding to the pages to be programmed in one word line segment is the same.
Further, the determining the initial programming state of the program verification of the current programming page specifically includes: determining a word line segment where a current programming page is located, and reading initial programming state information of programming verification corresponding to the word line segment.
Further, Nand Flash sets the information record of the memory block based on the history programming operation information.
Furthermore, the control unit of the Nand Flash controls the reading of the information record of the storage block.
Compared with the prior art, the programming method of the Nand Flash provided by the embodiment of the invention is based on the information recorded in advance, and directly carries out programming operation according to the initial programming voltage value in the information record and the initial programming state for carrying out programming verification when the current programming page is programmed. By using the method, the programming is not required to be started from the lowest voltage value and the programming verification is not required to be started from the initial programming state, so that the programming time is greatly saved, the programming precision and the programming speed of the Nand Flash are improved, and the influence on the time for writing in the Nand Flash and the correctness of the written data by a user is avoided.
Drawings
FIG. 1 is a schematic diagram of a change in state of a memory cell during a TLC Nand Flash particle programming operation;
FIG. 2 is a flowchart of a programming method of Nand Flash according to an embodiment of the present invention;
FIG. 3A is a flowchart of a programming method of Nand Flash according to a second embodiment of the present invention;
fig. 3B is a schematic diagram of a programming process of a programming method of Nand Flash in TLC Nand Flash according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings.
Example one
Fig. 2 is a flowchart of a programming method of Nand Flash according to an embodiment of the present invention, where the method is executed by Nand Flash and is an improvement of an existing programming method, and as shown in fig. 2, the method includes:
Generally, for the Nand Flash program operation, a word line is selected first, and then the program page of the selected word line is subjected to operations such as program-under-pressure and program-verify. In this embodiment, the word line address may refer to an address of a memory page formed by a memory cell array in Nand Flash, where a plurality of memory pages may form a memory block, that is, a plurality of programmable memory pages are provided in a memory block, and each memory page has a corresponding word line address. In addition, in the present embodiment, after the word line is selected, the program page is not directly programmed from the lowest program voltage, but an initial voltage value for programming is determined based on the word line address of the program page, and then the voltage is continuously applied to the program page for a set time.
Further, the initial programming voltage value to be applied to the current programming page is determined based on the word line address, specifically: judging whether the word line address of the current programming page and the word line address of the previous programming page belong to the same storage block or not, if so, directly applying the same initial programming voltage as the previous programming page to the current programming page; if not, determining the storage block to which the current programming page belongs, reading the information record of the storage block to which the current programming page belongs, and applying the initial programming voltage set in the information record to the current programming page.
In this embodiment, before the programming operation is performed on the current programming page, in order to save the time of the programming operation, the programming page does not need to be programmed for the first time, so that the programming state of the memory cells in the programming page is in an intermediate state, but before the programming operation, the optimal initial programming voltage value that can be applied to the current programming page is determined according to the information record corresponding to the memory block. The process of determining the initial programming voltage can be described simply as: judging whether the word line address of the current programming page and the word line address of the last programming page belong to the same memory block, if so, directly applying the same initial programming voltage as the last programming page to the current programming page, and continuously applying the programming voltage within a set time; if the current programming page does not belong to the same memory block, the memory block to which the word line address of the current programming page belongs needs to be determined, and then the information record of the memory block to which the current programming page belongs is read, so that the initial programming voltage value to be applied to the current programming page is determined. It should be noted that information of the initial programming voltage value that can be applied by the current programming page is recorded in the information record corresponding to the memory block to which the current programming page belongs.
Further, in this embodiment, the information records of all the storage blocks are stored in the logical register of NandFlash in the form of an information table, where one storage block corresponds to one line of information records of the information table.
Specifically, in order to improve the programming accuracy of Nand Flash and save the programming time, before the programming operation of Nand Flash starts, the magnitude of the initial programming voltage applied to the programming page and where to start the program verification should be recorded as reference values. Generally, the fluctuation of the initial programming voltage of the programming page in the same memory block is not large, so that the relevant information can be recorded by taking the memory block as a unit, and finally, the information records of all the memory blocks can be gathered into an information table and stored in a logic register of Nand Flash. In this embodiment, one memory block of Nand Flash corresponds to one line of information records in the information table. And the programming page of the selected word line can be subjected to pressure programming based on the initial programming voltage value required by the quick reading of the information record of the memory block.
Further, the content of one line of information record corresponding to the one storage block is: the initial voltage value of the program-under-pressure and the initial program state of the program-verify.
In this embodiment, the information record content in the information table may be specifically described as: the initial programming voltage value to be applied when all the pages to be programmed included in the current memory block are subjected to the pressure programming and the initial programming state of the program verification is performed when the program verification is started after the pressure programming.
For example, for a TLC Nand Flash memory, the existing programming method needs to first press program a programming page to make the Nand Flash memory cell bit state in an intermediate state, then press program the programming page again from the initial voltage value applied for the first time, and finally make the memory cell bit in a programming state to which the programming should be performed. By utilizing the improved programming method, before the programming page is subjected to pressure programming, only the information record corresponding to the memory block where the programming page is located needs to be read, and based on the initial programming voltage value information in the information record, the programming page can be subjected to direct pressure programming to enable the bit of the memory cell to be in the programming state to which the programming is required, so that the programming time is greatly saved.
In this embodiment, after the current programming page is subjected to the stress programming, it is necessary to verify whether the memory cells of the current programming page reach the ones that should be locatedThe programmed state. Generally, for multi-bit Nand Flash, a memory cell has multiple program states, which can be sequentially denoted as 1 st state, 2 nd state, and m th state, where m is the total number of program states that Nand Flash has, and m is denoted as m 2N1, N is the number of bits of the memory cell of Nand Flash. After the pressure programming, the existing programming method directly performs the programming verification on all the programming states from the 1 st state, and the programming method of the invention only needs to read the information record of the corresponding memory block of the programming page to determine from which programming state the programming page performs the programming verification.
Further, one row of information records includes 1 initial voltage value for the press programming and n initial programming states for the program verification, where n is the number of word line segments of the memory block divided based on the word line address.
In the present embodiment, one memory block corresponds to one row of information records in which 1 initial voltage value for the pressure programming and n initial program state information for the program verification are recorded in a binary form, where n is the number of word line segments into which the corresponding memory block is divided based on the word line address. Specifically, when setting information recording, 1 initial voltage value of pressure programming is set for one memory block; however, in order to ensure the programming accuracy in the programming operation, the initial program state information of a plurality of program verifications is often set. The setting operation is briefly described as follows: one memory block is equally divided into n groups of word line segments based on the word line segment address, and then 1 program verify start program state information is set for each group of word line segments. Thus, one row of information records in the information table includes n pieces of program-verified initial program state information.
Furthermore, the number of the pages to be programmed in each word line segment is the same, and the initial programming state information of the program verification corresponding to the pages to be programmed in one word line segment is the same.
Specifically, the memory blocks are equally divided based on the word line segment addresses, so that the number of pages to be programmed contained in each word line segment of the memory block is the same, and the initial programming states of the pages to be programmed in one word line segment for program verification after the page to be programmed in one word line segment is subjected to the pressurized programming are the same.
In this embodiment, after the memory blocks are equally divided based on the word line segment addresses, the initial program status information for performing program verification on the page to be programmed in each word line segment may be preferably set as: and starting programming state information when a programming page at the first bit of the word line segment is subjected to programming verification. It can also be understood that: the initial programming state information read when the program verification is started on the rest pages to be programmed in the word line segment is the same as the initial programming state information of the page to be programmed at the first bit of the word line segment.
Further, the determining the initial programming state of the program verification of the current programming page specifically includes: determining a word line segment where a current programming page is located, and reading initial programming state information of programming verification corresponding to the word line segment.
Specifically, if the word line address of the current programming page and the word line address of the previous programming page belong to the same memory block, after the initial programming voltage which is the same as that of the previous programming page is directly applied, determining which word line segment the word line address of the current programming page is in the memory block, and then performing programming verification according to the initial programming state information of the programming verification corresponding to the word line segment; if the current programming page and the last programming page do not belong to the same memory block, after the memory block of the current programming page is determined and the initial programming voltage information is read for pressure programming, the word line segment of the word line address of the current programming page is determined, and then the programming verification is carried out according to the initial programming state information of the programming verification corresponding to the word line segment.
In this embodiment, the end condition of the program operation is that the state of the memory cell bit in the current program page reaches the program state required by the program. Whether the bit of the memory cell reaches the programming state can be verified through programming verification, when the programming verification fails, the current programming page needs to be subjected to pressure programming again by using the set step value boosting voltage, the programming verification can be started again according to the initial programming state information of the corresponding programming verification after the pressure programming, and the programming operation can be stopped after the operation is repeated until the verification is successful.
In this embodiment, the Nand Flash sets the information record of the memory block based on the history programming operation information. Specifically, a program page of the memory block may be programmed based on an existing programming method, and information about the program operation of the program page needs to be recorded during the programming. The program operation information may be current program voltage information applied to a program page when a bit of a memory cell is in an intermediate state, and a verification result thereof is the most excellent when program verification is performed from which program state. According to the operation information, programming information more suitable for the programming operation can be set so as to be used when the operation is programmed again.
Furthermore, the control unit of the Nand Flash controls the reading of the information record of the storage block. Specifically, when the initial programming voltage value to be applied to the current programming page and the initial programming state of the current programming page for programming verification are determined, the reading operation of the information record is controlled by the control unit of Nand Flash.
The programming method of Nand Flash provided by the embodiment of the invention is improved, and before programming operation, an initial programming voltage value to be applied is determined based on a memory block where a programming page is located, and after pressure programming, initial programming state information for programming verification is determined based on a word line segment of the memory block where the programming page is located. By using the method, the time consumption of the whole programming operation can be greatly reduced, the programming speed is greatly improved, the programming precision of the Nand Flash is effectively improved, and the influence on the time for writing in the Nand Flash and the correctness of the written data by a user is avoided.
Example two
As shown in fig. 3A, a third embodiment of the present invention provides a preferred embodiment of a programming method for Nand Flash, and this embodiment describes in detail a programming method for Nand Flash according to the present invention based on TLC Nand Flash. A programming schematic diagram of the programming method provided in this embodiment is shown in fig. 3B, and the following specifically describes the programming operation process of fig. 3B with reference to fig. 3A, and as shown in fig. 3A, a flow schematic diagram of the programming operation performed in TLC Nand Flash by the method according to the embodiment of the present invention is provided, which specifically includes the following steps:
Illustratively, the TLC Nand Flash based control unit selects a word line to be programmed, thereby determining a current programming page.
Illustratively, the current programming page is a programming page obtained by selecting a word line in TLC Nand Flash. Before the program operation, whether the word line address of the current program page and the word line address of the program page in the last program operation belong to the same memory block is judged, thereby determining the initial program voltage value in the pressurization program.
In this embodiment, if the word line address of the current programming page and the word line address of the last programming page belong to the same memory block, step 203 is executed to directly apply the same initial programming voltage as the previous programming page. Specifically, the voltage pump is controlled by the control unit of the TLC Nand Flash to continuously apply the same voltage value as the last programming page to the programming page, and the control unit also controls the time for applying the voltage to the programming page by the voltage pump, and the voltage pump applies a high level voltage to the word line during the pressurization programming, and simultaneously keeps the bit line level of the programming page at 0.
In this embodiment, if the word line address of the current programming page and the word line address of the programming page in the last programming operation belong to the same memory block, step 204 is executed to determine the memory block of the current programming page, and then determine the initial programming voltage to be applied based on the information record of the memory block.
Specifically, in the present embodiment, the information record of the memory block in the TLC Nand Flash is set mainly based on the related information in the history programming operation of the TLC Nand Flash. When the TLC Nand Flash is programmed again, after a word line is selected to determine a programming page, a storage block to which the current programming page belongs is determined, and then a control unit based on the Nand Flash reads information records stored in an information table in a logic register, so that the initial programming voltage value of the current programming page is determined. The information table comprises information records of all the storage blocks of the TLC Nand Flash, one storage block corresponds to one line of information records in the information table, and the content of one line of information records comprises: 1 initial voltage value for the pressure programming and n initial program states for the program verification, n being the number of word line segments into which the memory block is divided based on the word line address. The initial voltage value of the press programming is used as the initial voltage value applied by the corresponding programming page; the starting program state of the program verify is used as the program state from which the program verify starts when the program verify is performed after the current program page is pressurized.
In this embodiment, when the initial voltage value of the current program page is determined, after the program-boosting is completed, the program verification needs to be performed on the current program page. The initial programming state of the program verification can be read from the information record of the memory block, before the initial programming state is read, the word line segment where the current programming page is located needs to be determined, and then the program verification initial programming state information corresponding to the word line segment where the current programming page is located needs to be read.
In this embodiment, the information record of one memory block contains n pieces of initial programming state information for program verification, that is, if one memory block is divided into n word line segments, each word line segment corresponds to one piece of initial programming state information. Therefore, when the current programming page reads the initial programming state information, the segment of the word line is determined. For example, in TLC Nand Flash, the memory cells have 3 bits, so the total number of programmed states m is 7, which can be respectively referred to as p1 at 1 st state, p2 at 2 nd state, p 3932 at i state, pi at i state, p7 at 7 th state, and if there are 128 pages to be programmed in one memory block of TLC Nand Flash, the word line addresses thereof can be represented as WL 0-WL 127. If the pages to be programmed are divided into 4 groups equally, the word lines may be divided into WL 0-WL 31, WL 32-WL 63, WL 64-WL 95, and WL 96-WL 127 by word line segment addresses. Based on the 4 groups of word line segments, the information records of the memory blocks are correspondingly set with 4 pieces of initial programming state information for programming verification. Preferably, when setting the initial programming state information, the initial programming state information of the first page to be programmed of each group of word line segments can be regarded as the initial programming state information of all pages to be programmed of the group, such as the pages to be programmed corresponding to WL 1-WL 31, and the programming state information can be regarded as the initial programming state information of the page to be programmed of WL0, so that the program verification can be started according to the initial programming state P4 recorded by the information.
In this embodiment, after determining the initial program state for program verification, program verification is started from that program state.
In the embodiment, the process of program verification checks whether the state of the bit of the memory cell is already in the state to which the program should be performed, and if the check result does not satisfy the program end condition, step 208 is performed, and if the program end condition is satisfied, step 209 may be performed.
In this embodiment, if the program verification does not satisfy the program end condition, the program voltage applied to the current program page needs to be raised. Generally, the programming voltage is raised by a set step value, which may be a fixed voltage increment value, and may preferably be any value from 0.5V to 1.5V.
When the above steps are completed, the program operation for the current program page may be stopped.
In the preferred embodiment of the programming method of Nand Flash according to the second embodiment of the present invention, after a word line of TLC Nand Flash is selected, an initial programming voltage value applied to a programming page of the selected word line is determined, after the program is pressed, an initial programming state at the time of program verification is determined, and the program verification is performed from the initial programming state. By using the method, the time consumption of the whole programming operation can be greatly reduced, the programming speed is greatly improved, the programming precision of the Nand Flash is effectively improved, and the influence on the time for writing in the Nand Flash and the correctness of the written data by a user is avoided.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (5)
1. A programming method of Nand Flash is characterized by comprising the following steps:
determining an initial programming voltage value to be applied to a current programming page based on a word line address, and performing pressure programming within a set time;
determining an initial programming state of a current programming page for programming verification, and starting programming verification;
if the programming verification fails, the current programming voltage is raised by a set step value, and then the programming verification is carried out; repeating the current step until the programming verification is successful, and stopping programming operation;
the determining of the initial programming voltage value to be applied to the current programming page based on the word line address specifically includes:
judging whether the word line address of the current programming page and the word line address of the previous programming page belong to the same storage block or not, if so, directly applying the same initial programming voltage as the previous programming page to the current programming page;
if not, determining the storage block to which the current programming page belongs, reading the information record of the storage block to which the current programming page belongs, and applying the initial programming voltage set in the information record to the current programming page;
the information record of the memory block comprises n initial programming states of programming verification, wherein n is the number of word line segments divided by the memory block based on the word line address; the number of pages to be programmed in each word line segment is the same, and the initial programming state information of the programming verification corresponding to the pages to be programmed in one word line segment is the same;
the determining of the initial programming state of the program verification of the current programming page specifically includes:
determining a word line segment where a current programming page is located, and reading initial programming state information of programming verification corresponding to the word line segment.
2. The method according to claim 1, wherein the information records of all memory blocks are stored in a logical register of Nand Flash in the form of an information table, wherein one memory block corresponds to one row of information records of the information table.
3. The method of claim 2, wherein the row of information records includes 1 force-programmed initial voltage value.
4. The method according to any one of claims 1 to 3, wherein the Nand Flash sets the information record of the memory block based on the history programming operation information.
5. Method according to any of claims 1 to 3, characterized in that the reading of the memory block information record is controlled by the control unit of Nand Flash.
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| CN111863081A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Method and device for controlling programming verification of NOR flash memory |
| CN111951860B (en) * | 2019-05-14 | 2022-10-18 | 兆易创新科技集团股份有限公司 | Nonvolatile memory write processing method and device |
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| KR100801035B1 (en) * | 2006-12-14 | 2008-02-04 | 삼성전자주식회사 | Method of programming multi-level cells, page buffer block and non-volatile memory device including the same |
| KR101263818B1 (en) * | 2007-06-19 | 2013-05-14 | 삼성전자주식회사 | Programming method of flash memory device |
| US7800956B2 (en) * | 2008-06-27 | 2010-09-21 | Sandisk Corporation | Programming algorithm to reduce disturb with minimal extra time penalty |
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| DE102012109612A1 (en) * | 2011-10-13 | 2013-04-18 | Samsung Electronics Co., Ltd. | Method for programming non-volatile memory e.g. programmable ROM, involves changing threshold voltage of first memory cell transistor via first peripheral |
| CN103811071B (en) * | 2012-11-15 | 2016-10-19 | 北京兆易创新科技股份有限公司 | The read method of a kind of high reliability NAND Flash and system thereof |
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-
2015
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Non-Patent Citations (1)
| Title |
|---|
| Predicting bad pages in NAND flash to improve read time: A dynamic programming approach;Haleh Tabrizi;《2015 IEEE International Conference on Communications (ICC)》;20150910;289-294 * |
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